| Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 1 | config CPU_INTEL_MODEL_206AX |
| 2 | bool |
| 3 | |
| Nico Huber | 772a154 | 2019-05-10 16:48:14 +0200 | [diff] [blame] | 4 | if CPU_INTEL_MODEL_206AX |
| Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 5 | |
| 6 | config CPU_SPECIFIC_OPTIONS |
| 7 | def_bool y |
| Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 8 | select ARCH_BOOTBLOCK_X86_32 |
| Stefan Reinauer | 77b1655 | 2015-01-14 19:51:47 +0100 | [diff] [blame] | 9 | select ARCH_VERSTAGE_X86_32 |
| Furquan Shaikh | 99ac98f | 2014-04-23 10:18:48 -0700 | [diff] [blame] | 10 | select ARCH_ROMSTAGE_X86_32 |
| 11 | select ARCH_RAMSTAGE_X86_32 |
| Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 12 | select SMP |
| Arthur Heymans | 7e6946a | 2019-01-21 17:55:02 +0100 | [diff] [blame] | 13 | select MMX |
| Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 14 | select SSE2 |
| Patrick Rudolph | b9959e2 | 2017-06-06 10:44:29 +0200 | [diff] [blame] | 15 | select UDELAY_TSC |
| 16 | select TSC_CONSTANT_RATE |
| 17 | select TSC_MONOTONIC_TIMER |
| Alexandru Gagniuc | 66e0c4c | 2013-12-04 22:21:15 -0600 | [diff] [blame] | 18 | select SUPPORT_CPU_UCODE_IN_CBFS |
| Sven Schnelle | 51676b1 | 2012-07-29 19:18:03 +0200 | [diff] [blame] | 19 | #select AP_IN_SIPI_WAIT |
| Stefan Reinauer | 0db6820 | 2012-08-07 14:44:51 -0700 | [diff] [blame] | 20 | select TSC_SYNC_MFENCE |
| Matt DeVillier | ed6fe2f | 2016-12-14 16:12:43 -0600 | [diff] [blame] | 21 | select CPU_INTEL_COMMON |
| Arthur Heymans | edbf5d9 | 2018-01-25 20:03:42 +0100 | [diff] [blame] | 22 | select PARALLEL_MP |
| Arthur Heymans | 74f9fe6 | 2019-04-24 12:29:44 +0200 | [diff] [blame] | 23 | select NO_FIXED_XIP_ROM_SIZE |
| Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 24 | |
| 25 | config BOOTBLOCK_CPU_INIT |
| 26 | string |
| 27 | default "cpu/intel/model_206ax/bootblock.c" |
| 28 | |
| Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 29 | config SMM_TSEG_SIZE |
| 30 | hex |
| 31 | default 0x800000 |
| 32 | |
| Arthur Heymans | 67031a5 | 2018-02-05 19:08:03 +0100 | [diff] [blame] | 33 | config SMM_RESERVED_SIZE |
| 34 | hex |
| 35 | default 0x100000 |
| 36 | |
| 37 | # Intel Enhanced Debug region must be 4MB |
| 38 | config IED_REGION_SIZE |
| 39 | hex |
| 40 | default 0x400000 |
| 41 | |
| Vadim Bendebury | 999e94c | 2012-06-19 04:20:20 +0000 | [diff] [blame] | 42 | endif |