Angel Pons | a2ee761 | 2020-04-04 18:51:15 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 2 | |
Aaron Durbin | bc98cc6 | 2015-09-02 09:21:36 -0500 | [diff] [blame] | 3 | #include <bootmode.h> |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <device/device.h> |
| 6 | #include <soc/nvidia/tegra/dc.h> |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 7 | #include <soc/display.h> |
Julius Werner | f0d21ff3 | 2014-10-20 13:24:14 -0700 | [diff] [blame] | 8 | #include <soc/sdram.h> |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 9 | #include <symbols.h> |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 10 | |
Julius Werner | f0d21ff3 | 2014-10-20 13:24:14 -0700 | [diff] [blame] | 11 | #include "chip.h" |
| 12 | |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 13 | /* this sucks, but for now, fb size/location are hardcoded. |
| 14 | * Will break if we get 2. Sigh. |
| 15 | * We assume it's all multiples of MiB for MMUs sake. |
| 16 | */ |
Furquan Shaikh | bcac1cb | 2020-05-13 12:19:15 -0700 | [diff] [blame] | 17 | static void soc_read_resources(struct device *dev) |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 18 | { |
Kyösti Mälkki | 7c60068 | 2022-07-01 18:50:26 +0300 | [diff] [blame] | 19 | uint64_t lcdbase = fb_base_mb(); |
| 20 | uint64_t fb_size = FB_SIZE_MB; |
Tom Warren | 64982c50 | 2014-01-23 13:37:50 -0700 | [diff] [blame] | 21 | |
Kyösti Mälkki | a08f509 | 2021-06-26 14:28:42 +0300 | [diff] [blame] | 22 | ram_from_to(dev, 0, (uintptr_t)_dram, (sdram_max_addressable_mb() - fb_size) * MiB); |
| 23 | mmio_range(dev, 1, lcdbase * MiB, fb_size * MiB); |
Gabe Black | 5cbbc70 | 2014-02-08 05:17:38 -0800 | [diff] [blame] | 24 | |
Kyösti Mälkki | 7c60068 | 2022-07-01 18:50:26 +0300 | [diff] [blame] | 25 | ram_from_to(dev, 2, sdram_max_addressable_mb() * (uint64_t)MiB, |
Kyösti Mälkki | a08f509 | 2021-06-26 14:28:42 +0300 | [diff] [blame] | 26 | (uintptr_t)_dram + sdram_size_mb() * (uint64_t)MiB); |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 27 | } |
| 28 | |
Elyes HAOUAS | 3fcb218 | 2018-05-25 10:03:57 +0200 | [diff] [blame] | 29 | static void soc_init(struct device *dev) |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 30 | { |
Aaron Durbin | bc98cc6 | 2015-09-02 09:21:36 -0500 | [diff] [blame] | 31 | if (display_init_required()) |
Gabe Black | 042f849 | 2014-03-31 21:01:14 -0700 | [diff] [blame] | 32 | display_startup(dev); |
Aaron Durbin | bc98cc6 | 2015-09-02 09:21:36 -0500 | [diff] [blame] | 33 | else |
| 34 | printk(BIOS_INFO, "Skipping display init.\n"); |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 35 | printk(BIOS_INFO, "CPU: Tegra124\n"); |
| 36 | } |
| 37 | |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 38 | static struct device_operations soc_ops = { |
Furquan Shaikh | bcac1cb | 2020-05-13 12:19:15 -0700 | [diff] [blame] | 39 | .read_resources = soc_read_resources, |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 40 | .set_resources = noop_set_resources, |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 41 | .init = soc_init, |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 42 | }; |
| 43 | |
Elyes HAOUAS | 3fcb218 | 2018-05-25 10:03:57 +0200 | [diff] [blame] | 44 | static void enable_tegra124_dev(struct device *dev) |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 45 | { |
| 46 | dev->ops = &soc_ops; |
| 47 | } |
| 48 | |
| 49 | struct chip_operations soc_nvidia_tegra124_ops = { |
Nicholas Sudsgaard | bfb11be | 2024-01-30 09:53:46 +0900 | [diff] [blame^] | 50 | .name = "SOC Nvidia Tegra124", |
Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 51 | .enable_dev = enable_tegra124_dev, |
| 52 | }; |