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Gabe Blackd40be112013-10-09 23:45:07 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
6 * Copyright 2013 Google Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
Gabe Blackd40be112013-10-09 23:45:07 -070016 */
17
Julius Wernerf0d21ff32014-10-20 13:24:14 -070018#include <arch/io.h>
Aaron Durbinbc98cc62015-09-02 09:21:36 -050019#include <bootmode.h>
Gabe Blackd40be112013-10-09 23:45:07 -070020#include <console/console.h>
21#include <device/device.h>
22#include <soc/nvidia/tegra/dc.h>
Tom Warren64982c502014-01-23 13:37:50 -070023#include <soc/display.h>
Julius Wernerf0d21ff32014-10-20 13:24:14 -070024#include <soc/sdram.h>
Julius Wernerec5e5e02014-08-20 15:29:56 -070025#include <symbols.h>
Gabe Blackd40be112013-10-09 23:45:07 -070026
Julius Wernerf0d21ff32014-10-20 13:24:14 -070027#include "chip.h"
28
Gabe Blackd40be112013-10-09 23:45:07 -070029/* this sucks, but for now, fb size/location are hardcoded.
30 * Will break if we get 2. Sigh.
31 * We assume it's all multiples of MiB for MMUs sake.
32 */
Elyes HAOUAS3fcb2182018-05-25 10:03:57 +020033static void soc_enable(struct device *dev)
Gabe Blackd40be112013-10-09 23:45:07 -070034{
Tom Warren64982c502014-01-23 13:37:50 -070035 u32 lcdbase = fb_base_mb();
Gabe Blackd40be112013-10-09 23:45:07 -070036 unsigned long fb_size = FB_SIZE_MB;
Tom Warren64982c502014-01-23 13:37:50 -070037
Julius Wernerec5e5e02014-08-20 15:29:56 -070038 ram_resource(dev, 0, (uintptr_t)_dram/KiB,
Gabe Black5cbbc702014-02-08 05:17:38 -080039 (sdram_max_addressable_mb() - fb_size)*KiB -
Julius Wernerec5e5e02014-08-20 15:29:56 -070040 (uintptr_t)_dram/KiB);
Gabe Blackd40be112013-10-09 23:45:07 -070041 mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB);
Gabe Black5cbbc702014-02-08 05:17:38 -080042
Julius Wernerec5e5e02014-08-20 15:29:56 -070043 u32 sdram_end_mb = sdram_size_mb() + (uintptr_t)_dram/MiB;
Gabe Black5cbbc702014-02-08 05:17:38 -080044
45 if (sdram_end_mb > sdram_max_addressable_mb())
46 ram_resource(dev, 2, sdram_max_addressable_mb()*KiB,
47 (sdram_end_mb - sdram_max_addressable_mb())*KiB);
Gabe Blackd40be112013-10-09 23:45:07 -070048}
49
Elyes HAOUAS3fcb2182018-05-25 10:03:57 +020050static void soc_init(struct device *dev)
Gabe Blackd40be112013-10-09 23:45:07 -070051{
Aaron Durbinbc98cc62015-09-02 09:21:36 -050052 if (display_init_required())
Gabe Black042f8492014-03-31 21:01:14 -070053 display_startup(dev);
Aaron Durbinbc98cc62015-09-02 09:21:36 -050054 else
55 printk(BIOS_INFO, "Skipping display init.\n");
Gabe Blackd40be112013-10-09 23:45:07 -070056 printk(BIOS_INFO, "CPU: Tegra124\n");
57}
58
Gabe Blackd40be112013-10-09 23:45:07 -070059static struct device_operations soc_ops = {
Edward O'Callaghan0625a8b2014-10-31 08:03:16 +110060 .read_resources = DEVICE_NOOP,
61 .set_resources = DEVICE_NOOP,
Gabe Blackd40be112013-10-09 23:45:07 -070062 .enable_resources = soc_enable,
63 .init = soc_init,
64 .scan_bus = 0,
65};
66
Elyes HAOUAS3fcb2182018-05-25 10:03:57 +020067static void enable_tegra124_dev(struct device *dev)
Gabe Blackd40be112013-10-09 23:45:07 -070068{
69 dev->ops = &soc_ops;
70}
71
72struct chip_operations soc_nvidia_tegra124_ops = {
73 CHIP_NAME("SOC Nvidia Tegra124")
74 .enable_dev = enable_tegra124_dev,
75};