blob: c38232daec642bd444a95f00716800ea549a1033 [file] [log] [blame]
Gabe Blackd40be112013-10-09 23:45:07 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2007-2009 coresystems GmbH
5 * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
6 * Copyright 2013 Google Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
Patrick Georgib890a122015-03-26 15:17:45 +010019 * Foundation, Inc.
Gabe Blackd40be112013-10-09 23:45:07 -070020 */
21
Julius Wernerf0d21ff32014-10-20 13:24:14 -070022#include <arch/io.h>
Aaron Durbinbc98cc62015-09-02 09:21:36 -050023#include <bootmode.h>
Gabe Blackd40be112013-10-09 23:45:07 -070024#include <console/console.h>
25#include <device/device.h>
26#include <soc/nvidia/tegra/dc.h>
Tom Warren64982c502014-01-23 13:37:50 -070027#include <soc/display.h>
Julius Wernerf0d21ff32014-10-20 13:24:14 -070028#include <soc/sdram.h>
Julius Wernerec5e5e02014-08-20 15:29:56 -070029#include <symbols.h>
Gabe Blackd40be112013-10-09 23:45:07 -070030
Julius Wernerf0d21ff32014-10-20 13:24:14 -070031#include "chip.h"
32
Gabe Blackd40be112013-10-09 23:45:07 -070033/* this sucks, but for now, fb size/location are hardcoded.
34 * Will break if we get 2. Sigh.
35 * We assume it's all multiples of MiB for MMUs sake.
36 */
37static void soc_enable(device_t dev)
38{
Tom Warren64982c502014-01-23 13:37:50 -070039 u32 lcdbase = fb_base_mb();
Gabe Blackd40be112013-10-09 23:45:07 -070040 unsigned long fb_size = FB_SIZE_MB;
Tom Warren64982c502014-01-23 13:37:50 -070041
Julius Wernerec5e5e02014-08-20 15:29:56 -070042 ram_resource(dev, 0, (uintptr_t)_dram/KiB,
Gabe Black5cbbc702014-02-08 05:17:38 -080043 (sdram_max_addressable_mb() - fb_size)*KiB -
Julius Wernerec5e5e02014-08-20 15:29:56 -070044 (uintptr_t)_dram/KiB);
Gabe Blackd40be112013-10-09 23:45:07 -070045 mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB);
Gabe Black5cbbc702014-02-08 05:17:38 -080046
Julius Wernerec5e5e02014-08-20 15:29:56 -070047 u32 sdram_end_mb = sdram_size_mb() + (uintptr_t)_dram/MiB;
Gabe Black5cbbc702014-02-08 05:17:38 -080048
49 if (sdram_end_mb > sdram_max_addressable_mb())
50 ram_resource(dev, 2, sdram_max_addressable_mb()*KiB,
51 (sdram_end_mb - sdram_max_addressable_mb())*KiB);
Gabe Blackd40be112013-10-09 23:45:07 -070052}
53
54static void soc_init(device_t dev)
55{
Aaron Durbinbc98cc62015-09-02 09:21:36 -050056 if (display_init_required())
Gabe Black042f8492014-03-31 21:01:14 -070057 display_startup(dev);
Aaron Durbinbc98cc62015-09-02 09:21:36 -050058 else
59 printk(BIOS_INFO, "Skipping display init.\n");
Gabe Blackd40be112013-10-09 23:45:07 -070060 printk(BIOS_INFO, "CPU: Tegra124\n");
61}
62
Gabe Blackd40be112013-10-09 23:45:07 -070063static struct device_operations soc_ops = {
Edward O'Callaghan0625a8b2014-10-31 08:03:16 +110064 .read_resources = DEVICE_NOOP,
65 .set_resources = DEVICE_NOOP,
Gabe Blackd40be112013-10-09 23:45:07 -070066 .enable_resources = soc_enable,
67 .init = soc_init,
68 .scan_bus = 0,
69};
70
71static void enable_tegra124_dev(device_t dev)
72{
73 dev->ops = &soc_ops;
74}
75
76struct chip_operations soc_nvidia_tegra124_ops = {
77 CHIP_NAME("SOC Nvidia Tegra124")
78 .enable_dev = enable_tegra124_dev,
79};