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Subrata Banik2871e0e2020-09-27 11:30:58 +05301/* SPDX-License-Identifier: GPL-2.0-only */
2
3/*
4 * This file is created based on Intel Alder Lake Processor CPU Datasheet
5 * Document number: 619501
6 * Chapter number: 14
7 */
8
Subrata Banik2871e0e2020-09-27 11:30:58 +05309#include <console/console.h>
10#include <device/pci.h>
Tim Wawrzynczak6cf79d92021-07-30 10:37:55 -060011#include <device/pci_ids.h>
Subrata Banik2871e0e2020-09-27 11:30:58 +053012#include <cpu/x86/mp.h>
13#include <cpu/x86/msr.h>
14#include <cpu/intel/smm_reloc.h>
15#include <cpu/intel/turbo.h>
Michael Niewöhner10ae1cf2020-10-11 14:05:32 +020016#include <cpu/intel/common/common.h>
Subrata Banik2871e0e2020-09-27 11:30:58 +053017#include <fsp/api.h>
18#include <intelblocks/cpulib.h>
19#include <intelblocks/mp_init.h>
20#include <intelblocks/msr.h>
Sridhar Siricilla23e2cde2022-01-14 19:20:15 +053021#include <intelblocks/acpi.h>
Subrata Banik2871e0e2020-09-27 11:30:58 +053022#include <soc/cpu.h>
23#include <soc/msr.h>
24#include <soc/pci_devs.h>
Subrata Banik2871e0e2020-09-27 11:30:58 +053025#include <soc/soc_chip.h>
Felix Heldd27ef5b2021-10-20 20:18:12 +020026#include <types.h>
Subrata Banik2871e0e2020-09-27 11:30:58 +053027
Sridhar Siricilla23e2cde2022-01-14 19:20:15 +053028enum alderlake_model {
29 ADL_MODEL_P_M = 0x9A,
30 ADL_MODEL_N = 0xBE,
31};
32
Subrata Banik56ab8e22022-01-07 13:40:19 +000033bool cpu_soc_is_in_untrusted_mode(void)
34{
35 msr_t msr;
36
37 msr = rdmsr(MSR_BIOS_DONE);
38 return !!(msr.lo & ENABLE_IA_UNTRUSTED);
39}
40
Subrata Banik37a55d12022-05-30 18:11:12 +000041void cpu_soc_bios_done(void)
42{
43 msr_t msr;
44
45 msr = rdmsr(MSR_BIOS_DONE);
46 msr.lo |= ENABLE_IA_UNTRUSTED;
47 wrmsr(MSR_BIOS_DONE, msr);
48}
49
Subrata Banik2871e0e2020-09-27 11:30:58 +053050static void soc_fsp_load(void)
51{
Kyösti Mälkkicc93c6e2021-01-09 22:53:52 +020052 fsps_load();
Subrata Banik2871e0e2020-09-27 11:30:58 +053053}
54
Subrata Banik2871e0e2020-09-27 11:30:58 +053055static void configure_misc(void)
56{
57 msr_t msr;
58
Tim Wawrzynczakb0d3a012021-12-02 16:19:29 -070059 const config_t *conf = config_of_soc();
Subrata Banik2871e0e2020-09-27 11:30:58 +053060
61 msr = rdmsr(IA32_MISC_ENABLE);
62 msr.lo |= (1 << 0); /* Fast String enable */
63 msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
64 wrmsr(IA32_MISC_ENABLE, msr);
65
66 /* Set EIST status */
67 cpu_set_eist(conf->eist_enable);
68
69 /* Disable Thermal interrupts */
70 msr.lo = 0;
71 msr.hi = 0;
72 wrmsr(IA32_THERM_INTERRUPT, msr);
73
74 /* Enable package critical interrupt only */
75 msr.lo = 1 << 4;
76 msr.hi = 0;
77 wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
78
Jeremy Compostella117770d2022-07-21 15:40:03 -070079 /* Enable PROCHOT and Energy/Performance Bias control */
Subrata Banik2871e0e2020-09-27 11:30:58 +053080 msr = rdmsr(MSR_POWER_CTL);
Angel Pons4d794bd2021-10-11 14:00:54 +020081 msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */
Subrata Banik2871e0e2020-09-27 11:30:58 +053082 msr.lo |= (1 << 23); /* Lock it */
Jeremy Compostella117770d2022-07-21 15:40:03 -070083 msr.lo |= (1 << 18); /* Energy/Performance Bias control */
Subrata Banik2871e0e2020-09-27 11:30:58 +053084 wrmsr(MSR_POWER_CTL, msr);
85}
86
Sridhar Siricilla23e2cde2022-01-14 19:20:15 +053087enum core_type get_soc_cpu_type(void)
88{
89 struct cpuinfo_x86 cpuinfo;
90
91 if (cpu_is_hybrid_supported())
92 return cpu_get_cpu_type();
93
94 get_fms(&cpuinfo, cpuid_eax(1));
95
96 if (cpuinfo.x86 == 0x6 && cpuinfo.x86_model == ADL_MODEL_N)
97 return CPUID_CORE_TYPE_INTEL_ATOM;
98 else
99 return CPUID_CORE_TYPE_INTEL_CORE;
100}
101
Sridahr Siricilla73b90c62021-11-11 01:10:16 +0530102bool soc_is_nominal_freq_supported(void)
103{
104 return true;
105}
106
Subrata Banik2871e0e2020-09-27 11:30:58 +0530107/* All CPUs including BSP will run the following function. */
108void soc_core_init(struct device *cpu)
109{
110 /* Clear out pending MCEs */
111 /* TODO(adurbin): This should only be done on a cold boot. Also, some
112 * of these banks are core vs package scope. For now every CPU clears
113 * every bank. */
114 mca_configure();
115
Subrata Banik2871e0e2020-09-27 11:30:58 +0530116 enable_lapic_tpr();
Subrata Banik2871e0e2020-09-27 11:30:58 +0530117
118 /* Configure Enhanced SpeedStep and Thermal Sensors */
119 configure_misc();
120
Subrata Banik2871e0e2020-09-27 11:30:58 +0530121 enable_pm_timer_emulation();
122
123 /* Enable Direct Cache Access */
124 configure_dca_cap();
125
Sridhar Siricilla44c1b5e2023-03-30 10:13:18 +0530126 /* Set core type in struct cpu_info */
127 set_dev_core_type();
128
Jeremy Compostellacd6a2ad2022-07-21 14:08:08 -0700129 /* Set energy policy. The "normal" EPB (6) is not suitable for Alder
130 * Lake or Raptor Lake CPUs, as this results in higher uncore power. */
131 set_energy_perf_bias(7);
Subrata Banik2871e0e2020-09-27 11:30:58 +0530132
Cliff Huang0bb22252022-03-07 18:42:13 -0800133 const config_t *conf = config_of_soc();
134 /* Set energy-performance preference */
135 if (conf->enable_energy_perf_pref)
136 if (check_energy_perf_cap())
137 set_energy_perf_pref(conf->energy_perf_pref_value);
Subrata Banik2871e0e2020-09-27 11:30:58 +0530138 /* Enable Turbo */
139 enable_turbo();
Subrata Banik069b6d02022-08-15 16:38:49 +0530140
Subrata Banik766bd002022-08-23 19:29:07 +0530141 if (CONFIG(INTEL_TME) && is_tme_supported())
Subrata Banik069b6d02022-08-15 16:38:49 +0530142 set_tme_core_activate();
Subrata Banik2871e0e2020-09-27 11:30:58 +0530143}
144
145static void per_cpu_smm_trigger(void)
146{
147 /* Relocate the SMM handler. */
148 smm_relocate();
149}
150
Cliff Huang0bb22252022-03-07 18:42:13 -0800151static void pre_mp_init(void)
152{
153 soc_fsp_load();
154
155 const config_t *conf = config_of_soc();
156 if (conf->enable_energy_perf_pref) {
157 if (check_energy_perf_cap())
158 enable_energy_perf_pref();
159 else
160 printk(BIOS_WARNING, "Energy Performance Preference not supported!\n");
161 }
162}
163
Subrata Banik2871e0e2020-09-27 11:30:58 +0530164static void post_mp_init(void)
165{
166 /* Set Max Ratio */
167 cpu_set_max_ratio();
168
169 /*
Kane Chen3aee3ad2021-05-04 09:53:38 +0800170 * 1. Now that all APs have been relocated as well as the BSP let SMIs
Subrata Banik2871e0e2020-09-27 11:30:58 +0530171 * start flowing.
Kane Chen3aee3ad2021-05-04 09:53:38 +0800172 * 2. Skip enabling power button SMI and enable it after BS_CHIPS_INIT
173 * to avoid shutdown hang due to lack of init on certain IP in FSP-S.
Subrata Banik2871e0e2020-09-27 11:30:58 +0530174 */
Kane Chen3aee3ad2021-05-04 09:53:38 +0800175 global_smi_enable_no_pwrbtn();
Subrata Banik2871e0e2020-09-27 11:30:58 +0530176}
177
178static const struct mp_ops mp_ops = {
179 /*
180 * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
181 * that are set prior to ramstage.
182 * Real MTRRs programming are being done after resource allocation.
183 */
Cliff Huang0bb22252022-03-07 18:42:13 -0800184 .pre_mp_init = pre_mp_init,
Subrata Banik2871e0e2020-09-27 11:30:58 +0530185 .get_cpu_count = get_cpu_count,
186 .get_smm_info = smm_info,
187 .get_microcode_info = get_microcode_info,
188 .pre_mp_smm_init = smm_initialize,
189 .per_cpu_smm_trigger = per_cpu_smm_trigger,
190 .relocation_handler = smm_relocation_handler,
191 .post_mp_init = post_mp_init,
192};
193
Arthur Heymans829e8e62023-01-30 19:09:34 +0100194void mp_init_cpus(struct bus *cpu_bus)
Subrata Banik2871e0e2020-09-27 11:30:58 +0530195{
Felix Held4dd7d112021-10-20 23:31:43 +0200196 /* TODO: Handle mp_init_with_smm failure? */
197 mp_init_with_smm(cpu_bus, &mp_ops);
Subrata Banik2871e0e2020-09-27 11:30:58 +0530198
199 /* Thermal throttle activation offset */
200 configure_tcc_thermal_target();
201}
Tim Wawrzynczak6cf79d92021-07-30 10:37:55 -0600202
203enum adl_cpu_type get_adl_cpu_type(void)
204{
205 const uint16_t adl_m_mch_ids[] = {
Felix Singer43b7f412022-03-07 04:34:52 +0100206 PCI_DID_INTEL_ADL_M_ID_1,
207 PCI_DID_INTEL_ADL_M_ID_2,
Tim Wawrzynczak6cf79d92021-07-30 10:37:55 -0600208 };
209 const uint16_t adl_p_mch_ids[] = {
Felix Singer43b7f412022-03-07 04:34:52 +0100210 PCI_DID_INTEL_ADL_P_ID_1,
211 PCI_DID_INTEL_ADL_P_ID_3,
212 PCI_DID_INTEL_ADL_P_ID_4,
213 PCI_DID_INTEL_ADL_P_ID_5,
214 PCI_DID_INTEL_ADL_P_ID_6,
215 PCI_DID_INTEL_ADL_P_ID_7,
216 PCI_DID_INTEL_ADL_P_ID_8,
217 PCI_DID_INTEL_ADL_P_ID_9,
218 PCI_DID_INTEL_ADL_P_ID_10
Tim Wawrzynczak6cf79d92021-07-30 10:37:55 -0600219 };
220 const uint16_t adl_s_mch_ids[] = {
Felix Singer43b7f412022-03-07 04:34:52 +0100221 PCI_DID_INTEL_ADL_S_ID_1,
222 PCI_DID_INTEL_ADL_S_ID_2,
223 PCI_DID_INTEL_ADL_S_ID_3,
224 PCI_DID_INTEL_ADL_S_ID_4,
225 PCI_DID_INTEL_ADL_S_ID_5,
226 PCI_DID_INTEL_ADL_S_ID_6,
227 PCI_DID_INTEL_ADL_S_ID_7,
228 PCI_DID_INTEL_ADL_S_ID_8,
229 PCI_DID_INTEL_ADL_S_ID_9,
230 PCI_DID_INTEL_ADL_S_ID_10,
231 PCI_DID_INTEL_ADL_S_ID_11,
232 PCI_DID_INTEL_ADL_S_ID_12,
233 PCI_DID_INTEL_ADL_S_ID_13,
234 PCI_DID_INTEL_ADL_S_ID_14,
235 PCI_DID_INTEL_ADL_S_ID_15,
Tim Wawrzynczak6cf79d92021-07-30 10:37:55 -0600236 };
237
Usha P93f50b32021-12-02 14:18:10 +0530238 const uint16_t adl_n_mch_ids[] = {
Felix Singer43b7f412022-03-07 04:34:52 +0100239 PCI_DID_INTEL_ADL_N_ID_1,
240 PCI_DID_INTEL_ADL_N_ID_2,
241 PCI_DID_INTEL_ADL_N_ID_3,
242 PCI_DID_INTEL_ADL_N_ID_4,
Usha P93f50b32021-12-02 14:18:10 +0530243 };
244
Tim Crawford53c6eea2023-07-07 09:59:56 -0600245 const uint16_t rpl_hx_mch_ids[] = {
246 PCI_DID_INTEL_RPL_HX_ID_1,
247 PCI_DID_INTEL_RPL_HX_ID_2,
248 PCI_DID_INTEL_RPL_HX_ID_3,
249 PCI_DID_INTEL_RPL_HX_ID_4,
250 PCI_DID_INTEL_RPL_HX_ID_5,
251 PCI_DID_INTEL_RPL_HX_ID_6,
252 PCI_DID_INTEL_RPL_HX_ID_7,
253 PCI_DID_INTEL_RPL_HX_ID_8,
254 };
255
Max Fritz573e6de2022-11-19 01:54:44 +0100256 const uint16_t rpl_s_mch_ids[] = {
257 PCI_DID_INTEL_RPL_S_ID_1,
258 PCI_DID_INTEL_RPL_S_ID_2,
259 PCI_DID_INTEL_RPL_S_ID_3,
260 PCI_DID_INTEL_RPL_S_ID_4,
261 PCI_DID_INTEL_RPL_S_ID_5
262 };
263
Bora Guvendika15b25f2022-02-28 14:43:49 -0800264 const uint16_t rpl_p_mch_ids[] = {
265 PCI_DID_INTEL_RPL_P_ID_1,
266 PCI_DID_INTEL_RPL_P_ID_2,
zhixingma529a64b2022-06-13 15:06:27 -0700267 PCI_DID_INTEL_RPL_P_ID_3,
Lawrence Chang0a5da512022-10-19 14:38:41 +0800268 PCI_DID_INTEL_RPL_P_ID_4,
Marx Wang39ede0a2022-12-20 10:48:33 +0800269 PCI_DID_INTEL_RPL_P_ID_5,
Bora Guvendika15b25f2022-02-28 14:43:49 -0800270 };
271
Tim Wawrzynczak6cf79d92021-07-30 10:37:55 -0600272 const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT),
273 PCI_FUNC(SA_DEVFN_ROOT)),
274 PCI_DEVICE_ID);
275
276 for (size_t i = 0; i < ARRAY_SIZE(adl_p_mch_ids); i++) {
277 if (adl_p_mch_ids[i] == mchid)
278 return ADL_P;
279 }
280
281 for (size_t i = 0; i < ARRAY_SIZE(adl_m_mch_ids); i++) {
282 if (adl_m_mch_ids[i] == mchid)
283 return ADL_M;
284 }
285
286 for (size_t i = 0; i < ARRAY_SIZE(adl_s_mch_ids); i++) {
287 if (adl_s_mch_ids[i] == mchid)
288 return ADL_S;
289 }
290
Max Fritz573e6de2022-11-19 01:54:44 +0100291 for (size_t i = 0; i < ARRAY_SIZE(rpl_s_mch_ids); i++) {
292 if (rpl_s_mch_ids[i] == mchid)
293 return RPL_S;
294 }
295
Usha P93f50b32021-12-02 14:18:10 +0530296 for (size_t i = 0; i < ARRAY_SIZE(adl_n_mch_ids); i++) {
297 if (adl_n_mch_ids[i] == mchid)
298 return ADL_N;
299 }
300
Tim Crawford53c6eea2023-07-07 09:59:56 -0600301 for (size_t i = 0; i < ARRAY_SIZE(rpl_hx_mch_ids); i++) {
302 if (rpl_hx_mch_ids[i] == mchid)
303 return RPL_HX;
304 }
305
Bora Guvendika15b25f2022-02-28 14:43:49 -0800306 for (size_t i = 0; i < ARRAY_SIZE(rpl_p_mch_ids); i++) {
307 if (rpl_p_mch_ids[i] == mchid)
308 return RPL_P;
309 }
310
Tim Wawrzynczak6cf79d92021-07-30 10:37:55 -0600311 return ADL_UNKNOWN;
312}
Tim Wawrzynczake2b8f302021-07-19 15:35:47 -0600313
314uint8_t get_supported_lpm_mask(void)
315{
316 enum adl_cpu_type type = get_adl_cpu_type();
317 switch (type) {
318 case ADL_M: /* fallthrough */
Usha P93f50b32021-12-02 14:18:10 +0530319 case ADL_N:
Tim Wawrzynczake2b8f302021-07-19 15:35:47 -0600320 case ADL_P:
Bora Guvendika15b25f2022-02-28 14:43:49 -0800321 case RPL_P:
Tim Wawrzynczake2b8f302021-07-19 15:35:47 -0600322 return LPM_S0i2_0 | LPM_S0i3_0;
323 case ADL_S:
Max Fritz573e6de2022-11-19 01:54:44 +0100324 case RPL_S:
Tim Crawford53c6eea2023-07-07 09:59:56 -0600325 case RPL_HX:
Tim Wawrzynczake2b8f302021-07-19 15:35:47 -0600326 return LPM_S0i2_0 | LPM_S0i2_1;
327 default:
328 printk(BIOS_ERR, "Unknown ADL CPU type: %d\n", type);
329 return 0;
330 }
331}