Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | /* |
| 4 | * This file is created based on Intel Alder Lake Processor CPU Datasheet |
| 5 | * Document number: 619501 |
| 6 | * Chapter number: 14 |
| 7 | */ |
| 8 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 9 | #include <console/console.h> |
| 10 | #include <device/pci.h> |
Tim Wawrzynczak | 6cf79d9 | 2021-07-30 10:37:55 -0600 | [diff] [blame^] | 11 | #include <device/pci_ids.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 12 | #include <cpu/x86/lapic.h> |
| 13 | #include <cpu/x86/mp.h> |
| 14 | #include <cpu/x86/msr.h> |
| 15 | #include <cpu/intel/smm_reloc.h> |
| 16 | #include <cpu/intel/turbo.h> |
Michael Niewöhner | 10ae1cf | 2020-10-11 14:05:32 +0200 | [diff] [blame] | 17 | #include <cpu/intel/common/common.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 18 | #include <fsp/api.h> |
| 19 | #include <intelblocks/cpulib.h> |
| 20 | #include <intelblocks/mp_init.h> |
| 21 | #include <intelblocks/msr.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 22 | #include <soc/cpu.h> |
| 23 | #include <soc/msr.h> |
| 24 | #include <soc/pci_devs.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 25 | #include <soc/soc_chip.h> |
| 26 | |
| 27 | static void soc_fsp_load(void) |
| 28 | { |
Kyösti Mälkki | cc93c6e | 2021-01-09 22:53:52 +0200 | [diff] [blame] | 29 | fsps_load(); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 30 | } |
| 31 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 32 | static void configure_misc(void) |
| 33 | { |
| 34 | msr_t msr; |
| 35 | |
| 36 | config_t *conf = config_of_soc(); |
| 37 | |
| 38 | msr = rdmsr(IA32_MISC_ENABLE); |
| 39 | msr.lo |= (1 << 0); /* Fast String enable */ |
| 40 | msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
| 41 | wrmsr(IA32_MISC_ENABLE, msr); |
| 42 | |
| 43 | /* Set EIST status */ |
| 44 | cpu_set_eist(conf->eist_enable); |
| 45 | |
| 46 | /* Disable Thermal interrupts */ |
| 47 | msr.lo = 0; |
| 48 | msr.hi = 0; |
| 49 | wrmsr(IA32_THERM_INTERRUPT, msr); |
| 50 | |
| 51 | /* Enable package critical interrupt only */ |
| 52 | msr.lo = 1 << 4; |
| 53 | msr.hi = 0; |
| 54 | wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| 55 | |
| 56 | /* Enable PROCHOT */ |
| 57 | msr = rdmsr(MSR_POWER_CTL); |
| 58 | msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ |
| 59 | msr.lo |= (1 << 23); /* Lock it */ |
| 60 | wrmsr(MSR_POWER_CTL, msr); |
| 61 | } |
| 62 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 63 | /* All CPUs including BSP will run the following function. */ |
| 64 | void soc_core_init(struct device *cpu) |
| 65 | { |
| 66 | /* Clear out pending MCEs */ |
| 67 | /* TODO(adurbin): This should only be done on a cold boot. Also, some |
| 68 | * of these banks are core vs package scope. For now every CPU clears |
| 69 | * every bank. */ |
| 70 | mca_configure(); |
| 71 | |
| 72 | /* Enable the local CPU apics */ |
| 73 | enable_lapic_tpr(); |
| 74 | setup_lapic(); |
| 75 | |
| 76 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 77 | configure_misc(); |
| 78 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 79 | enable_pm_timer_emulation(); |
| 80 | |
| 81 | /* Enable Direct Cache Access */ |
| 82 | configure_dca_cap(); |
| 83 | |
| 84 | /* Set energy policy */ |
| 85 | set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| 86 | |
| 87 | /* Enable Turbo */ |
| 88 | enable_turbo(); |
| 89 | } |
| 90 | |
| 91 | static void per_cpu_smm_trigger(void) |
| 92 | { |
| 93 | /* Relocate the SMM handler. */ |
| 94 | smm_relocate(); |
| 95 | } |
| 96 | |
| 97 | static void post_mp_init(void) |
| 98 | { |
| 99 | /* Set Max Ratio */ |
| 100 | cpu_set_max_ratio(); |
| 101 | |
| 102 | /* |
Kane Chen | 3aee3ad | 2021-05-04 09:53:38 +0800 | [diff] [blame] | 103 | * 1. Now that all APs have been relocated as well as the BSP let SMIs |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 104 | * start flowing. |
Kane Chen | 3aee3ad | 2021-05-04 09:53:38 +0800 | [diff] [blame] | 105 | * 2. Skip enabling power button SMI and enable it after BS_CHIPS_INIT |
| 106 | * to avoid shutdown hang due to lack of init on certain IP in FSP-S. |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 107 | */ |
Kane Chen | 3aee3ad | 2021-05-04 09:53:38 +0800 | [diff] [blame] | 108 | global_smi_enable_no_pwrbtn(); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 109 | } |
| 110 | |
| 111 | static const struct mp_ops mp_ops = { |
| 112 | /* |
| 113 | * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, |
| 114 | * that are set prior to ramstage. |
| 115 | * Real MTRRs programming are being done after resource allocation. |
| 116 | */ |
| 117 | .pre_mp_init = soc_fsp_load, |
| 118 | .get_cpu_count = get_cpu_count, |
| 119 | .get_smm_info = smm_info, |
| 120 | .get_microcode_info = get_microcode_info, |
| 121 | .pre_mp_smm_init = smm_initialize, |
| 122 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| 123 | .relocation_handler = smm_relocation_handler, |
| 124 | .post_mp_init = post_mp_init, |
| 125 | }; |
| 126 | |
| 127 | void soc_init_cpus(struct bus *cpu_bus) |
| 128 | { |
| 129 | if (mp_init_with_smm(cpu_bus, &mp_ops)) |
| 130 | printk(BIOS_ERR, "MP initialization failure.\n"); |
| 131 | |
| 132 | /* Thermal throttle activation offset */ |
| 133 | configure_tcc_thermal_target(); |
| 134 | } |
Tim Wawrzynczak | 6cf79d9 | 2021-07-30 10:37:55 -0600 | [diff] [blame^] | 135 | |
| 136 | enum adl_cpu_type get_adl_cpu_type(void) |
| 137 | { |
| 138 | const uint16_t adl_m_mch_ids[] = { |
| 139 | PCI_DEVICE_ID_INTEL_ADL_M_ID_1, |
| 140 | PCI_DEVICE_ID_INTEL_ADL_M_ID_2, |
| 141 | }; |
| 142 | const uint16_t adl_p_mch_ids[] = { |
| 143 | PCI_DEVICE_ID_INTEL_ADL_P_ID_1, |
| 144 | PCI_DEVICE_ID_INTEL_ADL_P_ID_3, |
| 145 | PCI_DEVICE_ID_INTEL_ADL_P_ID_4, |
| 146 | PCI_DEVICE_ID_INTEL_ADL_P_ID_5, |
| 147 | PCI_DEVICE_ID_INTEL_ADL_P_ID_6, |
| 148 | PCI_DEVICE_ID_INTEL_ADL_P_ID_7, |
| 149 | PCI_DEVICE_ID_INTEL_ADL_P_ID_8, |
| 150 | PCI_DEVICE_ID_INTEL_ADL_P_ID_9, |
| 151 | }; |
| 152 | const uint16_t adl_s_mch_ids[] = { |
| 153 | PCI_DEVICE_ID_INTEL_ADL_S_ID_1, |
| 154 | PCI_DEVICE_ID_INTEL_ADL_S_ID_2, |
| 155 | PCI_DEVICE_ID_INTEL_ADL_S_ID_3, |
| 156 | PCI_DEVICE_ID_INTEL_ADL_S_ID_4, |
| 157 | PCI_DEVICE_ID_INTEL_ADL_S_ID_5, |
| 158 | PCI_DEVICE_ID_INTEL_ADL_S_ID_6, |
| 159 | PCI_DEVICE_ID_INTEL_ADL_S_ID_7, |
| 160 | PCI_DEVICE_ID_INTEL_ADL_S_ID_8, |
| 161 | PCI_DEVICE_ID_INTEL_ADL_S_ID_9, |
| 162 | PCI_DEVICE_ID_INTEL_ADL_S_ID_10, |
| 163 | PCI_DEVICE_ID_INTEL_ADL_S_ID_11, |
| 164 | PCI_DEVICE_ID_INTEL_ADL_S_ID_12, |
| 165 | PCI_DEVICE_ID_INTEL_ADL_S_ID_13, |
| 166 | PCI_DEVICE_ID_INTEL_ADL_S_ID_14, |
| 167 | PCI_DEVICE_ID_INTEL_ADL_S_ID_15, |
| 168 | }; |
| 169 | |
| 170 | const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT), |
| 171 | PCI_FUNC(SA_DEVFN_ROOT)), |
| 172 | PCI_DEVICE_ID); |
| 173 | |
| 174 | for (size_t i = 0; i < ARRAY_SIZE(adl_p_mch_ids); i++) { |
| 175 | if (adl_p_mch_ids[i] == mchid) |
| 176 | return ADL_P; |
| 177 | } |
| 178 | |
| 179 | for (size_t i = 0; i < ARRAY_SIZE(adl_m_mch_ids); i++) { |
| 180 | if (adl_m_mch_ids[i] == mchid) |
| 181 | return ADL_M; |
| 182 | } |
| 183 | |
| 184 | for (size_t i = 0; i < ARRAY_SIZE(adl_s_mch_ids); i++) { |
| 185 | if (adl_s_mch_ids[i] == mchid) |
| 186 | return ADL_S; |
| 187 | } |
| 188 | |
| 189 | return ADL_UNKNOWN; |
| 190 | } |