Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | /* |
| 4 | * This file is created based on Intel Alder Lake Processor CPU Datasheet |
| 5 | * Document number: 619501 |
| 6 | * Chapter number: 14 |
| 7 | */ |
| 8 | |
| 9 | #include <arch/cpu.h> |
| 10 | #include <console/console.h> |
| 11 | #include <device/pci.h> |
| 12 | #include <cpu/x86/lapic.h> |
| 13 | #include <cpu/x86/mp.h> |
| 14 | #include <cpu/x86/msr.h> |
| 15 | #include <cpu/intel/smm_reloc.h> |
| 16 | #include <cpu/intel/turbo.h> |
Michael Niewöhner | 10ae1cf | 2020-10-11 14:05:32 +0200 | [diff] [blame^] | 17 | #include <cpu/intel/common/common.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 18 | #include <fsp/api.h> |
| 19 | #include <intelblocks/cpulib.h> |
| 20 | #include <intelblocks/mp_init.h> |
| 21 | #include <intelblocks/msr.h> |
| 22 | #include <romstage_handoff.h> |
| 23 | #include <soc/cpu.h> |
| 24 | #include <soc/msr.h> |
| 25 | #include <soc/pci_devs.h> |
| 26 | #include <soc/pm.h> |
| 27 | #include <soc/soc_chip.h> |
| 28 | |
| 29 | static void soc_fsp_load(void) |
| 30 | { |
| 31 | fsps_load(romstage_handoff_is_resume()); |
| 32 | } |
| 33 | |
| 34 | static void configure_isst(void) |
| 35 | { |
| 36 | config_t *conf = config_of_soc(); |
| 37 | msr_t msr; |
| 38 | |
| 39 | if (conf->speed_shift_enable) { |
| 40 | /* |
| 41 | * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP |
| 42 | * is supported or not. coreboot needs to configure MSR 0x1AA |
| 43 | * which is then reflected in the CPUID register. |
| 44 | */ |
| 45 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 46 | msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ |
| 47 | msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ |
| 48 | msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ |
| 49 | wrmsr(MSR_MISC_PWR_MGMT, msr); |
| 50 | } else { |
| 51 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 52 | msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ |
| 53 | msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ |
| 54 | msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ |
| 55 | wrmsr(MSR_MISC_PWR_MGMT, msr); |
| 56 | } |
| 57 | } |
| 58 | |
| 59 | static void configure_misc(void) |
| 60 | { |
| 61 | msr_t msr; |
| 62 | |
| 63 | config_t *conf = config_of_soc(); |
| 64 | |
| 65 | msr = rdmsr(IA32_MISC_ENABLE); |
| 66 | msr.lo |= (1 << 0); /* Fast String enable */ |
| 67 | msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
| 68 | wrmsr(IA32_MISC_ENABLE, msr); |
| 69 | |
| 70 | /* Set EIST status */ |
| 71 | cpu_set_eist(conf->eist_enable); |
| 72 | |
| 73 | /* Disable Thermal interrupts */ |
| 74 | msr.lo = 0; |
| 75 | msr.hi = 0; |
| 76 | wrmsr(IA32_THERM_INTERRUPT, msr); |
| 77 | |
| 78 | /* Enable package critical interrupt only */ |
| 79 | msr.lo = 1 << 4; |
| 80 | msr.hi = 0; |
| 81 | wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| 82 | |
| 83 | /* Enable PROCHOT */ |
| 84 | msr = rdmsr(MSR_POWER_CTL); |
| 85 | msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ |
| 86 | msr.lo |= (1 << 23); /* Lock it */ |
| 87 | wrmsr(MSR_POWER_CTL, msr); |
| 88 | } |
| 89 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 90 | static void enable_pm_timer_emulation(void) |
| 91 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 92 | msr_t msr; |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 93 | |
| 94 | if (!CONFIG_CPU_XTAL_HZ) |
| 95 | return; |
| 96 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 97 | /* |
| 98 | * The derived frequency is calculated as follows: |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 99 | * (clock * msr[63:32]) >> 32 = target frequency. |
| 100 | * Back solve the multiplier so the 3.579545MHz ACPI timer frequency is used. |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 101 | */ |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 102 | msr.hi = (3579545ULL << 32) / CONFIG_CPU_XTAL_HZ; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 103 | /* Set PM1 timer IO port and enable */ |
| 104 | msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | |
| 105 | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); |
| 106 | wrmsr(MSR_EMULATE_PM_TIMER, msr); |
| 107 | } |
| 108 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 109 | /* All CPUs including BSP will run the following function. */ |
| 110 | void soc_core_init(struct device *cpu) |
| 111 | { |
| 112 | /* Clear out pending MCEs */ |
| 113 | /* TODO(adurbin): This should only be done on a cold boot. Also, some |
| 114 | * of these banks are core vs package scope. For now every CPU clears |
| 115 | * every bank. */ |
| 116 | mca_configure(); |
| 117 | |
| 118 | /* Enable the local CPU apics */ |
| 119 | enable_lapic_tpr(); |
| 120 | setup_lapic(); |
| 121 | |
| 122 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 123 | configure_misc(); |
| 124 | |
| 125 | /* Configure Intel Speed Shift */ |
| 126 | configure_isst(); |
| 127 | |
| 128 | /* Enable PM timer emulation */ |
| 129 | enable_pm_timer_emulation(); |
| 130 | |
| 131 | /* Enable Direct Cache Access */ |
| 132 | configure_dca_cap(); |
| 133 | |
| 134 | /* Set energy policy */ |
| 135 | set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| 136 | |
| 137 | /* Enable Turbo */ |
| 138 | enable_turbo(); |
| 139 | } |
| 140 | |
| 141 | static void per_cpu_smm_trigger(void) |
| 142 | { |
| 143 | /* Relocate the SMM handler. */ |
| 144 | smm_relocate(); |
| 145 | } |
| 146 | |
| 147 | static void post_mp_init(void) |
| 148 | { |
| 149 | /* Set Max Ratio */ |
| 150 | cpu_set_max_ratio(); |
| 151 | |
| 152 | /* |
| 153 | * Now that all APs have been relocated as well as the BSP let SMIs |
| 154 | * start flowing. |
| 155 | */ |
| 156 | global_smi_enable(); |
| 157 | } |
| 158 | |
| 159 | static const struct mp_ops mp_ops = { |
| 160 | /* |
| 161 | * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, |
| 162 | * that are set prior to ramstage. |
| 163 | * Real MTRRs programming are being done after resource allocation. |
| 164 | */ |
| 165 | .pre_mp_init = soc_fsp_load, |
| 166 | .get_cpu_count = get_cpu_count, |
| 167 | .get_smm_info = smm_info, |
| 168 | .get_microcode_info = get_microcode_info, |
| 169 | .pre_mp_smm_init = smm_initialize, |
| 170 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| 171 | .relocation_handler = smm_relocation_handler, |
| 172 | .post_mp_init = post_mp_init, |
| 173 | }; |
| 174 | |
| 175 | void soc_init_cpus(struct bus *cpu_bus) |
| 176 | { |
| 177 | if (mp_init_with_smm(cpu_bus, &mp_ops)) |
| 178 | printk(BIOS_ERR, "MP initialization failure.\n"); |
| 179 | |
| 180 | /* Thermal throttle activation offset */ |
| 181 | configure_tcc_thermal_target(); |
| 182 | } |