Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
| 4 | #include <acpi/acpigen.h> |
Elyes Haouas | ad65e8c | 2022-10-31 14:02:13 +0100 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <cpu/cpu.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 7 | #include <cpu/intel/speedstep.h> |
| 8 | #include <cpu/intel/turbo.h> |
Elyes Haouas | ad65e8c | 2022-10-31 14:02:13 +0100 | [diff] [blame] | 9 | #include <cpu/x86/msr.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 10 | #include <device/device.h> |
Elyes Haouas | ad65e8c | 2022-10-31 14:02:13 +0100 | [diff] [blame] | 11 | #include <types.h> |
| 12 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 13 | #include "haswell.h" |
| 14 | #include "chip.h" |
| 15 | |
Duncan Laurie | 1ad5564 | 2013-03-07 14:08:04 -0800 | [diff] [blame] | 16 | #include <southbridge/intel/lynxpoint/pch.h> |
| 17 | |
Angel Pons | 618b9ad | 2021-01-21 21:22:19 +0100 | [diff] [blame] | 18 | #define MWAIT_RES(state, sub_state) \ |
| 19 | { \ |
| 20 | .addrl = (((state) << 4) | (sub_state)), \ |
| 21 | .space_id = ACPI_ADDRESS_SPACE_FIXED, \ |
| 22 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ |
| 23 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ |
| 24 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ |
| 25 | } |
| 26 | |
| 27 | static acpi_cstate_t cstate_map[NUM_C_STATES] = { |
| 28 | [C_STATE_C0] = { }, |
| 29 | [C_STATE_C1] = { |
| 30 | .latency = 0, |
| 31 | .power = 1000, |
| 32 | .resource = MWAIT_RES(0, 0), |
| 33 | }, |
| 34 | [C_STATE_C1E] = { |
| 35 | .latency = 0, |
| 36 | .power = 1000, |
| 37 | .resource = MWAIT_RES(0, 1), |
| 38 | }, |
| 39 | [C_STATE_C3] = { |
| 40 | .latency = C_STATE_LATENCY_FROM_LAT_REG(0), |
| 41 | .power = 900, |
| 42 | .resource = MWAIT_RES(1, 0), |
| 43 | }, |
| 44 | [C_STATE_C6_SHORT_LAT] = { |
| 45 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
| 46 | .power = 800, |
| 47 | .resource = MWAIT_RES(2, 0), |
| 48 | }, |
| 49 | [C_STATE_C6_LONG_LAT] = { |
| 50 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
| 51 | .power = 800, |
| 52 | .resource = MWAIT_RES(2, 1), |
| 53 | }, |
| 54 | [C_STATE_C7_SHORT_LAT] = { |
| 55 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
| 56 | .power = 700, |
| 57 | .resource = MWAIT_RES(3, 0), |
| 58 | }, |
| 59 | [C_STATE_C7_LONG_LAT] = { |
| 60 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
| 61 | .power = 700, |
| 62 | .resource = MWAIT_RES(3, 1), |
| 63 | }, |
| 64 | [C_STATE_C7S_SHORT_LAT] = { |
| 65 | .latency = C_STATE_LATENCY_FROM_LAT_REG(1), |
| 66 | .power = 700, |
| 67 | .resource = MWAIT_RES(3, 2), |
| 68 | }, |
| 69 | [C_STATE_C7S_LONG_LAT] = { |
| 70 | .latency = C_STATE_LATENCY_FROM_LAT_REG(2), |
| 71 | .power = 700, |
| 72 | .resource = MWAIT_RES(3, 3), |
| 73 | }, |
| 74 | [C_STATE_C8] = { |
| 75 | .latency = C_STATE_LATENCY_FROM_LAT_REG(3), |
| 76 | .power = 600, |
| 77 | .resource = MWAIT_RES(4, 0), |
| 78 | }, |
| 79 | [C_STATE_C9] = { |
| 80 | .latency = C_STATE_LATENCY_FROM_LAT_REG(4), |
| 81 | .power = 500, |
| 82 | .resource = MWAIT_RES(5, 0), |
| 83 | }, |
| 84 | [C_STATE_C10] = { |
| 85 | .latency = C_STATE_LATENCY_FROM_LAT_REG(5), |
| 86 | .power = 400, |
| 87 | .resource = MWAIT_RES(6, 0), |
| 88 | }, |
| 89 | }; |
| 90 | |
Angel Pons | e49dec4 | 2021-01-21 21:54:14 +0100 | [diff] [blame] | 91 | static const int cstate_set_s0ix[3] = { |
Angel Pons | 8e6f162 | 2020-10-29 00:18:11 +0100 | [diff] [blame] | 92 | C_STATE_C1E, |
| 93 | C_STATE_C7S_LONG_LAT, |
| 94 | C_STATE_C10, |
| 95 | }; |
| 96 | |
Angel Pons | e49dec4 | 2021-01-21 21:54:14 +0100 | [diff] [blame] | 97 | static const int cstate_set_lp[3] = { |
Angel Pons | bda1c55 | 2020-10-29 00:08:24 +0100 | [diff] [blame] | 98 | C_STATE_C1E, |
| 99 | C_STATE_C3, |
| 100 | C_STATE_C7S_LONG_LAT, |
Angel Pons | ba5761a | 2020-10-28 18:50:26 +0100 | [diff] [blame] | 101 | }; |
| 102 | |
Angel Pons | e49dec4 | 2021-01-21 21:54:14 +0100 | [diff] [blame] | 103 | static const int cstate_set_trad[3] = { |
Angel Pons | bda1c55 | 2020-10-29 00:08:24 +0100 | [diff] [blame] | 104 | C_STATE_C1, |
| 105 | C_STATE_C3, |
| 106 | C_STATE_C6_LONG_LAT, |
Angel Pons | ba5761a | 2020-10-28 18:50:26 +0100 | [diff] [blame] | 107 | }; |
| 108 | |
Angel Pons | 11235d6 | 2021-01-04 17:56:44 +0100 | [diff] [blame] | 109 | static int get_logical_cores_per_package(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 110 | { |
Angel Pons | 11235d6 | 2021-01-04 17:56:44 +0100 | [diff] [blame] | 111 | msr_t msr = rdmsr(MSR_CORE_THREAD_COUNT); |
| 112 | return msr.lo & 0xffff; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 113 | } |
| 114 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 115 | static acpi_tstate_t tss_table_fine[] = { |
| 116 | { 100, 1000, 0, 0x00, 0 }, |
| 117 | { 94, 940, 0, 0x1f, 0 }, |
| 118 | { 88, 880, 0, 0x1e, 0 }, |
| 119 | { 82, 820, 0, 0x1d, 0 }, |
| 120 | { 75, 760, 0, 0x1c, 0 }, |
| 121 | { 69, 700, 0, 0x1b, 0 }, |
| 122 | { 63, 640, 0, 0x1a, 0 }, |
| 123 | { 57, 580, 0, 0x19, 0 }, |
| 124 | { 50, 520, 0, 0x18, 0 }, |
| 125 | { 44, 460, 0, 0x17, 0 }, |
| 126 | { 38, 400, 0, 0x16, 0 }, |
| 127 | { 32, 340, 0, 0x15, 0 }, |
| 128 | { 25, 280, 0, 0x14, 0 }, |
| 129 | { 19, 220, 0, 0x13, 0 }, |
| 130 | { 13, 160, 0, 0x12, 0 }, |
| 131 | }; |
| 132 | |
| 133 | static acpi_tstate_t tss_table_coarse[] = { |
| 134 | { 100, 1000, 0, 0x00, 0 }, |
| 135 | { 88, 875, 0, 0x1f, 0 }, |
| 136 | { 75, 750, 0, 0x1e, 0 }, |
| 137 | { 63, 625, 0, 0x1d, 0 }, |
| 138 | { 50, 500, 0, 0x1c, 0 }, |
| 139 | { 38, 375, 0, 0x1b, 0 }, |
| 140 | { 25, 250, 0, 0x1a, 0 }, |
| 141 | { 13, 125, 0, 0x19, 0 }, |
| 142 | }; |
| 143 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 144 | static void generate_T_state_entries(int core, int cores_per_package) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 145 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 146 | /* Indicate SW_ALL coordination for T-states */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 147 | acpigen_write_TSD_package(core, cores_per_package, SW_ALL); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 148 | |
| 149 | /* Indicate FFixedHW so OS will use MSR */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 150 | acpigen_write_empty_PTC(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 151 | |
| 152 | /* Set a T-state limit that can be modified in NVS */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 153 | acpigen_write_TPC("\\TLVL"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 154 | |
| 155 | /* |
| 156 | * CPUID.(EAX=6):EAX[5] indicates support |
| 157 | * for extended throttle levels. |
| 158 | */ |
| 159 | if (cpuid_eax(6) & (1 << 5)) |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 160 | acpigen_write_TSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 161 | ARRAY_SIZE(tss_table_fine), tss_table_fine); |
| 162 | else |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 163 | acpigen_write_TSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 164 | ARRAY_SIZE(tss_table_coarse), tss_table_coarse); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 165 | } |
| 166 | |
Arthur Heymans | dd96ab6 | 2021-11-15 20:11:12 +0100 | [diff] [blame] | 167 | static bool is_s0ix_enabled(const struct device *dev) |
Angel Pons | 8e6f162 | 2020-10-29 00:18:11 +0100 | [diff] [blame] | 168 | { |
| 169 | if (!haswell_is_ult()) |
| 170 | return false; |
| 171 | |
Arthur Heymans | dd96ab6 | 2021-11-15 20:11:12 +0100 | [diff] [blame] | 172 | const struct cpu_intel_haswell_config *conf = dev->chip_info; |
Angel Pons | 8e6f162 | 2020-10-29 00:18:11 +0100 | [diff] [blame] | 173 | return conf->s0ix_enable; |
| 174 | } |
| 175 | |
Arthur Heymans | dd96ab6 | 2021-11-15 20:11:12 +0100 | [diff] [blame] | 176 | static void generate_C_state_entries(const struct device *dev) |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 177 | { |
Angel Pons | 618b9ad | 2021-01-21 21:22:19 +0100 | [diff] [blame] | 178 | acpi_cstate_t acpi_cstate_map[3] = {0}; |
Angel Pons | ba5761a | 2020-10-28 18:50:26 +0100 | [diff] [blame] | 179 | |
Angel Pons | e49dec4 | 2021-01-21 21:54:14 +0100 | [diff] [blame] | 180 | const int *acpi_cstates; |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 181 | |
Arthur Heymans | dd96ab6 | 2021-11-15 20:11:12 +0100 | [diff] [blame] | 182 | if (is_s0ix_enabled(dev)) |
Angel Pons | 618b9ad | 2021-01-21 21:22:19 +0100 | [diff] [blame] | 183 | acpi_cstates = cstate_set_s0ix; |
Angel Pons | 8e6f162 | 2020-10-29 00:18:11 +0100 | [diff] [blame] | 184 | else if (haswell_is_ult()) |
Angel Pons | 618b9ad | 2021-01-21 21:22:19 +0100 | [diff] [blame] | 185 | acpi_cstates = cstate_set_lp; |
Angel Pons | ba5761a | 2020-10-28 18:50:26 +0100 | [diff] [blame] | 186 | else |
Angel Pons | 618b9ad | 2021-01-21 21:22:19 +0100 | [diff] [blame] | 187 | acpi_cstates = cstate_set_trad; |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 188 | |
Angel Pons | 618b9ad | 2021-01-21 21:22:19 +0100 | [diff] [blame] | 189 | /* Count number of active C-states */ |
| 190 | int count = 0; |
| 191 | |
| 192 | for (int i = 0; i < ARRAY_SIZE(acpi_cstate_map); i++) { |
| 193 | if (acpi_cstates[i] > 0 && acpi_cstates[i] < ARRAY_SIZE(cstate_map)) { |
| 194 | acpi_cstate_map[count] = cstate_map[acpi_cstates[i]]; |
| 195 | acpi_cstate_map[count].ctype = i + 1; |
| 196 | count++; |
| 197 | } |
Angel Pons | ba5761a | 2020-10-28 18:50:26 +0100 | [diff] [blame] | 198 | } |
Angel Pons | 618b9ad | 2021-01-21 21:22:19 +0100 | [diff] [blame] | 199 | acpigen_write_CST_package(acpi_cstate_map, count); |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 200 | } |
| 201 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 202 | static int calculate_power(int tdp, int p1_ratio, int ratio) |
| 203 | { |
| 204 | u32 m; |
| 205 | u32 power; |
| 206 | |
| 207 | /* |
| 208 | * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 |
| 209 | * |
| 210 | * Power = (ratio / p1_ratio) * m * tdp |
| 211 | */ |
| 212 | |
| 213 | m = (110000 - ((p1_ratio - ratio) * 625)) / 11; |
| 214 | m = (m * m) / 1000; |
| 215 | |
| 216 | power = ((ratio * 100000 / p1_ratio) / 100); |
| 217 | power *= (m / 100) * (tdp / 1000); |
| 218 | power /= 1000; |
| 219 | |
| 220 | return (int)power; |
| 221 | } |
| 222 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 223 | static void generate_P_state_entries(int core, int cores_per_package) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 224 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 225 | int ratio_min, ratio_max, ratio_turbo, ratio_step; |
| 226 | int coord_type, power_max, power_unit, num_entries; |
| 227 | int ratio, power, clock, clock_max; |
| 228 | msr_t msr; |
| 229 | |
| 230 | /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ |
| 231 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 232 | if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) |
| 233 | coord_type = SW_ANY; |
| 234 | else |
| 235 | coord_type = HW_ALL; |
| 236 | |
| 237 | /* Get bus ratio limits and calculate clock speeds */ |
| 238 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 239 | ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ |
| 240 | |
| 241 | /* Determine if this CPU has configurable TDP */ |
| 242 | if (cpu_config_tdp_levels()) { |
| 243 | /* Set max ratio to nominal TDP ratio */ |
| 244 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 245 | ratio_max = msr.lo & 0xff; |
| 246 | } else { |
| 247 | /* Max Non-Turbo Ratio */ |
| 248 | ratio_max = (msr.lo >> 8) & 0xff; |
| 249 | } |
Angel Pons | ca96549 | 2020-10-28 19:15:36 +0100 | [diff] [blame] | 250 | clock_max = ratio_max * CPU_BCLK; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 251 | |
| 252 | /* Calculate CPU TDP in mW */ |
| 253 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 254 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 255 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 256 | power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; |
| 257 | |
| 258 | /* Write _PCT indicating use of FFixedHW */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 259 | acpigen_write_empty_PCT(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 260 | |
| 261 | /* Write _PPC with no limit on supported P-state */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 262 | acpigen_write_PPC_NVS(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 263 | |
| 264 | /* Write PSD indicating configured coordination type */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 265 | acpigen_write_PSD_package(core, 1, coord_type); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 266 | |
| 267 | /* Add P-state entries in _PSS table */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 268 | acpigen_write_name("_PSS"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 269 | |
| 270 | /* Determine ratio points */ |
| 271 | ratio_step = PSS_RATIO_STEP; |
| 272 | num_entries = (ratio_max - ratio_min) / ratio_step; |
| 273 | while (num_entries > PSS_MAX_ENTRIES-1) { |
| 274 | ratio_step <<= 1; |
| 275 | num_entries >>= 1; |
| 276 | } |
| 277 | |
| 278 | /* P[T] is Turbo state if enabled */ |
| 279 | if (get_turbo_state() == TURBO_ENABLED) { |
| 280 | /* _PSS package count including Turbo */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 281 | acpigen_write_package(num_entries + 2); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 282 | |
| 283 | msr = rdmsr(MSR_TURBO_RATIO_LIMIT); |
| 284 | ratio_turbo = msr.lo & 0xff; |
| 285 | |
| 286 | /* Add entry for Turbo ratio */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 287 | acpigen_write_PSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 288 | clock_max + 1, /*MHz*/ |
| 289 | power_max, /*mW*/ |
| 290 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 291 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 292 | ratio_turbo << 8, /*control*/ |
| 293 | ratio_turbo << 8); /*status*/ |
| 294 | } else { |
| 295 | /* _PSS package count without Turbo */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 296 | acpigen_write_package(num_entries + 1); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 297 | } |
| 298 | |
| 299 | /* First regular entry is max non-turbo ratio */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 300 | acpigen_write_PSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 301 | clock_max, /*MHz*/ |
| 302 | power_max, /*mW*/ |
| 303 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 304 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 305 | ratio_max << 8, /*control*/ |
| 306 | ratio_max << 8); /*status*/ |
| 307 | |
| 308 | /* Generate the remaining entries */ |
| 309 | for (ratio = ratio_min + ((num_entries - 1) * ratio_step); |
| 310 | ratio >= ratio_min; ratio -= ratio_step) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 311 | /* Calculate power at this ratio */ |
| 312 | power = calculate_power(power_max, ratio_max, ratio); |
Angel Pons | ca96549 | 2020-10-28 19:15:36 +0100 | [diff] [blame] | 313 | clock = ratio * CPU_BCLK; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 314 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 315 | acpigen_write_PSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 316 | clock, /*MHz*/ |
| 317 | power, /*mW*/ |
| 318 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 319 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 320 | ratio << 8, /*control*/ |
| 321 | ratio << 8); /*status*/ |
| 322 | } |
| 323 | |
| 324 | /* Fix package length */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 325 | acpigen_pop_len(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 326 | } |
| 327 | |
Kyösti Mälkki | d521b96 | 2023-04-12 21:44:49 +0300 | [diff] [blame] | 328 | static void generate_cpu_entry(const struct device *device, int cpu, int core, int cores_per_package) |
| 329 | { |
| 330 | /* Generate Scope(\_SB) { Device(CPUx */ |
| 331 | acpigen_write_processor_device(cpu * cores_per_package + core); |
| 332 | |
| 333 | /* Generate P-state tables */ |
| 334 | generate_P_state_entries(core, cores_per_package); |
| 335 | |
| 336 | /* Generate C-state tables */ |
| 337 | generate_C_state_entries(device); |
| 338 | |
| 339 | /* Generate T-state tables */ |
| 340 | generate_T_state_entries(cpu, cores_per_package); |
| 341 | |
| 342 | acpigen_write_processor_device_end(); |
| 343 | } |
| 344 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 345 | void generate_cpu_entries(const struct device *device) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 346 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 347 | int totalcores = dev_count_cpu(); |
Angel Pons | 11235d6 | 2021-01-04 17:56:44 +0100 | [diff] [blame] | 348 | int cores_per_package = get_logical_cores_per_package(); |
Kyösti Mälkki | e39a3e3 | 2023-04-12 16:39:12 +0300 | [diff] [blame] | 349 | int numcpus = totalcores / cores_per_package; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 350 | |
| 351 | printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", |
| 352 | numcpus, cores_per_package); |
| 353 | |
Kyösti Mälkki | d521b96 | 2023-04-12 21:44:49 +0300 | [diff] [blame] | 354 | for (int cpu_id = 0; cpu_id < numcpus; cpu_id++) |
| 355 | for (int core_id = 0; core_id < cores_per_package; core_id++) |
| 356 | generate_cpu_entry(device, cpu_id, core_id, cores_per_package); |
Arthur Heymans | c54d14f | 2018-11-28 12:09:23 +0100 | [diff] [blame] | 357 | |
| 358 | /* PPKG is usually used for thermal management |
| 359 | of the first and only package. */ |
| 360 | acpigen_write_processor_package("PPKG", 0, cores_per_package); |
| 361 | |
| 362 | /* Add a method to notify processor nodes */ |
| 363 | acpigen_write_processor_cnot(cores_per_package); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 364 | } |
| 365 | |
| 366 | struct chip_operations cpu_intel_haswell_ops = { |
Nicholas Sudsgaard | bfb11be | 2024-01-30 09:53:46 +0900 | [diff] [blame^] | 367 | .name = "Intel Haswell CPU", |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 368 | }; |