Angel Pons | f23ae0b | 2020-04-02 23:48:12 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 3 | |
| 4 | #include <types.h> |
| 5 | #include <console/console.h> |
| 6 | #include <arch/acpi.h> |
| 7 | #include <arch/acpigen.h> |
| 8 | #include <arch/cpu.h> |
| 9 | #include <cpu/x86/msr.h> |
| 10 | #include <cpu/intel/speedstep.h> |
| 11 | #include <cpu/intel/turbo.h> |
| 12 | #include <device/device.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 13 | #include "haswell.h" |
| 14 | #include "chip.h" |
| 15 | |
Duncan Laurie | 1ad5564 | 2013-03-07 14:08:04 -0800 | [diff] [blame] | 16 | #include <southbridge/intel/lynxpoint/pch.h> |
| 17 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 18 | static int get_cores_per_package(void) |
| 19 | { |
| 20 | struct cpuinfo_x86 c; |
| 21 | struct cpuid_result result; |
| 22 | int cores = 1; |
| 23 | |
| 24 | get_fms(&c, cpuid_eax(1)); |
| 25 | if (c.x86 != 6) |
| 26 | return 1; |
| 27 | |
| 28 | result = cpuid_ext(0xb, 1); |
| 29 | cores = result.ebx & 0xff; |
| 30 | |
| 31 | return cores; |
| 32 | } |
| 33 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 34 | static void generate_cstate_entries(acpi_cstate_t *cstates, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 35 | int c1, int c2, int c3) |
| 36 | { |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 37 | int cstate_count = 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 38 | |
| 39 | /* Count number of active C-states */ |
| 40 | if (c1 > 0) |
| 41 | ++cstate_count; |
| 42 | if (c2 > 0) |
| 43 | ++cstate_count; |
| 44 | if (c3 > 0) |
| 45 | ++cstate_count; |
| 46 | if (!cstate_count) |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 47 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 48 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 49 | acpigen_write_package(cstate_count + 1); |
| 50 | acpigen_write_byte(cstate_count); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 51 | |
| 52 | /* Add an entry if the level is enabled */ |
| 53 | if (c1 > 0) { |
| 54 | cstates[c1].ctype = 1; |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 55 | acpigen_write_CST_package_entry(&cstates[c1]); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 56 | } |
| 57 | if (c2 > 0) { |
| 58 | cstates[c2].ctype = 2; |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 59 | acpigen_write_CST_package_entry(&cstates[c2]); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 60 | } |
| 61 | if (c3 > 0) { |
| 62 | cstates[c3].ctype = 3; |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 63 | acpigen_write_CST_package_entry(&cstates[c3]); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 64 | } |
| 65 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 66 | acpigen_pop_len(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 67 | } |
| 68 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 69 | static void generate_C_state_entries(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 70 | { |
| 71 | struct cpu_info *info; |
| 72 | struct cpu_driver *cpu; |
Edward O'Callaghan | 2c9d2cf | 2014-10-27 23:29:29 +1100 | [diff] [blame] | 73 | struct device *lapic; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 74 | struct cpu_intel_haswell_config *conf = NULL; |
| 75 | |
| 76 | /* Find the SpeedStep CPU in the device tree using magic APIC ID */ |
| 77 | lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC); |
| 78 | if (!lapic) |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 79 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 80 | conf = lapic->chip_info; |
| 81 | if (!conf) |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 82 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 83 | |
| 84 | /* Find CPU map of supported C-states */ |
| 85 | info = cpu_info(); |
| 86 | if (!info) |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 87 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 88 | cpu = find_cpu_driver(info->cpu); |
| 89 | if (!cpu || !cpu->cstates) |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 90 | return; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 91 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 92 | acpigen_emit_byte(0x14); /* MethodOp */ |
| 93 | acpigen_write_len_f(); /* PkgLength */ |
| 94 | acpigen_emit_namestring("_CST"); |
| 95 | acpigen_emit_byte(0x00); /* No Arguments */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 96 | |
| 97 | /* If running on AC power */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 98 | acpigen_emit_byte(0xa0); /* IfOp */ |
| 99 | acpigen_write_len_f(); /* PkgLength */ |
| 100 | acpigen_emit_namestring("PWRS"); |
| 101 | acpigen_emit_byte(0xa4); /* ReturnOp */ |
| 102 | generate_cstate_entries(cpu->cstates, conf->c1_acpower, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 103 | conf->c2_acpower, conf->c3_acpower); |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 104 | acpigen_pop_len(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 105 | |
| 106 | /* Else on battery power */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 107 | acpigen_emit_byte(0xa4); /* ReturnOp */ |
| 108 | generate_cstate_entries(cpu->cstates, conf->c1_battery, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 109 | conf->c2_battery, conf->c3_battery); |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 110 | acpigen_pop_len(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 111 | } |
| 112 | |
| 113 | static acpi_tstate_t tss_table_fine[] = { |
| 114 | { 100, 1000, 0, 0x00, 0 }, |
| 115 | { 94, 940, 0, 0x1f, 0 }, |
| 116 | { 88, 880, 0, 0x1e, 0 }, |
| 117 | { 82, 820, 0, 0x1d, 0 }, |
| 118 | { 75, 760, 0, 0x1c, 0 }, |
| 119 | { 69, 700, 0, 0x1b, 0 }, |
| 120 | { 63, 640, 0, 0x1a, 0 }, |
| 121 | { 57, 580, 0, 0x19, 0 }, |
| 122 | { 50, 520, 0, 0x18, 0 }, |
| 123 | { 44, 460, 0, 0x17, 0 }, |
| 124 | { 38, 400, 0, 0x16, 0 }, |
| 125 | { 32, 340, 0, 0x15, 0 }, |
| 126 | { 25, 280, 0, 0x14, 0 }, |
| 127 | { 19, 220, 0, 0x13, 0 }, |
| 128 | { 13, 160, 0, 0x12, 0 }, |
| 129 | }; |
| 130 | |
| 131 | static acpi_tstate_t tss_table_coarse[] = { |
| 132 | { 100, 1000, 0, 0x00, 0 }, |
| 133 | { 88, 875, 0, 0x1f, 0 }, |
| 134 | { 75, 750, 0, 0x1e, 0 }, |
| 135 | { 63, 625, 0, 0x1d, 0 }, |
| 136 | { 50, 500, 0, 0x1c, 0 }, |
| 137 | { 38, 375, 0, 0x1b, 0 }, |
| 138 | { 25, 250, 0, 0x1a, 0 }, |
| 139 | { 13, 125, 0, 0x19, 0 }, |
| 140 | }; |
| 141 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 142 | static void generate_T_state_entries(int core, int cores_per_package) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 143 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 144 | /* Indicate SW_ALL coordination for T-states */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 145 | acpigen_write_TSD_package(core, cores_per_package, SW_ALL); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 146 | |
| 147 | /* Indicate FFixedHW so OS will use MSR */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 148 | acpigen_write_empty_PTC(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 149 | |
| 150 | /* Set a T-state limit that can be modified in NVS */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 151 | acpigen_write_TPC("\\TLVL"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 152 | |
| 153 | /* |
| 154 | * CPUID.(EAX=6):EAX[5] indicates support |
| 155 | * for extended throttle levels. |
| 156 | */ |
| 157 | if (cpuid_eax(6) & (1 << 5)) |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 158 | acpigen_write_TSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 159 | ARRAY_SIZE(tss_table_fine), tss_table_fine); |
| 160 | else |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 161 | acpigen_write_TSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 162 | ARRAY_SIZE(tss_table_coarse), tss_table_coarse); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 163 | } |
| 164 | |
| 165 | static int calculate_power(int tdp, int p1_ratio, int ratio) |
| 166 | { |
| 167 | u32 m; |
| 168 | u32 power; |
| 169 | |
| 170 | /* |
| 171 | * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 |
| 172 | * |
| 173 | * Power = (ratio / p1_ratio) * m * tdp |
| 174 | */ |
| 175 | |
| 176 | m = (110000 - ((p1_ratio - ratio) * 625)) / 11; |
| 177 | m = (m * m) / 1000; |
| 178 | |
| 179 | power = ((ratio * 100000 / p1_ratio) / 100); |
| 180 | power *= (m / 100) * (tdp / 1000); |
| 181 | power /= 1000; |
| 182 | |
| 183 | return (int)power; |
| 184 | } |
| 185 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 186 | static void generate_P_state_entries(int core, int cores_per_package) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 187 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 188 | int ratio_min, ratio_max, ratio_turbo, ratio_step; |
| 189 | int coord_type, power_max, power_unit, num_entries; |
| 190 | int ratio, power, clock, clock_max; |
| 191 | msr_t msr; |
| 192 | |
| 193 | /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ |
| 194 | msr = rdmsr(MSR_MISC_PWR_MGMT); |
| 195 | if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) |
| 196 | coord_type = SW_ANY; |
| 197 | else |
| 198 | coord_type = HW_ALL; |
| 199 | |
| 200 | /* Get bus ratio limits and calculate clock speeds */ |
| 201 | msr = rdmsr(MSR_PLATFORM_INFO); |
| 202 | ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ |
| 203 | |
| 204 | /* Determine if this CPU has configurable TDP */ |
| 205 | if (cpu_config_tdp_levels()) { |
| 206 | /* Set max ratio to nominal TDP ratio */ |
| 207 | msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); |
| 208 | ratio_max = msr.lo & 0xff; |
| 209 | } else { |
| 210 | /* Max Non-Turbo Ratio */ |
| 211 | ratio_max = (msr.lo >> 8) & 0xff; |
| 212 | } |
| 213 | clock_max = ratio_max * HASWELL_BCLK; |
| 214 | |
| 215 | /* Calculate CPU TDP in mW */ |
| 216 | msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 217 | power_unit = 2 << ((msr.lo & 0xf) - 1); |
| 218 | msr = rdmsr(MSR_PKG_POWER_SKU); |
| 219 | power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; |
| 220 | |
| 221 | /* Write _PCT indicating use of FFixedHW */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 222 | acpigen_write_empty_PCT(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 223 | |
| 224 | /* Write _PPC with no limit on supported P-state */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 225 | acpigen_write_PPC_NVS(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 226 | |
| 227 | /* Write PSD indicating configured coordination type */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 228 | acpigen_write_PSD_package(core, 1, coord_type); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 229 | |
| 230 | /* Add P-state entries in _PSS table */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 231 | acpigen_write_name("_PSS"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 232 | |
| 233 | /* Determine ratio points */ |
| 234 | ratio_step = PSS_RATIO_STEP; |
| 235 | num_entries = (ratio_max - ratio_min) / ratio_step; |
| 236 | while (num_entries > PSS_MAX_ENTRIES-1) { |
| 237 | ratio_step <<= 1; |
| 238 | num_entries >>= 1; |
| 239 | } |
| 240 | |
| 241 | /* P[T] is Turbo state if enabled */ |
| 242 | if (get_turbo_state() == TURBO_ENABLED) { |
| 243 | /* _PSS package count including Turbo */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 244 | acpigen_write_package(num_entries + 2); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 245 | |
| 246 | msr = rdmsr(MSR_TURBO_RATIO_LIMIT); |
| 247 | ratio_turbo = msr.lo & 0xff; |
| 248 | |
| 249 | /* Add entry for Turbo ratio */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 250 | acpigen_write_PSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 251 | clock_max + 1, /*MHz*/ |
| 252 | power_max, /*mW*/ |
| 253 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 254 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 255 | ratio_turbo << 8, /*control*/ |
| 256 | ratio_turbo << 8); /*status*/ |
| 257 | } else { |
| 258 | /* _PSS package count without Turbo */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 259 | acpigen_write_package(num_entries + 1); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 260 | } |
| 261 | |
| 262 | /* First regular entry is max non-turbo ratio */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 263 | acpigen_write_PSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 264 | clock_max, /*MHz*/ |
| 265 | power_max, /*mW*/ |
| 266 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 267 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 268 | ratio_max << 8, /*control*/ |
| 269 | ratio_max << 8); /*status*/ |
| 270 | |
| 271 | /* Generate the remaining entries */ |
| 272 | for (ratio = ratio_min + ((num_entries - 1) * ratio_step); |
| 273 | ratio >= ratio_min; ratio -= ratio_step) { |
| 274 | |
| 275 | /* Calculate power at this ratio */ |
| 276 | power = calculate_power(power_max, ratio_max, ratio); |
| 277 | clock = ratio * HASWELL_BCLK; |
| 278 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 279 | acpigen_write_PSS_package( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 280 | clock, /*MHz*/ |
| 281 | power, /*mW*/ |
| 282 | PSS_LATENCY_TRANSITION, /*lat1*/ |
| 283 | PSS_LATENCY_BUSMASTER, /*lat2*/ |
| 284 | ratio << 8, /*control*/ |
| 285 | ratio << 8); /*status*/ |
| 286 | } |
| 287 | |
| 288 | /* Fix package length */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 289 | acpigen_pop_len(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 290 | } |
| 291 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame^] | 292 | void generate_cpu_entries(const struct device *device) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 293 | { |
Duncan Laurie | 1ad5564 | 2013-03-07 14:08:04 -0800 | [diff] [blame] | 294 | int coreID, cpuID, pcontrol_blk = get_pmbase(), plen = 6; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 295 | int totalcores = dev_count_cpu(); |
| 296 | int cores_per_package = get_cores_per_package(); |
| 297 | int numcpus = totalcores/cores_per_package; |
| 298 | |
| 299 | printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", |
| 300 | numcpus, cores_per_package); |
| 301 | |
Martin Roth | 9944b28 | 2014-08-11 11:24:55 -0600 | [diff] [blame] | 302 | for (cpuID = 1; cpuID <= numcpus; cpuID++) { |
Lee Leahy | 9d62e7e | 2017-03-15 17:40:50 -0700 | [diff] [blame] | 303 | for (coreID = 1; coreID <= cores_per_package; coreID++) { |
| 304 | if (coreID > 1) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 305 | pcontrol_blk = 0; |
| 306 | plen = 0; |
| 307 | } |
| 308 | |
Christian Walter | be3979c | 2019-12-18 15:07:59 +0100 | [diff] [blame] | 309 | /* Generate processor \_SB.CPUx */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 310 | acpigen_write_processor( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 311 | (cpuID-1)*cores_per_package+coreID-1, |
| 312 | pcontrol_blk, plen); |
| 313 | |
| 314 | /* Generate P-state tables */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 315 | generate_P_state_entries( |
Duncan Laurie | 25b8b7b | 2013-04-19 10:02:23 -0700 | [diff] [blame] | 316 | coreID-1, cores_per_package); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 317 | |
| 318 | /* Generate C-state tables */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 319 | generate_C_state_entries(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 320 | |
| 321 | /* Generate T-state tables */ |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 322 | generate_T_state_entries( |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 323 | cpuID-1, cores_per_package); |
| 324 | |
Vladimir Serbinenko | be0fd0a | 2014-11-04 21:10:59 +0100 | [diff] [blame] | 325 | acpigen_pop_len(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 326 | } |
| 327 | } |
Arthur Heymans | c54d14f | 2018-11-28 12:09:23 +0100 | [diff] [blame] | 328 | |
| 329 | /* PPKG is usually used for thermal management |
| 330 | of the first and only package. */ |
| 331 | acpigen_write_processor_package("PPKG", 0, cores_per_package); |
| 332 | |
| 333 | /* Add a method to notify processor nodes */ |
| 334 | acpigen_write_processor_cnot(cores_per_package); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 335 | } |
| 336 | |
| 337 | struct chip_operations cpu_intel_haswell_ops = { |
| 338 | CHIP_NAME("Intel Haswell CPU") |
| 339 | }; |