cpu/intel/haswell: Factor out ACPI C-state values
There's no need to have them in the devicetree. ACPI generation can now
be simplified even further, and is done in subsequent commits.
Change-Id: I3a788423aee9be279797a1f7c60ab892a0af37e7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46908
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c
index b757dc6..d257d86 100644
--- a/src/cpu/intel/haswell/acpi.c
+++ b/src/cpu/intel/haswell/acpi.c
@@ -14,6 +14,18 @@
#include <southbridge/intel/lynxpoint/pch.h>
+static int cstate_set_lp[3] = {
+ 2,
+ 3,
+ 9,
+};
+
+static int cstate_set_trad[3] = {
+ 1,
+ 3,
+ 5,
+};
+
static int get_cores_per_package(void)
{
struct cpuinfo_x86 c;
@@ -30,41 +42,6 @@
return cores;
}
-static void generate_cstate_entries(acpi_cstate_t *cstates,
- int c1, int c2, int c3)
-{
- int cstate_count = 0;
-
- /* Count number of active C-states */
- if (c1 > 0)
- ++cstate_count;
- if (c2 > 0)
- ++cstate_count;
- if (c3 > 0)
- ++cstate_count;
- if (!cstate_count)
- return;
-
- acpigen_write_package(cstate_count + 1);
- acpigen_write_byte(cstate_count);
-
- /* Add an entry if the level is enabled */
- if (c1 > 0) {
- cstates[c1].ctype = 1;
- acpigen_write_CST_package_entry(&cstates[c1]);
- }
- if (c2 > 0) {
- cstates[c2].ctype = 2;
- acpigen_write_CST_package_entry(&cstates[c2]);
- }
- if (c3 > 0) {
- cstates[c3].ctype = 3;
- acpigen_write_CST_package_entry(&cstates[c3]);
- }
-
- acpigen_pop_len();
-}
-
static acpi_tstate_t tss_table_fine[] = {
{ 100, 1000, 0, 0x00, 0 },
{ 94, 940, 0, 0x1f, 0 },
@@ -119,18 +96,12 @@
static void generate_C_state_entries(void)
{
+ acpi_cstate_t map[3];
+ int *set;
+ int i;
+
struct cpu_info *info;
struct cpu_driver *cpu;
- struct device *lapic;
- struct cpu_intel_haswell_config *conf = NULL;
-
- /* Find the SpeedStep CPU in the device tree using magic APIC ID */
- lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
- if (!lapic)
- return;
- conf = lapic->chip_info;
- if (!conf)
- return;
/* Find CPU map of supported C-states */
info = cpu_info();
@@ -140,25 +111,18 @@
if (!cpu || !cpu->cstates)
return;
- acpigen_emit_byte(0x14); /* MethodOp */
- acpigen_write_len_f(); /* PkgLength */
- acpigen_emit_namestring("_CST");
- acpigen_emit_byte(0x00); /* No Arguments */
+ if (haswell_is_ult())
+ set = cstate_set_lp;
+ else
+ set = cstate_set_trad;
- /* If running on AC power */
- acpigen_emit_byte(0xa0); /* IfOp */
- acpigen_write_len_f(); /* PkgLength */
- acpigen_emit_namestring("PWRS");
- acpigen_emit_byte(0xa4); /* ReturnOp */
- generate_cstate_entries(cpu->cstates, conf->c1_acpower,
- conf->c2_acpower, conf->c3_acpower);
- acpigen_pop_len();
+ for (i = 0; i < ARRAY_SIZE(map); i++) {
+ map[i] = cpu->cstates[set[i]];
+ map[i].ctype = i + 1;
+ }
- /* Else on battery power */
- acpigen_emit_byte(0xa4); /* ReturnOp */
- generate_cstate_entries(cpu->cstates, conf->c1_battery,
- conf->c2_battery, conf->c3_battery);
- acpigen_pop_len();
+ /* Generate C-state tables */
+ acpigen_write_CST_package(map, ARRAY_SIZE(map));
}
static int calculate_power(int tdp, int p1_ratio, int ratio)