blob: 08e967dd8e3ba0a9d764861883b9e5b8091c1be7 [file] [log] [blame]
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +03001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030014 */
15
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030016#include <device/device.h>
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030017#include <device/pci.h>
18#include <device/pci_ids.h>
19#include <device/pci_ops.h>
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030020
Elyes HAOUASbf0970e2019-03-21 11:10:03 +010021#include "hudson.h"
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030022
23static void sata_init(struct device *dev)
24{
Julius Wernercd49cce2019-03-05 16:53:33 -080025#if CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) || CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030026 /**************************************
27 * Configure the SATA port multiplier *
28 **************************************/
29 #define BYTE_TO_DWORD_OFFSET(x) (x/4)
30 #define AHCI_BASE_ADDRESS_REG 0x24
31 #define MISC_CONTROL_REG 0x40
32 #define UNLOCK_BIT (1<<0)
33 #define SATA_CAPABILITIES_REG 0xFC
34 #define CFG_CAP_SPM (1<<12)
35
36 volatile u32 *ahci_ptr =
37 (u32*)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00);
38 u32 temp;
39
40 /* unlock the write-protect */
41 temp = pci_read_config32(dev, MISC_CONTROL_REG);
42 temp |= UNLOCK_BIT;
43 pci_write_config32(dev, MISC_CONTROL_REG, temp);
44
45 /* set the SATA AHCI mode to allow port expanders */
46 *(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) |= CFG_CAP_SPM;
47
48 /* lock the write-protect */
49 temp = pci_read_config32(dev, MISC_CONTROL_REG);
50 temp &= ~UNLOCK_BIT;
51 pci_write_config32(dev, MISC_CONTROL_REG, temp);
52#endif
53};
54
55static struct pci_operations lops_pci = {
56 /* .set_subsystem = pci_dev_set_subsystem, */
57};
58
59static struct device_operations sata_ops = {
60 .read_resources = pci_dev_read_resources,
61 .set_resources = pci_dev_set_resources,
62 .enable_resources = pci_dev_enable_resources,
63 .init = sata_init,
64 .scan_bus = 0,
65 .ops_pci = &lops_pci,
66};
67
WANG Siyuanf2dfef02015-05-20 14:41:01 +080068static const unsigned short pci_device_ids[] = {
Kyösti Mälkki9d9a5522016-11-19 22:14:59 +020069 PCI_DEVICE_ID_AMD_SB900_SATA,
70 PCI_DEVICE_ID_AMD_SB900_SATA_AHCI,
WANG Siyuanf2dfef02015-05-20 14:41:01 +080071 PCI_DEVICE_ID_AMD_CZ_SATA,
72 PCI_DEVICE_ID_AMD_CZ_SATA_AHCI,
73 0
74};
75
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030076static const struct pci_driver sata0_driver __pci_driver = {
77 .ops = &sata_ops,
78 .vendor = PCI_VENDOR_ID_AMD,
WANG Siyuanf2dfef02015-05-20 14:41:01 +080079 .devices = pci_device_ids,
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +030080};