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Kyösti Mälkkie8b4da22014-10-21 18:22:32 +03001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2010 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <console/console.h>
21#include <device/device.h>
22#include <delay.h>
23#include <device/pci.h>
24#include <device/pci_ids.h>
25#include <device/pci_ops.h>
26#include <arch/io.h>
27#include "hudson.h"
28
29
30static void sata_init(struct device *dev)
31{
32#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE)
33 /**************************************
34 * Configure the SATA port multiplier *
35 **************************************/
36 #define BYTE_TO_DWORD_OFFSET(x) (x/4)
37 #define AHCI_BASE_ADDRESS_REG 0x24
38 #define MISC_CONTROL_REG 0x40
39 #define UNLOCK_BIT (1<<0)
40 #define SATA_CAPABILITIES_REG 0xFC
41 #define CFG_CAP_SPM (1<<12)
42
43 volatile u32 *ahci_ptr =
44 (u32*)(pci_read_config32(dev, AHCI_BASE_ADDRESS_REG) & 0xFFFFFF00);
45 u32 temp;
46
47 /* unlock the write-protect */
48 temp = pci_read_config32(dev, MISC_CONTROL_REG);
49 temp |= UNLOCK_BIT;
50 pci_write_config32(dev, MISC_CONTROL_REG, temp);
51
52 /* set the SATA AHCI mode to allow port expanders */
53 *(ahci_ptr + BYTE_TO_DWORD_OFFSET(SATA_CAPABILITIES_REG)) |= CFG_CAP_SPM;
54
55 /* lock the write-protect */
56 temp = pci_read_config32(dev, MISC_CONTROL_REG);
57 temp &= ~UNLOCK_BIT;
58 pci_write_config32(dev, MISC_CONTROL_REG, temp);
59#endif
60};
61
62static struct pci_operations lops_pci = {
63 /* .set_subsystem = pci_dev_set_subsystem, */
64};
65
66static struct device_operations sata_ops = {
67 .read_resources = pci_dev_read_resources,
68 .set_resources = pci_dev_set_resources,
69 .enable_resources = pci_dev_enable_resources,
70 .init = sata_init,
71 .scan_bus = 0,
72 .ops_pci = &lops_pci,
73};
74
75static const struct pci_driver sata0_driver __pci_driver = {
76 .ops = &sata_ops,
77 .vendor = PCI_VENDOR_ID_AMD,
78 .device = PCI_DEVICE_ID_ATI_SB900_SATA,
79};
80
81static const struct pci_driver sata0_driver_ahci __pci_driver = {
82 .ops = &sata_ops,
83 .vendor = PCI_VENDOR_ID_AMD,
84 .device = PCI_DEVICE_ID_ATI_SB900_SATA_AHCI,
85};