Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 3 | #include <commonlib/helpers.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 4 | #include <console/console.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 5 | #include <acpi/acpi.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 6 | #include <stdint.h> |
| 7 | #include <delay.h> |
| 8 | #include <cpu/intel/haswell/haswell.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 9 | #include <device/device.h> |
| 10 | #include <device/pci.h> |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 11 | #include <device/pci_def.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 12 | #include <device/pci_ids.h> |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 13 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 14 | #include <boot/tables.h> |
Angel Pons | 4b290b7 | 2020-09-24 23:38:53 +0200 | [diff] [blame] | 15 | #include <security/intel/txt/txt_register.h> |
Angel Pons | e2ec60f | 2021-01-26 19:18:09 +0100 | [diff] [blame] | 16 | #include <southbridge/intel/lynxpoint/pch.h> |
Kyösti Mälkki | b8b4133 | 2021-02-10 19:11:55 +0200 | [diff] [blame^] | 17 | #include <vendorcode/google/chromeos/chromeos.h> |
Elyes HAOUAS | a1e22b8 | 2019-03-18 22:49:36 +0100 | [diff] [blame] | 18 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 19 | #include "chip.h" |
| 20 | #include "haswell.h" |
| 21 | |
Tristan Corrick | f3127d4 | 2018-10-31 02:25:54 +1300 | [diff] [blame] | 22 | static const char *northbridge_acpi_name(const struct device *dev) |
| 23 | { |
| 24 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 25 | return "PCI0"; |
| 26 | |
| 27 | if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) |
| 28 | return NULL; |
| 29 | |
| 30 | switch (dev->path.pci.devfn) { |
| 31 | case PCI_DEVFN(0, 0): |
| 32 | return "MCHC"; |
| 33 | } |
| 34 | |
| 35 | return NULL; |
| 36 | } |
| 37 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 38 | /* |
| 39 | * TODO: We could determine how many PCIe busses we need in the bar. |
| 40 | * For now, that number is hardcoded to a max of 64. |
| 41 | */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 42 | static struct device_operations pci_domain_ops = { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 43 | .read_resources = pci_domain_read_resources, |
| 44 | .set_resources = pci_domain_set_resources, |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 45 | .scan_bus = pci_domain_scan_bus, |
| 46 | .acpi_name = northbridge_acpi_name, |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 47 | .write_acpi_tables = northbridge_write_acpi_tables, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 48 | }; |
| 49 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 50 | static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 51 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 52 | u32 bar = pci_read_config32(dev, index); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 53 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 54 | /* If not enabled don't report it */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 55 | if (!(bar & 0x1)) |
| 56 | return 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 57 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 58 | /* Knock down the enable bit */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 59 | *base = bar & ~1; |
| 60 | |
| 61 | return 1; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 62 | } |
| 63 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 64 | /* |
| 65 | * There are special BARs that actually are programmed in the MCHBAR. These Intel special |
| 66 | * features, but they do consume resources that need to be accounted for. |
| 67 | */ |
| 68 | static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 69 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 70 | u32 bar = MCHBAR32(index); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 71 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 72 | /* If not enabled don't report it */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 73 | if (!(bar & 0x1)) |
| 74 | return 0; |
| 75 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 76 | /* Knock down the enable bit */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 77 | *base = bar & ~1; |
| 78 | |
| 79 | return 1; |
| 80 | } |
| 81 | |
| 82 | struct fixed_mmio_descriptor { |
| 83 | unsigned int index; |
| 84 | u32 size; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 85 | int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 86 | const char *description; |
| 87 | }; |
| 88 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 89 | #define SIZE_KB(x) ((x) * 1024) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 90 | struct fixed_mmio_descriptor mc_fixed_resources[] = { |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 91 | { MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" }, |
| 92 | { DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" }, |
| 93 | { EPBAR, SIZE_KB(4), get_bar, "EPBAR" }, |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 94 | { GDXCBAR, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, |
| 95 | { EDRAMBAR, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 96 | }; |
| 97 | #undef SIZE_KB |
| 98 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 99 | /* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */ |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 100 | static void mc_add_fixed_mmio_resources(struct device *dev) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 101 | { |
| 102 | int i; |
| 103 | |
| 104 | for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { |
| 105 | u32 base; |
| 106 | u32 size; |
| 107 | struct resource *resource; |
| 108 | unsigned int index; |
| 109 | |
| 110 | size = mc_fixed_resources[i].size; |
| 111 | index = mc_fixed_resources[i].index; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 112 | if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size)) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 113 | continue; |
| 114 | |
| 115 | resource = new_resource(dev, mc_fixed_resources[i].index); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 116 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | |
| 117 | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; |
| 118 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 119 | resource->base = base; |
| 120 | resource->size = size; |
| 121 | printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", |
| 122 | __func__, mc_fixed_resources[i].description, index, |
| 123 | (unsigned long)base, (unsigned long)(base + size - 1)); |
| 124 | } |
Angel Pons | 32770f8 | 2021-01-20 15:03:30 +0100 | [diff] [blame] | 125 | |
| 126 | mmconf_resource(dev, PCIEXBAR); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 127 | } |
| 128 | |
Angel Pons | 4b290b7 | 2020-09-24 23:38:53 +0200 | [diff] [blame] | 129 | /* |
| 130 | * Host Memory Map: |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 131 | * |
| 132 | * +--------------------------+ TOUUD |
| 133 | * | | |
| 134 | * +--------------------------+ 4GiB |
| 135 | * | PCI Address Space | |
| 136 | * +--------------------------+ TOLUD (also maps into MC address space) |
| 137 | * | iGD | |
| 138 | * +--------------------------+ BDSM |
| 139 | * | GTT | |
| 140 | * +--------------------------+ BGSM |
| 141 | * | TSEG | |
| 142 | * +--------------------------+ TSEGMB |
Angel Pons | 4b290b7 | 2020-09-24 23:38:53 +0200 | [diff] [blame] | 143 | * | DPR | |
| 144 | * +--------------------------+ (DPR top - DPR size) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 145 | * | Usage DRAM | |
| 146 | * +--------------------------+ 0 |
| 147 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 148 | * Some of the base registers above can be equal, making the size of the regions within 0. |
| 149 | * This is because the memory controller internally subtracts the base registers from each |
| 150 | * other to determine sizes of the regions. In other words, the memory map regions are always |
| 151 | * in a fixed order, no matter what sizes they have. |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 152 | */ |
| 153 | |
| 154 | struct map_entry { |
| 155 | int reg; |
| 156 | int is_64_bit; |
| 157 | int is_limit; |
| 158 | const char *description; |
| 159 | }; |
| 160 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 161 | static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 162 | { |
| 163 | uint64_t value; |
| 164 | uint64_t mask; |
| 165 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 166 | /* All registers have a 1MiB granularity */ |
| 167 | mask = ((1ULL << 20) - 1); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 168 | mask = ~mask; |
| 169 | |
| 170 | value = 0; |
| 171 | |
| 172 | if (entry->is_64_bit) { |
| 173 | value = pci_read_config32(dev, entry->reg + 4); |
| 174 | value <<= 32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 175 | } |
| 176 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 177 | value |= pci_read_config32(dev, entry->reg); |
| 178 | value &= mask; |
| 179 | |
| 180 | if (entry->is_limit) |
| 181 | value |= ~mask; |
| 182 | |
| 183 | *result = value; |
| 184 | } |
| 185 | |
| 186 | #define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ |
| 187 | { \ |
| 188 | .reg = reg_, \ |
| 189 | .is_64_bit = is_64_, \ |
| 190 | .is_limit = is_limit_, \ |
| 191 | .description = desc_, \ |
| 192 | } |
| 193 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 194 | #define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_) |
| 195 | #define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_) |
| 196 | #define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 197 | |
| 198 | enum { |
| 199 | TOM_REG, |
| 200 | TOUUD_REG, |
| 201 | MESEG_BASE_REG, |
| 202 | MESEG_LIMIT_REG, |
| 203 | REMAP_BASE_REG, |
| 204 | REMAP_LIMIT_REG, |
| 205 | TOLUD_REG, |
| 206 | BGSM_REG, |
| 207 | BDSM_REG, |
| 208 | TSEG_REG, |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 209 | /* Must be last */ |
| 210 | NUM_MAP_ENTRIES, |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 211 | }; |
| 212 | |
| 213 | static struct map_entry memory_map[NUM_MAP_ENTRIES] = { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 214 | [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), |
| 215 | [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), |
| 216 | [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 217 | [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 218 | [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 219 | [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 220 | [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), |
| 221 | [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), |
| 222 | [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), |
Angel Pons | d8abb26 | 2020-05-07 00:48:35 +0200 | [diff] [blame] | 223 | [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"), |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 224 | }; |
| 225 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 226 | static void mc_read_map_entries(struct device *dev, uint64_t *values) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 227 | { |
| 228 | int i; |
| 229 | for (i = 0; i < NUM_MAP_ENTRIES; i++) { |
| 230 | read_map_entry(dev, &memory_map[i], &values[i]); |
| 231 | } |
| 232 | } |
| 233 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 234 | static void mc_report_map_entries(struct device *dev, uint64_t *values) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 235 | { |
| 236 | int i; |
| 237 | for (i = 0; i < NUM_MAP_ENTRIES; i++) { |
| 238 | printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", |
| 239 | memory_map[i].description, values[i]); |
| 240 | } |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 241 | /* One can validate the BDSM and BGSM against the GGC */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 242 | printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); |
| 243 | } |
| 244 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 245 | static void mc_add_dram_resources(struct device *dev, int *resource_cnt) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 246 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 247 | unsigned long base_k, size_k, touud_k, index; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 248 | struct resource *resource; |
| 249 | uint64_t mc_values[NUM_MAP_ENTRIES]; |
| 250 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 251 | /* Read in the MAP registers and report their values */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 252 | mc_read_map_entries(dev, &mc_values[0]); |
| 253 | mc_report_map_entries(dev, &mc_values[0]); |
| 254 | |
Angel Pons | 4b290b7 | 2020-09-24 23:38:53 +0200 | [diff] [blame] | 255 | /* The DPR register is special */ |
| 256 | const union dpr_register dpr = { |
| 257 | .raw = pci_read_config32(dev, DPR), |
| 258 | }; |
| 259 | printk(BIOS_DEBUG, "MC MAP: DPR: 0x%x\n", dpr.raw); |
| 260 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 261 | /* |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 262 | * These are the host memory ranges that should be added: |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 263 | * - 0 -> 0xa0000: cacheable |
| 264 | * - 0xc0000 -> TSEG: cacheable |
| 265 | * - TSEG -> BGSM: cacheable with standard MTRRs and reserved |
| 266 | * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved |
| 267 | * - 4GiB -> TOUUD: cacheable |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 268 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 269 | * The default SMRAM space is reserved so that the range doesn't have to be saved |
| 270 | * during S3 Resume. Once marked reserved the OS cannot use the memory. This is a |
| 271 | * bit of an odd place to reserve the region, but the CPU devices don't have |
| 272 | * dev_ops->read_resources() called on them. |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 273 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 274 | * The range 0xa0000 -> 0xc0000 does not have any resources associated with it to |
| 275 | * handle legacy VGA memory. If this range is not omitted the mtrr code will setup |
| 276 | * the area as cacheable, causing VGA access to not work. |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 277 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 278 | * The TSEG region is mapped as cacheable so that one can perform SMRAM relocation |
| 279 | * faster. Once the SMRR is enabled, the SMRR takes precedence over the existing |
| 280 | * MTRRs covering this region. |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 281 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 282 | * It should be noted that cacheable entry types need to be added in order. The reason |
| 283 | * is that the current MTRR code assumes this and falls over itself if it isn't. |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 284 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 285 | * The resource index starts low and should not meet or exceed PCI_BASE_ADDRESS_0. |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 286 | */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 287 | index = *resource_cnt; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 288 | |
Aaron Durbin | 6a36004 | 2014-02-13 10:30:42 -0600 | [diff] [blame] | 289 | /* 0 - > 0xa0000 */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 290 | base_k = 0; |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 291 | size_k = (0xa0000 >> 10) - base_k; |
| 292 | ram_resource(dev, index++, base_k, size_k); |
| 293 | |
Angel Pons | 4b290b7 | 2020-09-24 23:38:53 +0200 | [diff] [blame] | 294 | /* 0xc0000 -> DPR base */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 295 | base_k = 0xc0000 >> 10; |
Angel Pons | 4b290b7 | 2020-09-24 23:38:53 +0200 | [diff] [blame] | 296 | size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - (base_k + dpr.size); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 297 | ram_resource(dev, index++, base_k, size_k); |
| 298 | |
Angel Pons | 4b290b7 | 2020-09-24 23:38:53 +0200 | [diff] [blame] | 299 | /* DPR base -> TSEG */ |
| 300 | if (dpr.size) { |
| 301 | resource = new_resource(dev, index++); |
| 302 | resource->base = (dpr.top - dpr.size) * MiB; |
| 303 | resource->size = dpr.size * MiB; |
| 304 | resource->flags = IORESOURCE_MEM | IORESOURCE_STORED | IORESOURCE_CACHEABLE | |
| 305 | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 306 | } |
| 307 | |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 308 | /* TSEG -> BGSM */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 309 | resource = new_resource(dev, index++); |
| 310 | resource->base = mc_values[TSEG_REG]; |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 311 | resource->size = mc_values[BGSM_REG] - resource->base; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 312 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | |
| 313 | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 314 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 315 | /* BGSM -> TOLUD. If the IGD is disabled, BGSM can equal TOLUD. */ |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 316 | if (mc_values[BGSM_REG] != mc_values[TOLUD_REG]) { |
| 317 | resource = new_resource(dev, index++); |
| 318 | resource->base = mc_values[BGSM_REG]; |
| 319 | resource->size = mc_values[TOLUD_REG] - resource->base; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 320 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | |
| 321 | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 322 | } |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 323 | |
| 324 | /* 4GiB -> TOUUD */ |
| 325 | base_k = 4096 * 1024; /* 4GiB */ |
Aaron Durbin | 27435d3 | 2013-06-03 09:46:56 -0500 | [diff] [blame] | 326 | touud_k = mc_values[TOUUD_REG] >> 10; |
| 327 | size_k = touud_k - base_k; |
| 328 | if (touud_k > base_k) |
Aaron Durbin | 5c66f08 | 2013-01-08 10:10:33 -0600 | [diff] [blame] | 329 | ram_resource(dev, index++, base_k, size_k); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 330 | |
Aaron Durbin | c965076 | 2013-03-22 22:03:09 -0500 | [diff] [blame] | 331 | /* Reserve everything between A segment and 1MB: |
| 332 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 333 | * 0xa0000 - 0xbffff: Legacy VGA |
Aaron Durbin | c965076 | 2013-03-22 22:03:09 -0500 | [diff] [blame] | 334 | * 0xc0000 - 0xfffff: RAM |
| 335 | */ |
| 336 | mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 337 | reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); |
| 338 | |
Kyösti Mälkki | b8b4133 | 2021-02-10 19:11:55 +0200 | [diff] [blame^] | 339 | if (CONFIG(CHROMEOS_RAMOOPS)) |
| 340 | chromeos_reserve_ram_oops(dev, index++); |
| 341 | |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 342 | *resource_cnt = index; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 343 | } |
| 344 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 345 | static void mc_read_resources(struct device *dev) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 346 | { |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 347 | int index = 0; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 348 | const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 349 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 350 | /* Read standard PCI resources */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 351 | pci_dev_read_resources(dev); |
| 352 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 353 | /* Add all fixed MMIO resources */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 354 | mc_add_fixed_mmio_resources(dev); |
| 355 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 356 | /* Add VT-d MMIO resources, if capable */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 357 | if (vtd_capable) { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 358 | mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB); |
| 359 | mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB); |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 360 | } |
| 361 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 362 | /* Calculate and add DRAM resources */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 363 | mc_add_dram_resources(dev, &index); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 364 | } |
| 365 | |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 366 | /* |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 367 | * The Mini-HD audio device is disabled whenever the IGD is. This is because it provides |
| 368 | * audio over the integrated graphics port(s), which requires the IGD to be functional. |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 369 | */ |
| 370 | static void disable_devices(void) |
| 371 | { |
| 372 | static const struct { |
| 373 | const unsigned int devfn; |
| 374 | const u32 mask; |
| 375 | const char *const name; |
| 376 | } nb_devs[] = { |
| 377 | { PCI_DEVFN(1, 2), DEVEN_D1F2EN, "PEG12" }, |
| 378 | { PCI_DEVFN(1, 1), DEVEN_D1F1EN, "PEG11" }, |
| 379 | { PCI_DEVFN(1, 0), DEVEN_D1F0EN, "PEG10" }, |
| 380 | { PCI_DEVFN(2, 0), DEVEN_D2EN | DEVEN_D3EN, "IGD" }, |
| 381 | { PCI_DEVFN(3, 0), DEVEN_D3EN, "Mini-HD audio" }, |
| 382 | { PCI_DEVFN(4, 0), DEVEN_D4EN, "\"device 4\"" }, |
| 383 | { PCI_DEVFN(7, 0), DEVEN_D7EN, "\"device 7\"" }, |
| 384 | }; |
| 385 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 386 | struct device *host_dev = pcidev_on_root(0, 0); |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 387 | u32 deven; |
| 388 | size_t i; |
| 389 | |
| 390 | if (!host_dev) |
| 391 | return; |
| 392 | |
| 393 | deven = pci_read_config32(host_dev, DEVEN); |
| 394 | |
| 395 | for (i = 0; i < ARRAY_SIZE(nb_devs); i++) { |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 396 | struct device *dev = pcidev_path_on_root(nb_devs[i].devfn); |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 397 | if (!dev || !dev->enabled) { |
| 398 | printk(BIOS_DEBUG, "Disabling %s.\n", nb_devs[i].name); |
| 399 | deven &= ~nb_devs[i].mask; |
| 400 | } |
| 401 | } |
| 402 | |
| 403 | pci_write_config32(host_dev, DEVEN, deven); |
| 404 | } |
| 405 | |
Angel Pons | 028b8e4 | 2020-07-24 14:03:29 +0200 | [diff] [blame] | 406 | static void init_egress(void) |
| 407 | { |
| 408 | /* VC0: Enable, ID0, TC0 */ |
| 409 | EPBAR32(EPVC0RCTL) = (1 << 31) | (0 << 24) | (1 << 0); |
| 410 | |
| 411 | /* No Low Priority Extended VCs, one Extended VC */ |
| 412 | EPBAR32(EPPVCCAP1) = (0 << 4) | (1 << 0); |
| 413 | |
| 414 | /* VC1: Enable, ID1, TC1 */ |
| 415 | EPBAR32(EPVC1RCTL) = (1 << 31) | (1 << 24) | (1 << 1); |
| 416 | |
| 417 | /* Poll the VC1 Negotiation Pending bit */ |
| 418 | while ((EPBAR16(EPVC1RSTS) & (1 << 1)) != 0) |
| 419 | ; |
| 420 | } |
| 421 | |
Angel Pons | 598ec6a | 2020-07-23 02:37:12 +0200 | [diff] [blame] | 422 | static void northbridge_dmi_init(void) |
| 423 | { |
| 424 | const bool is_haswell_h = !CONFIG(INTEL_LYNXPOINT_LP); |
| 425 | |
| 426 | u16 reg16; |
| 427 | u32 reg32; |
| 428 | |
| 429 | /* Steps prior to DMI ASPM */ |
| 430 | if (is_haswell_h) { |
| 431 | /* Configure DMI De-Emphasis */ |
| 432 | reg16 = DMIBAR16(DMILCTL2); |
| 433 | reg16 |= (1 << 6); /* 0b: -6.0 dB, 1b: -3.5 dB */ |
| 434 | DMIBAR16(DMILCTL2) = reg16; |
| 435 | |
| 436 | reg32 = DMIBAR32(DMIL0SLAT); |
| 437 | reg32 |= (1 << 31); |
| 438 | DMIBAR32(DMIL0SLAT) = reg32; |
| 439 | |
| 440 | reg32 = DMIBAR32(DMILLTC); |
| 441 | reg32 |= (1 << 29); |
| 442 | DMIBAR32(DMILLTC) = reg32; |
| 443 | |
| 444 | reg32 = DMIBAR32(DMI_AFE_PM_TMR); |
| 445 | reg32 &= ~0x1f; |
| 446 | reg32 |= 0x13; |
| 447 | DMIBAR32(DMI_AFE_PM_TMR) = reg32; |
| 448 | } |
| 449 | |
| 450 | /* Clear error status bits */ |
| 451 | DMIBAR32(DMIUESTS) = 0xffffffff; |
| 452 | DMIBAR32(DMICESTS) = 0xffffffff; |
| 453 | |
| 454 | if (is_haswell_h) { |
| 455 | /* Enable ASPM L0s and L1 on SA link, should happen before PCH link */ |
| 456 | reg16 = DMIBAR16(DMILCTL); |
| 457 | reg16 |= (1 << 1) | (1 << 0); |
| 458 | DMIBAR16(DMILCTL) = reg16; |
| 459 | } |
| 460 | } |
| 461 | |
Angel Pons | 76b8bc2 | 2020-07-23 02:32:27 +0200 | [diff] [blame] | 462 | static void northbridge_topology_init(void) |
| 463 | { |
| 464 | const u32 eple_a[3] = { EPLE2A, EPLE3A, EPLE4A }; |
| 465 | const u32 eple_d[3] = { EPLE2D, EPLE3D, EPLE4D }; |
| 466 | |
| 467 | u32 reg32; |
| 468 | |
| 469 | /* Set the CID1 Egress Port 0 Root Topology */ |
| 470 | reg32 = EPBAR32(EPESD); |
| 471 | reg32 &= ~(0xff << 16); |
| 472 | reg32 |= 1 << 16; |
| 473 | EPBAR32(EPESD) = reg32; |
| 474 | |
| 475 | reg32 = EPBAR32(EPLE1D); |
| 476 | reg32 &= ~(0xff << 16); |
| 477 | reg32 |= 1 | (1 << 16); |
| 478 | EPBAR32(EPLE1D) = reg32; |
Angel Pons | f95b9b4 | 2021-01-20 01:10:48 +0100 | [diff] [blame] | 479 | EPBAR64(EPLE1A) = CONFIG_FIXED_DMIBAR_MMIO_BASE; |
Angel Pons | 76b8bc2 | 2020-07-23 02:32:27 +0200 | [diff] [blame] | 480 | |
| 481 | for (unsigned int i = 0; i <= 2; i++) { |
| 482 | const struct device *const dev = pcidev_on_root(1, i); |
| 483 | |
| 484 | if (!dev || !dev->enabled) |
| 485 | continue; |
| 486 | |
| 487 | EPBAR64(eple_a[i]) = (u64)PCI_DEV(0, 1, i); |
| 488 | |
| 489 | reg32 = EPBAR32(eple_d[i]); |
| 490 | reg32 &= ~(0xff << 16); |
| 491 | reg32 |= 1 | (1 << 16); |
| 492 | EPBAR32(eple_d[i]) = reg32; |
| 493 | |
| 494 | pci_update_config32(dev, PEG_ESD, ~(0xff << 16), (1 << 16)); |
Angel Pons | f95b9b4 | 2021-01-20 01:10:48 +0100 | [diff] [blame] | 495 | pci_write_config32(dev, PEG_LE1A, CONFIG_FIXED_EPBAR_MMIO_BASE); |
Angel Pons | 76b8bc2 | 2020-07-23 02:32:27 +0200 | [diff] [blame] | 496 | pci_write_config32(dev, PEG_LE1A + 4, 0); |
| 497 | pci_update_config32(dev, PEG_LE1D, ~(0xff << 16), (1 << 16) | 1); |
| 498 | |
| 499 | /* Read and write to lock register */ |
| 500 | pci_or_config32(dev, PEG_DCAP2, 0); |
| 501 | } |
| 502 | |
| 503 | /* Set the CID1 DMI Port Root Topology */ |
| 504 | reg32 = DMIBAR32(DMIESD); |
| 505 | reg32 &= ~(0xff << 16); |
| 506 | reg32 |= 1 << 16; |
| 507 | DMIBAR32(DMIESD) = reg32; |
| 508 | |
| 509 | reg32 = DMIBAR32(DMILE1D); |
| 510 | reg32 &= ~(0xffff << 16); |
| 511 | reg32 |= 1 | (2 << 16); |
| 512 | DMIBAR32(DMILE1D) = reg32; |
Angel Pons | 6e732d3 | 2021-01-28 13:56:18 +0100 | [diff] [blame] | 513 | DMIBAR64(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE; |
Angel Pons | 76b8bc2 | 2020-07-23 02:32:27 +0200 | [diff] [blame] | 514 | |
Angel Pons | f95b9b4 | 2021-01-20 01:10:48 +0100 | [diff] [blame] | 515 | DMIBAR64(DMILE2A) = CONFIG_FIXED_EPBAR_MMIO_BASE; |
Angel Pons | 76b8bc2 | 2020-07-23 02:32:27 +0200 | [diff] [blame] | 516 | reg32 = DMIBAR32(DMILE2D); |
| 517 | reg32 &= ~(0xff << 16); |
| 518 | reg32 |= 1 | (1 << 16); |
| 519 | DMIBAR32(DMILE2D) = reg32; |
| 520 | |
| 521 | /* Program RO and Write-Once Registers */ |
| 522 | DMIBAR32(DMIPVCCAP1) = DMIBAR32(DMIPVCCAP1); |
| 523 | DMIBAR32(DMILCAP) = DMIBAR32(DMILCAP); |
| 524 | } |
| 525 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 526 | static void northbridge_init(struct device *dev) |
| 527 | { |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 528 | u8 bios_reset_cpl, pair; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 529 | |
Angel Pons | 028b8e4 | 2020-07-24 14:03:29 +0200 | [diff] [blame] | 530 | init_egress(); |
Angel Pons | 598ec6a | 2020-07-23 02:37:12 +0200 | [diff] [blame] | 531 | northbridge_dmi_init(); |
Angel Pons | 76b8bc2 | 2020-07-23 02:32:27 +0200 | [diff] [blame] | 532 | northbridge_topology_init(); |
Angel Pons | 598ec6a | 2020-07-23 02:37:12 +0200 | [diff] [blame] | 533 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 534 | /* Enable Power Aware Interrupt Routing. */ |
| 535 | pair = MCHBAR8(INTRDIRCTL); |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 536 | pair &= ~0x7; /* Clear 2:0 */ |
| 537 | pair |= 0x4; /* Fixed Priority */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 538 | MCHBAR8(INTRDIRCTL) = pair; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 539 | |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 540 | disable_devices(); |
| 541 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 542 | /* |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 543 | * Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU |
| 544 | * that BIOS has initialized memory and power management. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 545 | */ |
| 546 | bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 547 | bios_reset_cpl |= 3; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 548 | MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; |
| 549 | printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); |
| 550 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 551 | /* Configure turbo power limits 1ms after reset complete bit. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 552 | mdelay(1); |
| 553 | set_power_limits(28); |
| 554 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 555 | /* Set here before graphics PM init. */ |
| 556 | MCHBAR32(MMIO_PAVP_MSG) = 0x00100001; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 557 | } |
| 558 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 559 | static struct device_operations mc_ops = { |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 560 | .read_resources = mc_read_resources, |
| 561 | .set_resources = pci_dev_set_resources, |
| 562 | .enable_resources = pci_dev_enable_resources, |
| 563 | .init = northbridge_init, |
| 564 | .acpi_fill_ssdt = generate_cpu_entries, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 565 | .ops_pci = &pci_dev_ops_pci, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 566 | }; |
| 567 | |
Tristan Corrick | d385624 | 2018-11-01 03:03:29 +1300 | [diff] [blame] | 568 | static const unsigned short mc_pci_device_ids[] = { |
| 569 | 0x0c00, /* Desktop */ |
| 570 | 0x0c04, /* Mobile */ |
| 571 | 0x0a04, /* ULT */ |
Iru Cai | 0766c98 | 2018-12-17 13:21:36 +0800 | [diff] [blame] | 572 | 0x0c08, /* Server */ |
Iru Cai | 12a13e1 | 2020-05-22 22:57:03 +0800 | [diff] [blame] | 573 | 0x0d00, /* Crystal Well Desktop */ |
| 574 | 0x0d04, /* Crystal Well Mobile */ |
| 575 | 0x0d08, /* Crystal Well Server (by extrapolation) */ |
Tristan Corrick | d385624 | 2018-11-01 03:03:29 +1300 | [diff] [blame] | 576 | 0 |
Tristan Corrick | 4817012 | 2018-10-31 02:21:41 +1300 | [diff] [blame] | 577 | }; |
| 578 | |
Tristan Corrick | d385624 | 2018-11-01 03:03:29 +1300 | [diff] [blame] | 579 | static const struct pci_driver mc_driver_hsw __pci_driver = { |
| 580 | .ops = &mc_ops, |
| 581 | .vendor = PCI_VENDOR_ID_INTEL, |
| 582 | .devices = mc_pci_device_ids, |
Duncan Laurie | df7be71 | 2012-12-17 11:22:57 -0800 | [diff] [blame] | 583 | }; |
| 584 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 585 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 586 | .read_resources = noop_read_resources, |
| 587 | .set_resources = noop_set_resources, |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 588 | .init = mp_cpu_bus_init, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 589 | }; |
| 590 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 591 | static void enable_dev(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 592 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 593 | /* Set the operations if it is a special bus type. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 594 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 595 | dev->ops = &pci_domain_ops; |
| 596 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 597 | dev->ops = &cpu_bus_ops; |
| 598 | } |
| 599 | } |
| 600 | |
| 601 | struct chip_operations northbridge_intel_haswell_ops = { |
Angel Pons | 7bbf45e | 2020-10-22 23:55:24 +0200 | [diff] [blame] | 602 | CHIP_NAME("Intel Haswell integrated Northbridge") |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 603 | .enable_dev = enable_dev, |
| 604 | }; |