Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 3 | #include <commonlib/helpers.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 4 | #include <console/console.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 5 | #include <acpi/acpi.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 6 | #include <stdint.h> |
| 7 | #include <delay.h> |
| 8 | #include <cpu/intel/haswell/haswell.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 9 | #include <device/device.h> |
| 10 | #include <device/pci.h> |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 11 | #include <device/pci_def.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 12 | #include <device/pci_ids.h> |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 13 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 14 | #include <boot/tables.h> |
Angel Pons | 4b290b7 | 2020-09-24 23:38:53 +0200 | [diff] [blame] | 15 | #include <security/intel/txt/txt_register.h> |
Elyes HAOUAS | a1e22b8 | 2019-03-18 22:49:36 +0100 | [diff] [blame] | 16 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 17 | #include "chip.h" |
| 18 | #include "haswell.h" |
| 19 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 20 | static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 21 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 22 | u32 pciexbar_reg, mask; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 23 | |
| 24 | *base = 0; |
| 25 | *len = 0; |
| 26 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 27 | pciexbar_reg = pci_read_config32(dev, index); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 28 | |
| 29 | if (!(pciexbar_reg & (1 << 0))) |
| 30 | return 0; |
| 31 | |
| 32 | switch ((pciexbar_reg >> 1) & 3) { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 33 | case 0: /* 256MB */ |
Ryan Salsamendi | fa0725d | 2017-06-30 17:29:37 -0700 | [diff] [blame] | 34 | mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); |
| 35 | *base = pciexbar_reg & mask; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 36 | *len = 256 * 1024 * 1024; |
| 37 | return 1; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 38 | case 1: /* 128M */ |
Ryan Salsamendi | fa0725d | 2017-06-30 17:29:37 -0700 | [diff] [blame] | 39 | mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); |
| 40 | mask |= (1 << 27); |
| 41 | *base = pciexbar_reg & mask; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 42 | *len = 128 * 1024 * 1024; |
| 43 | return 1; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 44 | case 2: /* 64M */ |
Ryan Salsamendi | fa0725d | 2017-06-30 17:29:37 -0700 | [diff] [blame] | 45 | mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); |
| 46 | mask |= (1 << 27) | (1 << 26); |
| 47 | *base = pciexbar_reg & mask; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 48 | *len = 64 * 1024 * 1024; |
| 49 | return 1; |
| 50 | } |
| 51 | |
| 52 | return 0; |
| 53 | } |
| 54 | |
Angel Pons | f4fa1e1 | 2020-08-03 14:12:13 +0200 | [diff] [blame] | 55 | int decode_pcie_bar(u32 *const base, u32 *const len) |
| 56 | { |
| 57 | return get_pcie_bar(pcidev_on_root(0, 0), PCIEXBAR, base, len); |
| 58 | } |
| 59 | |
Tristan Corrick | f3127d4 | 2018-10-31 02:25:54 +1300 | [diff] [blame] | 60 | static const char *northbridge_acpi_name(const struct device *dev) |
| 61 | { |
| 62 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 63 | return "PCI0"; |
| 64 | |
| 65 | if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) |
| 66 | return NULL; |
| 67 | |
| 68 | switch (dev->path.pci.devfn) { |
| 69 | case PCI_DEVFN(0, 0): |
| 70 | return "MCHC"; |
| 71 | } |
| 72 | |
| 73 | return NULL; |
| 74 | } |
| 75 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 76 | /* |
| 77 | * TODO: We could determine how many PCIe busses we need in the bar. |
| 78 | * For now, that number is hardcoded to a max of 64. |
| 79 | */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 80 | static struct device_operations pci_domain_ops = { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 81 | .read_resources = pci_domain_read_resources, |
| 82 | .set_resources = pci_domain_set_resources, |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 83 | .scan_bus = pci_domain_scan_bus, |
| 84 | .acpi_name = northbridge_acpi_name, |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 85 | .write_acpi_tables = northbridge_write_acpi_tables, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 86 | }; |
| 87 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 88 | static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 89 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 90 | u32 bar = pci_read_config32(dev, index); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 91 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 92 | /* If not enabled don't report it */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 93 | if (!(bar & 0x1)) |
| 94 | return 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 95 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 96 | /* Knock down the enable bit */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 97 | *base = bar & ~1; |
| 98 | |
| 99 | return 1; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 100 | } |
| 101 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 102 | /* |
| 103 | * There are special BARs that actually are programmed in the MCHBAR. These Intel special |
| 104 | * features, but they do consume resources that need to be accounted for. |
| 105 | */ |
| 106 | static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 107 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 108 | u32 bar = MCHBAR32(index); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 109 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 110 | /* If not enabled don't report it */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 111 | if (!(bar & 0x1)) |
| 112 | return 0; |
| 113 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 114 | /* Knock down the enable bit */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 115 | *base = bar & ~1; |
| 116 | |
| 117 | return 1; |
| 118 | } |
| 119 | |
| 120 | struct fixed_mmio_descriptor { |
| 121 | unsigned int index; |
| 122 | u32 size; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 123 | int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 124 | const char *description; |
| 125 | }; |
| 126 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 127 | #define SIZE_KB(x) ((x) * 1024) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 128 | struct fixed_mmio_descriptor mc_fixed_resources[] = { |
| 129 | { PCIEXBAR, SIZE_KB(0), get_pcie_bar, "PCIEXBAR" }, |
| 130 | { MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" }, |
| 131 | { DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" }, |
| 132 | { EPBAR, SIZE_KB(4), get_bar, "EPBAR" }, |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 133 | { GDXCBAR, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, |
| 134 | { EDRAMBAR, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 135 | }; |
| 136 | #undef SIZE_KB |
| 137 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 138 | /* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */ |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 139 | static void mc_add_fixed_mmio_resources(struct device *dev) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 140 | { |
| 141 | int i; |
| 142 | |
| 143 | for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { |
| 144 | u32 base; |
| 145 | u32 size; |
| 146 | struct resource *resource; |
| 147 | unsigned int index; |
| 148 | |
| 149 | size = mc_fixed_resources[i].size; |
| 150 | index = mc_fixed_resources[i].index; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 151 | if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size)) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 152 | continue; |
| 153 | |
| 154 | resource = new_resource(dev, mc_fixed_resources[i].index); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 155 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | |
| 156 | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; |
| 157 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 158 | resource->base = base; |
| 159 | resource->size = size; |
| 160 | printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", |
| 161 | __func__, mc_fixed_resources[i].description, index, |
| 162 | (unsigned long)base, (unsigned long)(base + size - 1)); |
| 163 | } |
| 164 | } |
| 165 | |
Angel Pons | 4b290b7 | 2020-09-24 23:38:53 +0200 | [diff] [blame] | 166 | /* |
| 167 | * Host Memory Map: |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 168 | * |
| 169 | * +--------------------------+ TOUUD |
| 170 | * | | |
| 171 | * +--------------------------+ 4GiB |
| 172 | * | PCI Address Space | |
| 173 | * +--------------------------+ TOLUD (also maps into MC address space) |
| 174 | * | iGD | |
| 175 | * +--------------------------+ BDSM |
| 176 | * | GTT | |
| 177 | * +--------------------------+ BGSM |
| 178 | * | TSEG | |
| 179 | * +--------------------------+ TSEGMB |
Angel Pons | 4b290b7 | 2020-09-24 23:38:53 +0200 | [diff] [blame] | 180 | * | DPR | |
| 181 | * +--------------------------+ (DPR top - DPR size) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 182 | * | Usage DRAM | |
| 183 | * +--------------------------+ 0 |
| 184 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 185 | * Some of the base registers above can be equal, making the size of the regions within 0. |
| 186 | * This is because the memory controller internally subtracts the base registers from each |
| 187 | * other to determine sizes of the regions. In other words, the memory map regions are always |
| 188 | * in a fixed order, no matter what sizes they have. |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 189 | */ |
| 190 | |
| 191 | struct map_entry { |
| 192 | int reg; |
| 193 | int is_64_bit; |
| 194 | int is_limit; |
| 195 | const char *description; |
| 196 | }; |
| 197 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 198 | static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 199 | { |
| 200 | uint64_t value; |
| 201 | uint64_t mask; |
| 202 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 203 | /* All registers have a 1MiB granularity */ |
| 204 | mask = ((1ULL << 20) - 1); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 205 | mask = ~mask; |
| 206 | |
| 207 | value = 0; |
| 208 | |
| 209 | if (entry->is_64_bit) { |
| 210 | value = pci_read_config32(dev, entry->reg + 4); |
| 211 | value <<= 32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 212 | } |
| 213 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 214 | value |= pci_read_config32(dev, entry->reg); |
| 215 | value &= mask; |
| 216 | |
| 217 | if (entry->is_limit) |
| 218 | value |= ~mask; |
| 219 | |
| 220 | *result = value; |
| 221 | } |
| 222 | |
| 223 | #define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ |
| 224 | { \ |
| 225 | .reg = reg_, \ |
| 226 | .is_64_bit = is_64_, \ |
| 227 | .is_limit = is_limit_, \ |
| 228 | .description = desc_, \ |
| 229 | } |
| 230 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 231 | #define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_) |
| 232 | #define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_) |
| 233 | #define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 234 | |
| 235 | enum { |
| 236 | TOM_REG, |
| 237 | TOUUD_REG, |
| 238 | MESEG_BASE_REG, |
| 239 | MESEG_LIMIT_REG, |
| 240 | REMAP_BASE_REG, |
| 241 | REMAP_LIMIT_REG, |
| 242 | TOLUD_REG, |
| 243 | BGSM_REG, |
| 244 | BDSM_REG, |
| 245 | TSEG_REG, |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 246 | /* Must be last */ |
| 247 | NUM_MAP_ENTRIES, |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 248 | }; |
| 249 | |
| 250 | static struct map_entry memory_map[NUM_MAP_ENTRIES] = { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 251 | [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), |
| 252 | [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), |
| 253 | [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 254 | [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 255 | [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 256 | [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 257 | [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), |
| 258 | [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), |
| 259 | [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), |
Angel Pons | d8abb26 | 2020-05-07 00:48:35 +0200 | [diff] [blame] | 260 | [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TSEGMB"), |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 261 | }; |
| 262 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 263 | static void mc_read_map_entries(struct device *dev, uint64_t *values) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 264 | { |
| 265 | int i; |
| 266 | for (i = 0; i < NUM_MAP_ENTRIES; i++) { |
| 267 | read_map_entry(dev, &memory_map[i], &values[i]); |
| 268 | } |
| 269 | } |
| 270 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 271 | static void mc_report_map_entries(struct device *dev, uint64_t *values) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 272 | { |
| 273 | int i; |
| 274 | for (i = 0; i < NUM_MAP_ENTRIES; i++) { |
| 275 | printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", |
| 276 | memory_map[i].description, values[i]); |
| 277 | } |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 278 | /* One can validate the BDSM and BGSM against the GGC */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 279 | printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); |
| 280 | } |
| 281 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 282 | static void mc_add_dram_resources(struct device *dev, int *resource_cnt) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 283 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 284 | unsigned long base_k, size_k, touud_k, index; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 285 | struct resource *resource; |
| 286 | uint64_t mc_values[NUM_MAP_ENTRIES]; |
| 287 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 288 | /* Read in the MAP registers and report their values */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 289 | mc_read_map_entries(dev, &mc_values[0]); |
| 290 | mc_report_map_entries(dev, &mc_values[0]); |
| 291 | |
Angel Pons | 4b290b7 | 2020-09-24 23:38:53 +0200 | [diff] [blame] | 292 | /* The DPR register is special */ |
| 293 | const union dpr_register dpr = { |
| 294 | .raw = pci_read_config32(dev, DPR), |
| 295 | }; |
| 296 | printk(BIOS_DEBUG, "MC MAP: DPR: 0x%x\n", dpr.raw); |
| 297 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 298 | /* |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 299 | * These are the host memory ranges that should be added: |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 300 | * - 0 -> 0xa0000: cacheable |
| 301 | * - 0xc0000 -> TSEG: cacheable |
| 302 | * - TSEG -> BGSM: cacheable with standard MTRRs and reserved |
| 303 | * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved |
| 304 | * - 4GiB -> TOUUD: cacheable |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 305 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 306 | * The default SMRAM space is reserved so that the range doesn't have to be saved |
| 307 | * during S3 Resume. Once marked reserved the OS cannot use the memory. This is a |
| 308 | * bit of an odd place to reserve the region, but the CPU devices don't have |
| 309 | * dev_ops->read_resources() called on them. |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 310 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 311 | * The range 0xa0000 -> 0xc0000 does not have any resources associated with it to |
| 312 | * handle legacy VGA memory. If this range is not omitted the mtrr code will setup |
| 313 | * the area as cacheable, causing VGA access to not work. |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 314 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 315 | * The TSEG region is mapped as cacheable so that one can perform SMRAM relocation |
| 316 | * faster. Once the SMRR is enabled, the SMRR takes precedence over the existing |
| 317 | * MTRRs covering this region. |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 318 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 319 | * It should be noted that cacheable entry types need to be added in order. The reason |
| 320 | * is that the current MTRR code assumes this and falls over itself if it isn't. |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 321 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 322 | * The resource index starts low and should not meet or exceed PCI_BASE_ADDRESS_0. |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 323 | */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 324 | index = *resource_cnt; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 325 | |
Aaron Durbin | 6a36004 | 2014-02-13 10:30:42 -0600 | [diff] [blame] | 326 | /* 0 - > 0xa0000 */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 327 | base_k = 0; |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 328 | size_k = (0xa0000 >> 10) - base_k; |
| 329 | ram_resource(dev, index++, base_k, size_k); |
| 330 | |
Angel Pons | 4b290b7 | 2020-09-24 23:38:53 +0200 | [diff] [blame] | 331 | /* 0xc0000 -> DPR base */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 332 | base_k = 0xc0000 >> 10; |
Angel Pons | 4b290b7 | 2020-09-24 23:38:53 +0200 | [diff] [blame] | 333 | size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - (base_k + dpr.size); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 334 | ram_resource(dev, index++, base_k, size_k); |
| 335 | |
Angel Pons | 4b290b7 | 2020-09-24 23:38:53 +0200 | [diff] [blame] | 336 | /* DPR base -> TSEG */ |
| 337 | if (dpr.size) { |
| 338 | resource = new_resource(dev, index++); |
| 339 | resource->base = (dpr.top - dpr.size) * MiB; |
| 340 | resource->size = dpr.size * MiB; |
| 341 | resource->flags = IORESOURCE_MEM | IORESOURCE_STORED | IORESOURCE_CACHEABLE | |
| 342 | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 343 | } |
| 344 | |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 345 | /* TSEG -> BGSM */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 346 | resource = new_resource(dev, index++); |
| 347 | resource->base = mc_values[TSEG_REG]; |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 348 | resource->size = mc_values[BGSM_REG] - resource->base; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 349 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | |
| 350 | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 351 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 352 | /* BGSM -> TOLUD. If the IGD is disabled, BGSM can equal TOLUD. */ |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 353 | if (mc_values[BGSM_REG] != mc_values[TOLUD_REG]) { |
| 354 | resource = new_resource(dev, index++); |
| 355 | resource->base = mc_values[BGSM_REG]; |
| 356 | resource->size = mc_values[TOLUD_REG] - resource->base; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 357 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | |
| 358 | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 359 | } |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 360 | |
| 361 | /* 4GiB -> TOUUD */ |
| 362 | base_k = 4096 * 1024; /* 4GiB */ |
Aaron Durbin | 27435d3 | 2013-06-03 09:46:56 -0500 | [diff] [blame] | 363 | touud_k = mc_values[TOUUD_REG] >> 10; |
| 364 | size_k = touud_k - base_k; |
| 365 | if (touud_k > base_k) |
Aaron Durbin | 5c66f08 | 2013-01-08 10:10:33 -0600 | [diff] [blame] | 366 | ram_resource(dev, index++, base_k, size_k); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 367 | |
Aaron Durbin | c965076 | 2013-03-22 22:03:09 -0500 | [diff] [blame] | 368 | /* Reserve everything between A segment and 1MB: |
| 369 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 370 | * 0xa0000 - 0xbffff: Legacy VGA |
Aaron Durbin | c965076 | 2013-03-22 22:03:09 -0500 | [diff] [blame] | 371 | * 0xc0000 - 0xfffff: RAM |
| 372 | */ |
| 373 | mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 374 | reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); |
| 375 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 376 | #if CONFIG(CHROMEOS_RAMOOPS) |
Aaron Durbin | c965076 | 2013-03-22 22:03:09 -0500 | [diff] [blame] | 377 | reserved_ram_resource(dev, index++, |
| 378 | CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 379 | CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 380 | #endif |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 381 | *resource_cnt = index; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 382 | } |
| 383 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 384 | static void mc_read_resources(struct device *dev) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 385 | { |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 386 | int index = 0; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 387 | const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 388 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 389 | /* Read standard PCI resources */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 390 | pci_dev_read_resources(dev); |
| 391 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 392 | /* Add all fixed MMIO resources */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 393 | mc_add_fixed_mmio_resources(dev); |
| 394 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 395 | /* Add VT-d MMIO resources, if capable */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 396 | if (vtd_capable) { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 397 | mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB); |
| 398 | mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB); |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 399 | } |
| 400 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 401 | /* Calculate and add DRAM resources */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 402 | mc_add_dram_resources(dev, &index); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 403 | } |
| 404 | |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 405 | /* |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 406 | * The Mini-HD audio device is disabled whenever the IGD is. This is because it provides |
| 407 | * audio over the integrated graphics port(s), which requires the IGD to be functional. |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 408 | */ |
| 409 | static void disable_devices(void) |
| 410 | { |
| 411 | static const struct { |
| 412 | const unsigned int devfn; |
| 413 | const u32 mask; |
| 414 | const char *const name; |
| 415 | } nb_devs[] = { |
| 416 | { PCI_DEVFN(1, 2), DEVEN_D1F2EN, "PEG12" }, |
| 417 | { PCI_DEVFN(1, 1), DEVEN_D1F1EN, "PEG11" }, |
| 418 | { PCI_DEVFN(1, 0), DEVEN_D1F0EN, "PEG10" }, |
| 419 | { PCI_DEVFN(2, 0), DEVEN_D2EN | DEVEN_D3EN, "IGD" }, |
| 420 | { PCI_DEVFN(3, 0), DEVEN_D3EN, "Mini-HD audio" }, |
| 421 | { PCI_DEVFN(4, 0), DEVEN_D4EN, "\"device 4\"" }, |
| 422 | { PCI_DEVFN(7, 0), DEVEN_D7EN, "\"device 7\"" }, |
| 423 | }; |
| 424 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 425 | struct device *host_dev = pcidev_on_root(0, 0); |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 426 | u32 deven; |
| 427 | size_t i; |
| 428 | |
| 429 | if (!host_dev) |
| 430 | return; |
| 431 | |
| 432 | deven = pci_read_config32(host_dev, DEVEN); |
| 433 | |
| 434 | for (i = 0; i < ARRAY_SIZE(nb_devs); i++) { |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 435 | struct device *dev = pcidev_path_on_root(nb_devs[i].devfn); |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 436 | if (!dev || !dev->enabled) { |
| 437 | printk(BIOS_DEBUG, "Disabling %s.\n", nb_devs[i].name); |
| 438 | deven &= ~nb_devs[i].mask; |
| 439 | } |
| 440 | } |
| 441 | |
| 442 | pci_write_config32(host_dev, DEVEN, deven); |
| 443 | } |
| 444 | |
Angel Pons | 028b8e4 | 2020-07-24 14:03:29 +0200 | [diff] [blame] | 445 | static void init_egress(void) |
| 446 | { |
| 447 | /* VC0: Enable, ID0, TC0 */ |
| 448 | EPBAR32(EPVC0RCTL) = (1 << 31) | (0 << 24) | (1 << 0); |
| 449 | |
| 450 | /* No Low Priority Extended VCs, one Extended VC */ |
| 451 | EPBAR32(EPPVCCAP1) = (0 << 4) | (1 << 0); |
| 452 | |
| 453 | /* VC1: Enable, ID1, TC1 */ |
| 454 | EPBAR32(EPVC1RCTL) = (1 << 31) | (1 << 24) | (1 << 1); |
| 455 | |
| 456 | /* Poll the VC1 Negotiation Pending bit */ |
| 457 | while ((EPBAR16(EPVC1RSTS) & (1 << 1)) != 0) |
| 458 | ; |
| 459 | } |
| 460 | |
Angel Pons | 598ec6a | 2020-07-23 02:37:12 +0200 | [diff] [blame] | 461 | static void northbridge_dmi_init(void) |
| 462 | { |
| 463 | const bool is_haswell_h = !CONFIG(INTEL_LYNXPOINT_LP); |
| 464 | |
| 465 | u16 reg16; |
| 466 | u32 reg32; |
| 467 | |
| 468 | /* Steps prior to DMI ASPM */ |
| 469 | if (is_haswell_h) { |
| 470 | /* Configure DMI De-Emphasis */ |
| 471 | reg16 = DMIBAR16(DMILCTL2); |
| 472 | reg16 |= (1 << 6); /* 0b: -6.0 dB, 1b: -3.5 dB */ |
| 473 | DMIBAR16(DMILCTL2) = reg16; |
| 474 | |
| 475 | reg32 = DMIBAR32(DMIL0SLAT); |
| 476 | reg32 |= (1 << 31); |
| 477 | DMIBAR32(DMIL0SLAT) = reg32; |
| 478 | |
| 479 | reg32 = DMIBAR32(DMILLTC); |
| 480 | reg32 |= (1 << 29); |
| 481 | DMIBAR32(DMILLTC) = reg32; |
| 482 | |
| 483 | reg32 = DMIBAR32(DMI_AFE_PM_TMR); |
| 484 | reg32 &= ~0x1f; |
| 485 | reg32 |= 0x13; |
| 486 | DMIBAR32(DMI_AFE_PM_TMR) = reg32; |
| 487 | } |
| 488 | |
| 489 | /* Clear error status bits */ |
| 490 | DMIBAR32(DMIUESTS) = 0xffffffff; |
| 491 | DMIBAR32(DMICESTS) = 0xffffffff; |
| 492 | |
| 493 | if (is_haswell_h) { |
| 494 | /* Enable ASPM L0s and L1 on SA link, should happen before PCH link */ |
| 495 | reg16 = DMIBAR16(DMILCTL); |
| 496 | reg16 |= (1 << 1) | (1 << 0); |
| 497 | DMIBAR16(DMILCTL) = reg16; |
| 498 | } |
| 499 | } |
| 500 | |
Angel Pons | 76b8bc2 | 2020-07-23 02:32:27 +0200 | [diff] [blame^] | 501 | static void northbridge_topology_init(void) |
| 502 | { |
| 503 | const u32 eple_a[3] = { EPLE2A, EPLE3A, EPLE4A }; |
| 504 | const u32 eple_d[3] = { EPLE2D, EPLE3D, EPLE4D }; |
| 505 | |
| 506 | u32 reg32; |
| 507 | |
| 508 | /* Set the CID1 Egress Port 0 Root Topology */ |
| 509 | reg32 = EPBAR32(EPESD); |
| 510 | reg32 &= ~(0xff << 16); |
| 511 | reg32 |= 1 << 16; |
| 512 | EPBAR32(EPESD) = reg32; |
| 513 | |
| 514 | reg32 = EPBAR32(EPLE1D); |
| 515 | reg32 &= ~(0xff << 16); |
| 516 | reg32 |= 1 | (1 << 16); |
| 517 | EPBAR32(EPLE1D) = reg32; |
| 518 | EPBAR64(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; |
| 519 | |
| 520 | for (unsigned int i = 0; i <= 2; i++) { |
| 521 | const struct device *const dev = pcidev_on_root(1, i); |
| 522 | |
| 523 | if (!dev || !dev->enabled) |
| 524 | continue; |
| 525 | |
| 526 | EPBAR64(eple_a[i]) = (u64)PCI_DEV(0, 1, i); |
| 527 | |
| 528 | reg32 = EPBAR32(eple_d[i]); |
| 529 | reg32 &= ~(0xff << 16); |
| 530 | reg32 |= 1 | (1 << 16); |
| 531 | EPBAR32(eple_d[i]) = reg32; |
| 532 | |
| 533 | pci_update_config32(dev, PEG_ESD, ~(0xff << 16), (1 << 16)); |
| 534 | pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); |
| 535 | pci_write_config32(dev, PEG_LE1A + 4, 0); |
| 536 | pci_update_config32(dev, PEG_LE1D, ~(0xff << 16), (1 << 16) | 1); |
| 537 | |
| 538 | /* Read and write to lock register */ |
| 539 | pci_or_config32(dev, PEG_DCAP2, 0); |
| 540 | } |
| 541 | |
| 542 | /* Set the CID1 DMI Port Root Topology */ |
| 543 | reg32 = DMIBAR32(DMIESD); |
| 544 | reg32 &= ~(0xff << 16); |
| 545 | reg32 |= 1 << 16; |
| 546 | DMIBAR32(DMIESD) = reg32; |
| 547 | |
| 548 | reg32 = DMIBAR32(DMILE1D); |
| 549 | reg32 &= ~(0xffff << 16); |
| 550 | reg32 |= 1 | (2 << 16); |
| 551 | DMIBAR32(DMILE1D) = reg32; |
| 552 | DMIBAR64(DMILE1A) = (uintptr_t)DEFAULT_RCBA; |
| 553 | |
| 554 | DMIBAR64(DMILE2A) = (uintptr_t)DEFAULT_EPBAR; |
| 555 | reg32 = DMIBAR32(DMILE2D); |
| 556 | reg32 &= ~(0xff << 16); |
| 557 | reg32 |= 1 | (1 << 16); |
| 558 | DMIBAR32(DMILE2D) = reg32; |
| 559 | |
| 560 | /* Program RO and Write-Once Registers */ |
| 561 | DMIBAR32(DMIPVCCAP1) = DMIBAR32(DMIPVCCAP1); |
| 562 | DMIBAR32(DMILCAP) = DMIBAR32(DMILCAP); |
| 563 | } |
| 564 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 565 | static void northbridge_init(struct device *dev) |
| 566 | { |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 567 | u8 bios_reset_cpl, pair; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 568 | |
Angel Pons | 028b8e4 | 2020-07-24 14:03:29 +0200 | [diff] [blame] | 569 | init_egress(); |
Angel Pons | 598ec6a | 2020-07-23 02:37:12 +0200 | [diff] [blame] | 570 | northbridge_dmi_init(); |
Angel Pons | 76b8bc2 | 2020-07-23 02:32:27 +0200 | [diff] [blame^] | 571 | northbridge_topology_init(); |
Angel Pons | 598ec6a | 2020-07-23 02:37:12 +0200 | [diff] [blame] | 572 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 573 | /* Enable Power Aware Interrupt Routing. */ |
| 574 | pair = MCHBAR8(INTRDIRCTL); |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 575 | pair &= ~0x7; /* Clear 2:0 */ |
| 576 | pair |= 0x4; /* Fixed Priority */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 577 | MCHBAR8(INTRDIRCTL) = pair; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 578 | |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 579 | disable_devices(); |
| 580 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 581 | /* |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 582 | * Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU |
| 583 | * that BIOS has initialized memory and power management. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 584 | */ |
| 585 | bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 586 | bios_reset_cpl |= 3; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 587 | MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; |
| 588 | printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); |
| 589 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 590 | /* Configure turbo power limits 1ms after reset complete bit. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 591 | mdelay(1); |
| 592 | set_power_limits(28); |
| 593 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 594 | /* Set here before graphics PM init. */ |
| 595 | MCHBAR32(MMIO_PAVP_MSG) = 0x00100001; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 596 | } |
| 597 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 598 | static struct device_operations mc_ops = { |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 599 | .read_resources = mc_read_resources, |
| 600 | .set_resources = pci_dev_set_resources, |
| 601 | .enable_resources = pci_dev_enable_resources, |
| 602 | .init = northbridge_init, |
| 603 | .acpi_fill_ssdt = generate_cpu_entries, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 604 | .ops_pci = &pci_dev_ops_pci, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 605 | }; |
| 606 | |
Tristan Corrick | d385624 | 2018-11-01 03:03:29 +1300 | [diff] [blame] | 607 | static const unsigned short mc_pci_device_ids[] = { |
| 608 | 0x0c00, /* Desktop */ |
| 609 | 0x0c04, /* Mobile */ |
| 610 | 0x0a04, /* ULT */ |
Iru Cai | 0766c98 | 2018-12-17 13:21:36 +0800 | [diff] [blame] | 611 | 0x0c08, /* Server */ |
Iru Cai | 12a13e1 | 2020-05-22 22:57:03 +0800 | [diff] [blame] | 612 | 0x0d00, /* Crystal Well Desktop */ |
| 613 | 0x0d04, /* Crystal Well Mobile */ |
| 614 | 0x0d08, /* Crystal Well Server (by extrapolation) */ |
Tristan Corrick | d385624 | 2018-11-01 03:03:29 +1300 | [diff] [blame] | 615 | 0 |
Tristan Corrick | 4817012 | 2018-10-31 02:21:41 +1300 | [diff] [blame] | 616 | }; |
| 617 | |
Tristan Corrick | d385624 | 2018-11-01 03:03:29 +1300 | [diff] [blame] | 618 | static const struct pci_driver mc_driver_hsw __pci_driver = { |
| 619 | .ops = &mc_ops, |
| 620 | .vendor = PCI_VENDOR_ID_INTEL, |
| 621 | .devices = mc_pci_device_ids, |
Duncan Laurie | df7be71 | 2012-12-17 11:22:57 -0800 | [diff] [blame] | 622 | }; |
| 623 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 624 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 625 | .read_resources = noop_read_resources, |
| 626 | .set_resources = noop_set_resources, |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 627 | .init = mp_cpu_bus_init, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 628 | }; |
| 629 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 630 | static void enable_dev(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 631 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 632 | /* Set the operations if it is a special bus type. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 633 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 634 | dev->ops = &pci_domain_ops; |
| 635 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 636 | dev->ops = &cpu_bus_ops; |
| 637 | } |
| 638 | } |
| 639 | |
| 640 | struct chip_operations northbridge_intel_haswell_ops = { |
| 641 | CHIP_NAME("Intel i7 (Haswell) integrated Northbridge") |
| 642 | .enable_dev = enable_dev, |
| 643 | }; |