|author||Angel Pons <email@example.com>||Thu Jul 23 02:37:12 2020 +0200|
|committer||Angel Pons <firstname.lastname@example.org>||Tue Jul 28 10:54:29 2020 +0000|
nb/intel/haswell: Enable DMI ASPM On Haswell platforms, the processor and the PCH are two separate dies, and communicate through a high-speed bus. This is DMI (Direct Media Interface) on traditional two-package platforms, but single-package Haswell LP variants use OPI (On-Package Interconnect) instead. Since OPI is not routed through the mainboard, most link parameters are static and cannot be changed. OPI self-initializes on boot, anyway. However, DMI needs to be initialized in firmware. On Haswell, the MRC initializes the physical DMI link, but things like topology and power management need to be configured as well. And we don't do that properly. We enable ASPM on the PCH side of the DMI link, but not on the SA side. Both sides need to use the same settings, so enable DMI ASPM on the SA. Clearing the error status bits needs to be done on all Haswell variants. Tested on Asrock B85M Pro4, still boots. Change-Id: Ie97ff56eec9f928cfd2d5d43a287f3e0d2fbf3cf Signed-off-by: Angel Pons <email@example.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43743 Tested-by: build bot (Jenkins) <firstname.lastname@example.org> Reviewed-by: Arthur Heymans <email@example.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAINKconfig option if you're feeling lucky (no support in this case).
Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.