Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2 | |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 3 | #include <commonlib/helpers.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 4 | #include <console/console.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 5 | #include <string.h> |
Subrata Banik | 53b08c3 | 2018-12-10 14:11:35 +0530 | [diff] [blame] | 6 | #include <arch/cpu.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 7 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 9 | #include <northbridge/intel/sandybridge/chip.h> |
| 10 | #include <device/pci_def.h> |
| 11 | #include <delay.h> |
Elyes HAOUAS | 1d3b3c3 | 2019-05-04 08:12:42 +0200 | [diff] [blame] | 12 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 13 | #include "raminit_native.h" |
| 14 | #include "raminit_common.h" |
Angel Pons | 7f6586f | 2020-03-21 12:45:12 +0100 | [diff] [blame] | 15 | #include "raminit_tables.h" |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 16 | #include "sandybridge.h" |
| 17 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 18 | /* FIXME: no support for 3-channel chipsets */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 19 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 20 | /* length: [1..4] */ |
| 21 | #define IOSAV_RUN_ONCE(length) ((((length) - 1) << 18) | 1) |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 22 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 23 | static void sfence(void) |
| 24 | { |
| 25 | asm volatile ("sfence"); |
| 26 | } |
| 27 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 28 | /* Toggle IO reset bit */ |
| 29 | static void toggle_io_reset(void) |
| 30 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 31 | u32 r32 = MCHBAR32(MC_INIT_STATE_G); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 32 | MCHBAR32(MC_INIT_STATE_G) = r32 | 0x20; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 33 | udelay(1); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 34 | MCHBAR32(MC_INIT_STATE_G) = r32 & ~0x20; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 35 | udelay(1); |
| 36 | } |
| 37 | |
| 38 | static u32 get_XOVER_CLK(u8 rankmap) |
| 39 | { |
| 40 | return rankmap << 24; |
| 41 | } |
| 42 | |
| 43 | static u32 get_XOVER_CMD(u8 rankmap) |
| 44 | { |
| 45 | u32 reg; |
| 46 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 47 | /* Enable xover cmd */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 48 | reg = 0x4000; |
| 49 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 50 | /* Enable xover ctl */ |
| 51 | if (rankmap & 0x03) |
| 52 | reg |= (1 << 17); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 53 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 54 | if (rankmap & 0x0c) |
| 55 | reg |= (1 << 26); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 56 | |
| 57 | return reg; |
| 58 | } |
| 59 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 60 | /* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 61 | u8 get_CWL(u32 tCK) |
| 62 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 63 | /* Get CWL based on tCK using the following rule */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 64 | switch (tCK) { |
| 65 | case TCK_1333MHZ: |
| 66 | return 12; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 67 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 68 | case TCK_1200MHZ: |
| 69 | case TCK_1100MHZ: |
| 70 | return 11; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 71 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 72 | case TCK_1066MHZ: |
| 73 | case TCK_1000MHZ: |
| 74 | return 10; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 75 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 76 | case TCK_933MHZ: |
| 77 | case TCK_900MHZ: |
| 78 | return 9; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 79 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 80 | case TCK_800MHZ: |
| 81 | case TCK_700MHZ: |
| 82 | return 8; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 83 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 84 | case TCK_666MHZ: |
| 85 | return 7; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 86 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 87 | case TCK_533MHZ: |
| 88 | return 6; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 89 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 90 | default: |
| 91 | return 5; |
| 92 | } |
| 93 | } |
| 94 | |
| 95 | void dram_find_common_params(ramctr_timing *ctrl) |
| 96 | { |
| 97 | size_t valid_dimms; |
| 98 | int channel, slot; |
| 99 | dimm_info *dimms = &ctrl->info; |
| 100 | |
| 101 | ctrl->cas_supported = (1 << (MAX_CAS - MIN_CAS + 1)) - 1; |
| 102 | valid_dimms = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 103 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 104 | FOR_ALL_CHANNELS for (slot = 0; slot < 2; slot++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 105 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 106 | const dimm_attr *dimm = &dimms->dimm[channel][slot]; |
| 107 | if (dimm->dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) |
| 108 | continue; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 109 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 110 | valid_dimms++; |
| 111 | |
| 112 | /* Find all possible CAS combinations */ |
| 113 | ctrl->cas_supported &= dimm->cas_supported; |
| 114 | |
| 115 | /* Find the smallest common latencies supported by all DIMMs */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 116 | ctrl->tCK = MAX(ctrl->tCK, dimm->tCK); |
| 117 | ctrl->tAA = MAX(ctrl->tAA, dimm->tAA); |
| 118 | ctrl->tWR = MAX(ctrl->tWR, dimm->tWR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 119 | ctrl->tRCD = MAX(ctrl->tRCD, dimm->tRCD); |
| 120 | ctrl->tRRD = MAX(ctrl->tRRD, dimm->tRRD); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 121 | ctrl->tRP = MAX(ctrl->tRP, dimm->tRP); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 122 | ctrl->tRAS = MAX(ctrl->tRAS, dimm->tRAS); |
| 123 | ctrl->tRFC = MAX(ctrl->tRFC, dimm->tRFC); |
| 124 | ctrl->tWTR = MAX(ctrl->tWTR, dimm->tWTR); |
| 125 | ctrl->tRTP = MAX(ctrl->tRTP, dimm->tRTP); |
| 126 | ctrl->tFAW = MAX(ctrl->tFAW, dimm->tFAW); |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 127 | ctrl->tCWL = MAX(ctrl->tCWL, dimm->tCWL); |
| 128 | ctrl->tCMD = MAX(ctrl->tCMD, dimm->tCMD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | if (!ctrl->cas_supported) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 132 | die("Unsupported DIMM combination. DIMMS do not support common CAS latency"); |
| 133 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 134 | if (!valid_dimms) |
| 135 | die("No valid DIMMs found"); |
| 136 | } |
| 137 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 138 | void dram_xover(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 139 | { |
| 140 | u32 reg; |
| 141 | int channel; |
| 142 | |
| 143 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 144 | /* Enable xover clk */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 145 | reg = get_XOVER_CLK(ctrl->rankmap[channel]); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 146 | printram("XOVER CLK [%x] = %x\n", GDCRCKPICODE_ch(channel), reg); |
| 147 | MCHBAR32(GDCRCKPICODE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 148 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 149 | /* Enable xover ctl & xover cmd */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 150 | reg = get_XOVER_CMD(ctrl->rankmap[channel]); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 151 | printram("XOVER CMD [%x] = %x\n", GDCRCMDPICODING_ch(channel), reg); |
| 152 | MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 153 | } |
| 154 | } |
| 155 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 156 | static void dram_odt_stretch(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 157 | { |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 158 | u32 addr, stretch; |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 159 | |
| 160 | stretch = ctrl->ref_card_offset[channel]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 161 | /* |
| 162 | * ODT stretch: |
| 163 | * Delay ODT signal by stretch value. Useful for multi DIMM setups on the same channel. |
| 164 | */ |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 165 | if (IS_SANDY_CPU(ctrl->cpu) && IS_SANDY_CPU_C(ctrl->cpu)) { |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 166 | if (stretch == 2) |
| 167 | stretch = 3; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 168 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 169 | addr = SCHED_SECOND_CBIT_ch(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 170 | MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10)); |
| 171 | printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 172 | } else { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 173 | addr = TC_OTHP_ch(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 174 | MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18)); |
Iru Cai | 89af71c | 2018-08-16 16:46:27 +0800 | [diff] [blame] | 175 | printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 176 | } |
| 177 | } |
| 178 | |
| 179 | void dram_timing_regs(ramctr_timing *ctrl) |
| 180 | { |
| 181 | u32 reg, addr, val32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 182 | int channel; |
| 183 | |
| 184 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 185 | /* BIN parameters */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 186 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 187 | reg |= (ctrl->tRCD << 0); |
| 188 | reg |= (ctrl->tRP << 4); |
| 189 | reg |= (ctrl->CAS << 8); |
| 190 | reg |= (ctrl->CWL << 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 191 | reg |= (ctrl->tRAS << 16); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 192 | printram("DBP [%x] = %x\n", TC_DBP_ch(channel), reg); |
| 193 | MCHBAR32(TC_DBP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 194 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 195 | /* Regular access parameters */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 196 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 197 | reg |= (ctrl->tRRD << 0); |
| 198 | reg |= (ctrl->tRTP << 4); |
| 199 | reg |= (ctrl->tCKE << 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 200 | reg |= (ctrl->tWTR << 12); |
| 201 | reg |= (ctrl->tFAW << 16); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 202 | reg |= (ctrl->tWR << 24); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 203 | reg |= (3 << 30); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 204 | printram("RAP [%x] = %x\n", TC_RAP_ch(channel), reg); |
| 205 | MCHBAR32(TC_RAP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 206 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 207 | /* Other parameters */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 208 | addr = TC_OTHP_ch(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 209 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 210 | reg |= (ctrl->tXPDLL << 0); |
| 211 | reg |= (ctrl->tXP << 5); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 212 | reg |= (ctrl->tAONPD << 8); |
| 213 | reg |= 0xa0000; |
| 214 | printram("OTHP [%x] = %x\n", addr, reg); |
| 215 | MCHBAR32(addr) = reg; |
| 216 | |
Angel Pons | ca2f68a | 2020-03-22 13:15:12 +0100 | [diff] [blame] | 217 | /* Debug parameters - only applies to Ivy Bridge */ |
| 218 | if (IS_IVY_CPU(ctrl->cpu)) { |
| 219 | reg = 0; |
| 220 | |
| 221 | /* |
| 222 | * If tXP and tXPDLL are very high, we need to increase them by one. |
| 223 | * This can only happen on Ivy Bridge, and when overclocking the RAM. |
| 224 | */ |
| 225 | if (ctrl->tXP >= 8) |
| 226 | reg |= (1 << 12); |
| 227 | |
| 228 | if (ctrl->tXPDLL >= 32) |
| 229 | reg |= (1 << 13); |
| 230 | |
| 231 | MCHBAR32(TC_DTP_ch(channel)) = reg; |
| 232 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 233 | |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 234 | MCHBAR32_OR(addr, 0x00020000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 235 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 236 | dram_odt_stretch(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 237 | |
Patrick Rudolph | 5ee9bc1 | 2017-10-31 10:49:52 +0100 | [diff] [blame] | 238 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 239 | * TC-Refresh timing parameters: |
| 240 | * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow |
| 241 | * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024. |
Patrick Rudolph | 5ee9bc1 | 2017-10-31 10:49:52 +0100 | [diff] [blame] | 242 | */ |
| 243 | val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); |
| 244 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 245 | reg = ((ctrl->tREFI & 0xffff) << 0) | |
| 246 | ((ctrl->tRFC & 0x01ff) << 16) | (((val32 / 1024) & 0x7f) << 25); |
| 247 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 248 | printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), reg); |
| 249 | MCHBAR32(TC_RFTP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 250 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 251 | MCHBAR32_OR(TC_RFP_ch(channel), 0xff); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 252 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 253 | /* Self-refresh timing parameters */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 254 | reg = 0; |
| 255 | val32 = tDLLK; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 256 | reg = (reg & ~0x00000fff) | (val32 << 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 257 | val32 = ctrl->tXSOffset; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 258 | reg = (reg & ~0x0000f000) | (val32 << 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 259 | val32 = tDLLK - ctrl->tXSOffset; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 260 | reg = (reg & ~0x03ff0000) | (val32 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 261 | val32 = ctrl->tMOD - 8; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 262 | reg = (reg & ~0xf0000000) | (val32 << 28); |
| 263 | printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), reg); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 264 | MCHBAR32(TC_SRFTP_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 265 | } |
| 266 | } |
| 267 | |
| 268 | void dram_dimm_mapping(ramctr_timing *ctrl) |
| 269 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 270 | int channel; |
| 271 | dimm_info *info = &ctrl->info; |
| 272 | |
| 273 | FOR_ALL_CHANNELS { |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 274 | dimm_attr *dimmA, *dimmB; |
| 275 | u32 reg = 0; |
| 276 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 277 | if (info->dimm[channel][0].size_mb >= info->dimm[channel][1].size_mb) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 278 | dimmA = &info->dimm[channel][0]; |
| 279 | dimmB = &info->dimm[channel][1]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 280 | reg |= (0 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 281 | } else { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 282 | dimmA = &info->dimm[channel][1]; |
| 283 | dimmB = &info->dimm[channel][0]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 284 | reg |= (1 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 285 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 286 | |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 287 | if (dimmA && (dimmA->ranks > 0)) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 288 | reg |= (dimmA->size_mb / 256) << 0; |
| 289 | reg |= (dimmA->ranks - 1) << 17; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 290 | reg |= (dimmA->width / 8 - 1) << 19; |
| 291 | } |
| 292 | |
| 293 | if (dimmB && (dimmB->ranks > 0)) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 294 | reg |= (dimmB->size_mb / 256) << 8; |
| 295 | reg |= (dimmB->ranks - 1) << 18; |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 296 | reg |= (dimmB->width / 8 - 1) << 20; |
| 297 | } |
| 298 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 299 | reg |= 1 << 21; /* Rank interleave */ |
| 300 | reg |= 1 << 22; /* Enhanced interleave */ |
Nico Huber | ac4f216 | 2017-10-01 18:14:43 +0200 | [diff] [blame] | 301 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 302 | if ((dimmA && (dimmA->ranks > 0)) || (dimmB && (dimmB->ranks > 0))) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 303 | ctrl->mad_dimm[channel] = reg; |
| 304 | } else { |
| 305 | ctrl->mad_dimm[channel] = 0; |
| 306 | } |
| 307 | } |
| 308 | } |
| 309 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 310 | void dram_dimm_set_mapping(ramctr_timing *ctrl, int training) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 311 | { |
| 312 | int channel; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 313 | u32 ecc; |
| 314 | |
| 315 | if (ctrl->ecc_enabled) |
| 316 | ecc = training ? (1 << 24) : (3 << 24); |
| 317 | else |
| 318 | ecc = 0; |
| 319 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 320 | FOR_ALL_CHANNELS { |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 321 | MCHBAR32(MAD_DIMM(channel)) = ctrl->mad_dimm[channel] | ecc; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 322 | } |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 323 | |
| 324 | //udelay(10); /* TODO: Might be needed for ECC configurations; so far works without. */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 325 | } |
| 326 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 327 | void dram_zones(ramctr_timing *ctrl, int training) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 328 | { |
| 329 | u32 reg, ch0size, ch1size; |
| 330 | u8 val; |
| 331 | reg = 0; |
| 332 | val = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 333 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 334 | if (training) { |
| 335 | ch0size = ctrl->channel_size_mb[0] ? 256 : 0; |
| 336 | ch1size = ctrl->channel_size_mb[1] ? 256 : 0; |
| 337 | } else { |
| 338 | ch0size = ctrl->channel_size_mb[0]; |
| 339 | ch1size = ctrl->channel_size_mb[1]; |
| 340 | } |
| 341 | |
| 342 | if (ch0size >= ch1size) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 343 | reg = MCHBAR32(MAD_ZR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 344 | val = ch1size / 256; |
| 345 | reg = (reg & ~0xff000000) | val << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 346 | reg = (reg & ~0x00ff0000) | (2 * val) << 16; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 347 | MCHBAR32(MAD_ZR) = reg; |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 348 | MCHBAR32(MAD_CHNL) = 0x24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 349 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 350 | } else { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 351 | reg = MCHBAR32(MAD_ZR); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 352 | val = ch0size / 256; |
| 353 | reg = (reg & ~0xff000000) | val << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 354 | reg = (reg & ~0x00ff0000) | (2 * val) << 16; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 355 | MCHBAR32(MAD_ZR) = reg; |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 356 | MCHBAR32(MAD_CHNL) = 0x21; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 357 | } |
| 358 | } |
| 359 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 360 | #define DEFAULT_PCI_MMIO_SIZE 2048 |
| 361 | |
| 362 | static unsigned int get_mmio_size(void) |
| 363 | { |
| 364 | const struct device *dev; |
| 365 | const struct northbridge_intel_sandybridge_config *cfg = NULL; |
| 366 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 367 | dev = pcidev_path_on_root(PCI_DEVFN(0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 368 | if (dev) |
| 369 | cfg = dev->chip_info; |
| 370 | |
| 371 | /* If this is zero, it just means devicetree.cb didn't set it */ |
| 372 | if (!cfg || cfg->pci_mmio_size == 0) |
| 373 | return DEFAULT_PCI_MMIO_SIZE; |
| 374 | else |
| 375 | return cfg->pci_mmio_size; |
| 376 | } |
| 377 | |
Patrick Rudolph | 05d4bf7e | 2017-10-28 16:36:09 +0200 | [diff] [blame] | 378 | /* |
| 379 | * Returns the ECC mode the NB is running at. It takes precedence over ECC capability. |
| 380 | * The ME/PCU/.. has the ability to change this. |
| 381 | * Return 0: ECC is optional |
| 382 | * Return 1: ECC is forced |
| 383 | */ |
| 384 | bool get_host_ecc_forced(void) |
| 385 | { |
| 386 | /* read Capabilities A Register */ |
| 387 | const u32 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 388 | return !!(reg32 & (1 << 24)); |
| 389 | } |
| 390 | |
| 391 | /* |
| 392 | * Returns the ECC capability. |
| 393 | * The ME/PCU/.. has the ability to change this. |
| 394 | * Return 0: ECC is disabled |
| 395 | * Return 1: ECC is possible |
| 396 | */ |
| 397 | bool get_host_ecc_cap(void) |
| 398 | { |
| 399 | /* read Capabilities A Register */ |
| 400 | const u32 reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 401 | return !(reg32 & (1 << 25)); |
| 402 | } |
| 403 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 404 | void dram_memorymap(ramctr_timing *ctrl, int me_uma_size) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 405 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 406 | u32 reg, val, reclaim, tom, gfxstolen, gttsize; |
| 407 | size_t tsegbase, toludbase, remapbase, gfxstolenbase, mmiosize, gttbase; |
| 408 | size_t tsegsize, touudbase, remaplimit, mestolenbase, tsegbasedelta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 409 | uint16_t ggc; |
| 410 | |
| 411 | mmiosize = get_mmio_size(); |
| 412 | |
Felix Held | 87ddea2 | 2020-01-26 04:55:27 +0100 | [diff] [blame] | 413 | ggc = pci_read_config16(HOST_BRIDGE, GGC); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 414 | if (!(ggc & 2)) { |
| 415 | gfxstolen = ((ggc >> 3) & 0x1f) * 32; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 416 | gttsize = ((ggc >> 8) & 0x3); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 417 | } else { |
| 418 | gfxstolen = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 419 | gttsize = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 420 | } |
| 421 | |
| 422 | tsegsize = CONFIG_SMM_TSEG_SIZE >> 20; |
| 423 | |
| 424 | tom = ctrl->channel_size_mb[0] + ctrl->channel_size_mb[1]; |
| 425 | |
| 426 | mestolenbase = tom - me_uma_size; |
| 427 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 428 | toludbase = MIN(4096 - mmiosize + gfxstolen + gttsize + tsegsize, tom - me_uma_size); |
| 429 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 430 | gfxstolenbase = toludbase - gfxstolen; |
| 431 | gttbase = gfxstolenbase - gttsize; |
| 432 | |
| 433 | tsegbase = gttbase - tsegsize; |
| 434 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 435 | /* Round tsegbase down to nearest address aligned to tsegsize */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 436 | tsegbasedelta = tsegbase & (tsegsize - 1); |
| 437 | tsegbase &= ~(tsegsize - 1); |
| 438 | |
| 439 | gttbase -= tsegbasedelta; |
| 440 | gfxstolenbase -= tsegbasedelta; |
| 441 | toludbase -= tsegbasedelta; |
| 442 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 443 | /* Test if it is possible to reclaim a hole in the RAM addressing */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 444 | if (tom - me_uma_size > toludbase) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 445 | /* Reclaim is possible */ |
| 446 | reclaim = 1; |
| 447 | remapbase = MAX(4096, tom - me_uma_size); |
| 448 | remaplimit = remapbase + MIN(4096, tom - me_uma_size) - toludbase - 1; |
| 449 | touudbase = remaplimit + 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 450 | } else { |
| 451 | // Reclaim not possible |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 452 | reclaim = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 453 | touudbase = tom - me_uma_size; |
| 454 | } |
| 455 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 456 | /* Update memory map in PCIe configuration space */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 457 | printk(BIOS_DEBUG, "Update PCI-E configuration space:\n"); |
| 458 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 459 | /* TOM (top of memory) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 460 | reg = pci_read_config32(HOST_BRIDGE, TOM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 461 | val = tom & 0xfff; |
| 462 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 463 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 464 | pci_write_config32(HOST_BRIDGE, TOM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 465 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 466 | reg = pci_read_config32(HOST_BRIDGE, TOM + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 467 | val = tom & 0xfffff000; |
| 468 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 469 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOM + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 470 | pci_write_config32(HOST_BRIDGE, TOM + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 471 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 472 | /* TOLUD (Top Of Low Usable DRAM) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 473 | reg = pci_read_config32(HOST_BRIDGE, TOLUD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 474 | val = toludbase & 0xfff; |
| 475 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 476 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOLUD, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 477 | pci_write_config32(HOST_BRIDGE, TOLUD, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 478 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 479 | /* TOUUD LSB (Top Of Upper Usable DRAM) */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 480 | reg = pci_read_config32(HOST_BRIDGE, TOUUD); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 481 | val = touudbase & 0xfff; |
| 482 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 483 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 484 | pci_write_config32(HOST_BRIDGE, TOUUD, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 485 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 486 | /* TOUUD MSB */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 487 | reg = pci_read_config32(HOST_BRIDGE, TOUUD + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 488 | val = touudbase & 0xfffff000; |
| 489 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 490 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TOUUD + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 491 | pci_write_config32(HOST_BRIDGE, TOUUD + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 492 | |
| 493 | if (reclaim) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 494 | /* REMAP BASE */ |
| 495 | pci_write_config32(HOST_BRIDGE, REMAPBASE, remapbase << 20); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 496 | pci_write_config32(HOST_BRIDGE, REMAPBASE + 4, remapbase >> 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 497 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 498 | /* REMAP LIMIT */ |
| 499 | pci_write_config32(HOST_BRIDGE, REMAPLIMIT, remaplimit << 20); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 500 | pci_write_config32(HOST_BRIDGE, REMAPLIMIT + 4, remaplimit >> 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 501 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 502 | /* TSEG */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 503 | reg = pci_read_config32(HOST_BRIDGE, TSEGMB); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 504 | val = tsegbase & 0xfff; |
| 505 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 506 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", TSEGMB, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 507 | pci_write_config32(HOST_BRIDGE, TSEGMB, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 508 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 509 | /* GFX stolen memory */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 510 | reg = pci_read_config32(HOST_BRIDGE, BDSM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 511 | val = gfxstolenbase & 0xfff; |
| 512 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 513 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BDSM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 514 | pci_write_config32(HOST_BRIDGE, BDSM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 515 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 516 | /* GTT stolen memory */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 517 | reg = pci_read_config32(HOST_BRIDGE, BGSM); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 518 | val = gttbase & 0xfff; |
| 519 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 4902fee | 2019-12-28 18:09:47 +0100 | [diff] [blame] | 520 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", BGSM, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 521 | pci_write_config32(HOST_BRIDGE, BGSM, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 522 | |
| 523 | if (me_uma_size) { |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 524 | reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 525 | val = (0x80000 - me_uma_size) & 0xfffff000; |
| 526 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 527 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 528 | pci_write_config32(HOST_BRIDGE, MESEG_MASK + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 529 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 530 | /* ME base */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 531 | reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 532 | val = mestolenbase & 0xfff; |
| 533 | reg = (reg & ~0xfff00000) | (val << 20); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 534 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 535 | pci_write_config32(HOST_BRIDGE, MESEG_BASE, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 536 | |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 537 | reg = pci_read_config32(HOST_BRIDGE, MESEG_BASE + 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 538 | val = mestolenbase & 0xfffff000; |
| 539 | reg = (reg & ~0x000fffff) | (val >> 12); |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 540 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE + 4, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 541 | pci_write_config32(HOST_BRIDGE, MESEG_BASE + 4, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 542 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 543 | /* ME mask */ |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 544 | reg = pci_read_config32(HOST_BRIDGE, MESEG_MASK); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 545 | val = (0x80000 - me_uma_size) & 0xfff; |
| 546 | reg = (reg & ~0xfff00000) | (val << 20); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 547 | reg = reg | ME_STLEN_EN; /* Set ME memory enable */ |
| 548 | reg = reg | MELCK; /* Set lock bit on ME mem */ |
Felix Held | 651f99f | 2019-12-30 16:28:48 +0100 | [diff] [blame] | 549 | printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg); |
Angel Pons | b31d1d7 | 2020-01-10 01:35:09 +0100 | [diff] [blame] | 550 | pci_write_config32(HOST_BRIDGE, MESEG_MASK, reg); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 551 | } |
| 552 | } |
| 553 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 554 | static void wait_for_iosav(int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 555 | { |
| 556 | while (1) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 557 | if (MCHBAR32(IOSAV_STATUS_ch(channel)) & 0x50) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 558 | return; |
| 559 | } |
| 560 | } |
| 561 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 562 | static void write_reset(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 563 | { |
| 564 | int channel, slotrank; |
| 565 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 566 | /* Choose a populated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 567 | channel = (ctrl->rankmap[0]) ? 0 : 1; |
| 568 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 569 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 570 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 571 | /* Choose a populated rank */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 572 | slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; |
| 573 | |
| 574 | /* DRAM command ZQCS */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 575 | IOSAV_SUBSEQUENCE(channel, 0, |
| 576 | IOSAV_ZQCS & NO_RANKSEL, |
| 577 | 1, 3, 8, SSQ_NA, |
| 578 | 0, 6, 0, slotrank, |
| 579 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 580 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 581 | /* |
| 582 | * Execute command queue - why is bit 22 set here?! |
| 583 | * |
| 584 | * This is actually using the IOSAV state machine as a timer, so refresh is allowed. |
| 585 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 586 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = (1 << 22) | IOSAV_RUN_ONCE(1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 587 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 588 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 589 | } |
| 590 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 591 | void dram_jedecreset(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 592 | { |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 593 | u32 reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 594 | int channel; |
| 595 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 596 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 597 | ; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 598 | do { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 599 | reg = MCHBAR32(IOSAV_STATUS_ch(0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 600 | } while ((reg & 0x14) == 0); |
| 601 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 602 | /* Set state of memory controller */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 603 | reg = 0x112; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 604 | MCHBAR32(MC_INIT_STATE_G) = reg; |
| 605 | MCHBAR32(MC_INIT_STATE) = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 606 | reg |= 2; /* DDR reset */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 607 | MCHBAR32(MC_INIT_STATE_G) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 608 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 609 | /* Assert DIMM reset signal */ |
| 610 | MCHBAR32_AND(MC_INIT_STATE_G, ~2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 611 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 612 | /* Wait 200us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 613 | udelay(200); |
| 614 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 615 | /* Deassert DIMM reset signal */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 616 | MCHBAR32_OR(MC_INIT_STATE_G, 2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 617 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 618 | /* Wait 500us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 619 | udelay(500); |
| 620 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 621 | /* Enable DCLK */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 622 | MCHBAR32_OR(MC_INIT_STATE_G, 4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 623 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 624 | /* XXX Wait 20ns */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 625 | udelay(1); |
| 626 | |
| 627 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 628 | /* Set valid rank CKE */ |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 629 | reg = ctrl->rankmap[channel]; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 630 | MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 631 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 632 | /* Wait 10ns for ranks to settle */ |
| 633 | // udelay(0.01); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 634 | |
| 635 | reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 636 | MCHBAR32(MC_INIT_STATE_ch(channel)) = reg; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 637 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 638 | /* Write reset using a NOP */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 639 | write_reset(ctrl); |
| 640 | } |
| 641 | } |
| 642 | |
| 643 | static odtmap get_ODT(ramctr_timing *ctrl, u8 rank, int channel) |
| 644 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 645 | /* Get ODT based on rankmap */ |
| 646 | int dimms_per_ch = (ctrl->rankmap[channel] & 1) + ((ctrl->rankmap[channel] >> 2) & 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 647 | |
| 648 | if (dimms_per_ch == 1) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 649 | return (const odtmap){60, 60}; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 650 | } else { |
| 651 | return (const odtmap){120, 30}; |
| 652 | } |
| 653 | } |
| 654 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 655 | static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, u32 val) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 656 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 657 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 658 | |
| 659 | if (ctrl->rank_mirror[channel][slotrank]) { |
| 660 | /* DDR3 Rank1 Address mirror |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 661 | swap the following pins: |
| 662 | A3<->A4, A5<->A6, A7<->A8, BA0<->BA1 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 663 | reg = ((reg >> 1) & 1) | ((reg << 1) & 2); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 664 | val = (val & ~0x1f8) | ((val >> 1) & 0xa8) | ((val & 0xa8) << 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 665 | } |
| 666 | |
| 667 | /* DRAM command MRS */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 668 | IOSAV_SUBSEQUENCE(channel, 0, |
| 669 | IOSAV_MRS & NO_RANKSEL, |
| 670 | 1, 4, 4, SSQ_NA, |
| 671 | val, 6, reg, slotrank, |
| 672 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 673 | |
| 674 | /* DRAM command MRS */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 675 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 676 | IOSAV_MRS | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 677 | 1, 4, 4, SSQ_NA, |
| 678 | val, 6, reg, slotrank, |
| 679 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 680 | |
| 681 | /* DRAM command MRS */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 682 | IOSAV_SUBSEQUENCE(channel, 2, |
| 683 | IOSAV_MRS & NO_RANKSEL, |
| 684 | 1, 4, ctrl->tMOD, SSQ_NA, |
| 685 | val, 6, reg, slotrank, |
| 686 | ADDR_UPDATE_NONE); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 687 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 688 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 689 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 690 | } |
| 691 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 692 | static u32 make_mr0(ramctr_timing *ctrl, u8 rank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 693 | { |
| 694 | u16 mr0reg, mch_cas, mch_wr; |
| 695 | static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 696 | const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 697 | |
| 698 | /* DLL Reset - self clearing - set after CLK frequency has been changed */ |
| 699 | mr0reg = 0x100; |
| 700 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 701 | /* Convert CAS to MCH register friendly */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 702 | if (ctrl->CAS < 12) { |
| 703 | mch_cas = (u16) ((ctrl->CAS - 4) << 1); |
| 704 | } else { |
| 705 | mch_cas = (u16) (ctrl->CAS - 12); |
| 706 | mch_cas = ((mch_cas << 1) | 0x1); |
| 707 | } |
| 708 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 709 | /* Convert tWR to MCH register friendly */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 710 | mch_wr = mch_wr_t[ctrl->tWR - 5]; |
| 711 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 712 | mr0reg = (mr0reg & ~0x0004) | ((mch_cas & 0x1) << 2); |
| 713 | mr0reg = (mr0reg & ~0x0070) | ((mch_cas & 0xe) << 3); |
| 714 | mr0reg = (mr0reg & ~0x0e00) | (mch_wr << 9); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 715 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 716 | /* Precharge PD - Fast (desktop) 1 or slow (mobile) 0 - mostly power-saving feature */ |
| 717 | mr0reg = (mr0reg & ~(1 << 12)) | (!is_mobile << 12); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 718 | return mr0reg; |
| 719 | } |
| 720 | |
| 721 | static void dram_mr0(ramctr_timing *ctrl, u8 rank, int channel) |
| 722 | { |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 723 | write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, rank)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 724 | } |
| 725 | |
| 726 | static u32 encode_odt(u32 odt) |
| 727 | { |
| 728 | switch (odt) { |
| 729 | case 30: |
| 730 | return (1 << 9) | (1 << 2); // RZQ/8, RZQ/4 |
| 731 | case 60: |
| 732 | return (1 << 2); // RZQ/4 |
| 733 | case 120: |
| 734 | return (1 << 6); // RZQ/2 |
| 735 | default: |
| 736 | case 0: |
| 737 | return 0; |
| 738 | } |
| 739 | } |
| 740 | |
| 741 | static u32 make_mr1(ramctr_timing *ctrl, u8 rank, int channel) |
| 742 | { |
| 743 | odtmap odt; |
| 744 | u32 mr1reg; |
| 745 | |
| 746 | odt = get_ODT(ctrl, rank, channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 747 | mr1reg = 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 748 | |
| 749 | mr1reg |= encode_odt(odt.rttnom); |
| 750 | |
| 751 | return mr1reg; |
| 752 | } |
| 753 | |
| 754 | static void dram_mr1(ramctr_timing *ctrl, u8 rank, int channel) |
| 755 | { |
| 756 | u16 mr1reg; |
| 757 | |
| 758 | mr1reg = make_mr1(ctrl, rank, channel); |
| 759 | |
| 760 | write_mrreg(ctrl, channel, rank, 1, mr1reg); |
| 761 | } |
| 762 | |
| 763 | static void dram_mr2(ramctr_timing *ctrl, u8 rank, int channel) |
| 764 | { |
| 765 | u16 pasr, cwl, mr2reg; |
| 766 | odtmap odt; |
| 767 | int srt; |
| 768 | |
| 769 | pasr = 0; |
| 770 | cwl = ctrl->CWL - 5; |
| 771 | odt = get_ODT(ctrl, rank, channel); |
| 772 | |
| 773 | srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; |
| 774 | |
| 775 | mr2reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 776 | mr2reg = (mr2reg & ~0x07) | pasr; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 777 | mr2reg = (mr2reg & ~0x38) | (cwl << 3); |
| 778 | mr2reg = (mr2reg & ~0x40) | (ctrl->auto_self_refresh << 6); |
| 779 | mr2reg = (mr2reg & ~0x80) | (srt << 7); |
| 780 | mr2reg |= (odt.rttwr / 60) << 9; |
| 781 | |
| 782 | write_mrreg(ctrl, channel, rank, 2, mr2reg); |
| 783 | } |
| 784 | |
| 785 | static void dram_mr3(ramctr_timing *ctrl, u8 rank, int channel) |
| 786 | { |
| 787 | write_mrreg(ctrl, channel, rank, 3, 0); |
| 788 | } |
| 789 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 790 | void dram_mrscommands(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 791 | { |
| 792 | u8 slotrank; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 793 | int channel; |
| 794 | |
| 795 | FOR_ALL_POPULATED_CHANNELS { |
| 796 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 797 | /* MR2 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 798 | dram_mr2(ctrl, slotrank, channel); |
| 799 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 800 | /* MR3 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 801 | dram_mr3(ctrl, slotrank, channel); |
| 802 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 803 | /* MR1 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 804 | dram_mr1(ctrl, slotrank, channel); |
| 805 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 806 | /* MR0 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 807 | dram_mr0(ctrl, slotrank, channel); |
| 808 | } |
| 809 | } |
| 810 | |
Angel Pons | 69e1714 | 2020-03-23 12:26:29 +0100 | [diff] [blame] | 811 | /* DRAM command NOP (without ODT nor chip selects) */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 812 | IOSAV_SUBSEQUENCE(BROADCAST_CH, 0, |
| 813 | IOSAV_NOP & NO_RANKSEL & ~(0xff << 8), |
| 814 | 1, 4, 15, SSQ_NA, |
| 815 | 2, 6, 0, 0, |
| 816 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 817 | |
| 818 | /* DRAM command ZQCL */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 819 | IOSAV_SUBSEQUENCE(BROADCAST_CH, 1, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 820 | IOSAV_ZQCS | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 821 | 1, 4, 400, SSQ_NA, |
| 822 | 1024, 6, 0, 0, |
| 823 | ADDR_UPDATE(0, 0, 0, 1, 20, 0, 0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 824 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 825 | /* Execute command queue on all channels. Do it four times. */ |
| 826 | MCHBAR32(IOSAV_SEQ_CTL) = (1 << 18) | 4; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 827 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 828 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 829 | /* Wait for ref drained */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 830 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 831 | } |
| 832 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 833 | /* Refresh enable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 834 | MCHBAR32_OR(MC_INIT_STATE_G, 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 835 | |
| 836 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 837 | MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 838 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 839 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 840 | |
| 841 | slotrank = (ctrl->rankmap[channel] & 1) ? 0 : 2; |
| 842 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 843 | /* Drain */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 844 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 845 | |
| 846 | /* DRAM command ZQCS */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 847 | IOSAV_SUBSEQUENCE(channel, 0, |
| 848 | IOSAV_ZQCS & NO_RANKSEL, |
| 849 | 1, 36, 101, SSQ_NA, |
| 850 | 0, 6, 0, slotrank, |
| 851 | ADDR_UPDATE_WRAP(31)); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 852 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 853 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 854 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 855 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 856 | /* Drain */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 857 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 858 | } |
| 859 | } |
| 860 | |
Felix Held | 3b90603 | 2020-01-14 17:05:43 +0100 | [diff] [blame] | 861 | static const u32 lane_base[] = { |
| 862 | LANEBASE_B0, LANEBASE_B1, LANEBASE_B2, LANEBASE_B3, |
| 863 | LANEBASE_B4, LANEBASE_B5, LANEBASE_B6, LANEBASE_B7, |
| 864 | LANEBASE_ECC |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 865 | }; |
| 866 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 867 | void program_timings(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 868 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 869 | u32 reg32, reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 870 | int lane; |
| 871 | int slotrank, slot; |
| 872 | int full_shift = 0; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 873 | u16 pi_coding_ctrl[NUM_SLOTS]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 874 | |
| 875 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 876 | if (full_shift < -ctrl->timings[channel][slotrank].pi_coding) |
| 877 | full_shift = -ctrl->timings[channel][slotrank].pi_coding; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 878 | } |
| 879 | |
| 880 | for (slot = 0; slot < NUM_SLOTS; slot++) |
| 881 | switch ((ctrl->rankmap[channel] >> (2 * slot)) & 3) { |
| 882 | case 0: |
| 883 | default: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 884 | pi_coding_ctrl[slot] = 0x7f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 885 | break; |
| 886 | case 1: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 887 | pi_coding_ctrl[slot] = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 888 | ctrl->timings[channel][2 * slot + 0].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 889 | break; |
| 890 | case 2: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 891 | pi_coding_ctrl[slot] = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 892 | ctrl->timings[channel][2 * slot + 1].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 893 | break; |
| 894 | case 3: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 895 | pi_coding_ctrl[slot] = |
| 896 | (ctrl->timings[channel][2 * slot].pi_coding + |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 897 | ctrl->timings[channel][2 * slot + 1].pi_coding) / 2 + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 898 | break; |
| 899 | } |
| 900 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 901 | /* Enable CMD XOVER */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 902 | reg32 = get_XOVER_CMD(ctrl->rankmap[channel]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 903 | reg32 |= (pi_coding_ctrl[0] & 0x3f) << 6; |
| 904 | reg32 |= (pi_coding_ctrl[0] & 0x40) << 9; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 905 | reg32 |= (pi_coding_ctrl[1] & 0x7f) << 18; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 906 | reg32 |= (full_shift & 0x3f) | ((full_shift & 0x40) << 6); |
| 907 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 908 | MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 909 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 910 | /* Enable CLK XOVER */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 911 | reg_pi_code = get_XOVER_CLK(ctrl->rankmap[channel]); |
| 912 | reg_logic_delay = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 913 | |
| 914 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 915 | int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 916 | int offset_pi_code; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 917 | if (shift < 0) |
| 918 | shift = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 919 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 920 | offset_pi_code = ctrl->pi_code_offset + shift; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 921 | |
| 922 | /* Set CLK phase shift */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 923 | reg_pi_code |= (offset_pi_code & 0x3f) << (6 * slotrank); |
| 924 | reg_logic_delay |= ((offset_pi_code >> 6) & 1) << slotrank; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 925 | } |
| 926 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 927 | MCHBAR32(GDCRCKPICODE_ch(channel)) = reg_pi_code; |
| 928 | MCHBAR32(GDCRCKLOGICDELAY_ch(channel)) = reg_logic_delay; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 929 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 930 | reg_io_latency = MCHBAR32(SC_IO_LATENCY_ch(channel)); |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 931 | reg_io_latency &= 0xffff0000; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 932 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 933 | reg_roundtrip_latency = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 934 | |
| 935 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 936 | int post_timA_min_high = 7, pre_timA_min_high = 7; |
| 937 | int post_timA_max_high = 0, pre_timA_max_high = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 938 | int shift_402x = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 939 | int shift = ctrl->timings[channel][slotrank].pi_coding + full_shift; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 940 | |
| 941 | if (shift < 0) |
| 942 | shift = 0; |
| 943 | |
| 944 | FOR_ALL_LANES { |
Arthur Heymans | abc504f | 2017-05-15 09:36:44 +0200 | [diff] [blame] | 945 | post_timA_min_high = MIN(post_timA_min_high, |
| 946 | (ctrl->timings[channel][slotrank].lanes[lane]. |
| 947 | timA + shift) >> 6); |
| 948 | pre_timA_min_high = MIN(pre_timA_min_high, |
| 949 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 950 | timA >> 6); |
| 951 | post_timA_max_high = MAX(post_timA_max_high, |
| 952 | (ctrl->timings[channel][slotrank].lanes[lane]. |
| 953 | timA + shift) >> 6); |
| 954 | pre_timA_max_high = MAX(pre_timA_max_high, |
| 955 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 956 | timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 957 | } |
| 958 | |
| 959 | if (pre_timA_max_high - pre_timA_min_high < |
| 960 | post_timA_max_high - post_timA_min_high) |
| 961 | shift_402x = +1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 962 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 963 | else if (pre_timA_max_high - pre_timA_min_high > |
| 964 | post_timA_max_high - post_timA_min_high) |
| 965 | shift_402x = -1; |
| 966 | |
Felix Held | dee167e | 2019-12-30 17:30:16 +0100 | [diff] [blame] | 967 | reg_io_latency |= |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 968 | (ctrl->timings[channel][slotrank].io_latency + shift_402x - |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 969 | post_timA_min_high) << (4 * slotrank); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 970 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 971 | reg_roundtrip_latency |= |
| 972 | (ctrl->timings[channel][slotrank].roundtrip_latency + |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 973 | shift_402x) << (8 * slotrank); |
| 974 | |
| 975 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 976 | MCHBAR32(lane_base[lane] + GDCRRX(channel, slotrank)) = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 977 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 978 | timA + shift) & 0x3f) |
| 979 | | |
| 980 | ((ctrl->timings[channel][slotrank].lanes[lane]. |
| 981 | rising + shift) << 8) |
| 982 | | |
| 983 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 984 | timA + shift - |
| 985 | (post_timA_min_high << 6)) & 0x1c0) << 10) |
| 986 | | ((ctrl->timings[channel][slotrank].lanes[lane]. |
| 987 | falling + shift) << 20)); |
| 988 | |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 989 | MCHBAR32(lane_base[lane] + GDCRTX(channel, slotrank)) = |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 990 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 991 | timC + shift) & 0x3f) |
| 992 | | |
| 993 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 994 | timB + shift) & 0x3f) << 8) |
| 995 | | |
| 996 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 997 | timB + shift) & 0x1c0) << 9) |
| 998 | | |
| 999 | (((ctrl->timings[channel][slotrank].lanes[lane]. |
| 1000 | timC + shift) & 0x40) << 13)); |
| 1001 | } |
| 1002 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1003 | MCHBAR32(SC_ROUNDT_LAT_ch(channel)) = reg_roundtrip_latency; |
| 1004 | MCHBAR32(SC_IO_LATENCY_ch(channel)) = reg_io_latency; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1005 | } |
| 1006 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1007 | static void test_timA(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1008 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1009 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1010 | |
| 1011 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1012 | write MR3 MPR enable |
| 1013 | in this mode only RD and RDA are allowed |
| 1014 | all reads return a predefined pattern */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1015 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1016 | IOSAV_MRS | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1017 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 1018 | 4, 6, 3, slotrank, |
| 1019 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1020 | |
| 1021 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1022 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1023 | IOSAV_RD | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1024 | 1, 3, 4, SSQ_RD, |
| 1025 | 0, 0, 0, slotrank, |
| 1026 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1027 | |
| 1028 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1029 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1030 | IOSAV_RD | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1031 | 15, 4, ctrl->CAS + 36, SSQ_NA, |
| 1032 | 0, 6, 0, slotrank, |
| 1033 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1034 | |
| 1035 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1036 | write MR3 MPR disable */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1037 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1038 | IOSAV_MRS | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1039 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 1040 | 0, 6, 3, slotrank, |
| 1041 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1042 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1043 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1044 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1045 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1046 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1047 | } |
| 1048 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1049 | static int does_lane_work(ramctr_timing *ctrl, int channel, int slotrank, int lane) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1050 | { |
| 1051 | u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1052 | |
| 1053 | return (MCHBAR32(lane_base[lane] + |
| 1054 | GDCRTRAININGRESULT(channel, (timA / 32) & 1)) >> (timA % 32)) & 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1055 | } |
| 1056 | |
| 1057 | struct run { |
| 1058 | int middle; |
| 1059 | int end; |
| 1060 | int start; |
| 1061 | int all; |
| 1062 | int length; |
| 1063 | }; |
| 1064 | |
| 1065 | static struct run get_longest_zero_run(int *seq, int sz) |
| 1066 | { |
| 1067 | int i, ls; |
| 1068 | int bl = 0, bs = 0; |
| 1069 | struct run ret; |
| 1070 | |
| 1071 | ls = 0; |
| 1072 | for (i = 0; i < 2 * sz; i++) |
| 1073 | if (seq[i % sz]) { |
| 1074 | if (i - ls > bl) { |
| 1075 | bl = i - ls; |
| 1076 | bs = ls; |
| 1077 | } |
| 1078 | ls = i + 1; |
| 1079 | } |
| 1080 | if (bl == 0) { |
| 1081 | ret.middle = sz / 2; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1082 | ret.start = 0; |
| 1083 | ret.end = sz; |
Jacob Garber | e0c181d | 2019-04-08 22:21:43 -0600 | [diff] [blame] | 1084 | ret.length = sz; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1085 | ret.all = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1086 | return ret; |
| 1087 | } |
| 1088 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1089 | ret.start = bs % sz; |
| 1090 | ret.end = (bs + bl - 1) % sz; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1091 | ret.middle = (bs + (bl - 1) / 2) % sz; |
| 1092 | ret.length = bl; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1093 | ret.all = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1094 | |
| 1095 | return ret; |
| 1096 | } |
| 1097 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1098 | static void discover_timA_coarse(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1099 | { |
| 1100 | int timA; |
| 1101 | int statistics[NUM_LANES][128]; |
| 1102 | int lane; |
| 1103 | |
| 1104 | for (timA = 0; timA < 128; timA++) { |
| 1105 | FOR_ALL_LANES { |
| 1106 | ctrl->timings[channel][slotrank].lanes[lane].timA = timA; |
| 1107 | } |
| 1108 | program_timings(ctrl, channel); |
| 1109 | |
| 1110 | test_timA(ctrl, channel, slotrank); |
| 1111 | |
| 1112 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1113 | statistics[lane][timA] = !does_lane_work(ctrl, channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1114 | } |
| 1115 | } |
| 1116 | FOR_ALL_LANES { |
| 1117 | struct run rn = get_longest_zero_run(statistics[lane], 128); |
| 1118 | ctrl->timings[channel][slotrank].lanes[lane].timA = rn.middle; |
| 1119 | upperA[lane] = rn.end; |
| 1120 | if (upperA[lane] < rn.middle) |
| 1121 | upperA[lane] += 128; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1122 | |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1123 | printram("timA: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1124 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1125 | } |
| 1126 | } |
| 1127 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1128 | static void discover_timA_fine(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1129 | { |
| 1130 | int timA_delta; |
| 1131 | int statistics[NUM_LANES][51]; |
| 1132 | int lane, i; |
| 1133 | |
| 1134 | memset(statistics, 0, sizeof(statistics)); |
| 1135 | |
| 1136 | for (timA_delta = -25; timA_delta <= 25; timA_delta++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1137 | |
| 1138 | FOR_ALL_LANES { |
| 1139 | ctrl->timings[channel][slotrank].lanes[lane].timA |
| 1140 | = upperA[lane] + timA_delta + 0x40; |
| 1141 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1142 | program_timings(ctrl, channel); |
| 1143 | |
| 1144 | for (i = 0; i < 100; i++) { |
| 1145 | test_timA(ctrl, channel, slotrank); |
| 1146 | FOR_ALL_LANES { |
| 1147 | statistics[lane][timA_delta + 25] += |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1148 | does_lane_work(ctrl, channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1149 | } |
| 1150 | } |
| 1151 | } |
| 1152 | FOR_ALL_LANES { |
| 1153 | int last_zero, first_all; |
| 1154 | |
| 1155 | for (last_zero = -25; last_zero <= 25; last_zero++) |
| 1156 | if (statistics[lane][last_zero + 25]) |
| 1157 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1158 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1159 | last_zero--; |
| 1160 | for (first_all = -25; first_all <= 25; first_all++) |
| 1161 | if (statistics[lane][first_all + 25] == 100) |
| 1162 | break; |
| 1163 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1164 | printram("lane %d: %d, %d\n", lane, last_zero, first_all); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1165 | |
| 1166 | ctrl->timings[channel][slotrank].lanes[lane].timA = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1167 | (last_zero + first_all) / 2 + upperA[lane]; |
| 1168 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1169 | printram("Aval: %d, %d, %d: %x\n", channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1170 | lane, ctrl->timings[channel][slotrank].lanes[lane].timA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1171 | } |
| 1172 | } |
| 1173 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1174 | static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1175 | { |
| 1176 | int works[NUM_LANES]; |
| 1177 | int lane; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1178 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1179 | while (1) { |
| 1180 | int all_works = 1, some_works = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1181 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1182 | program_timings(ctrl, channel); |
| 1183 | test_timA(ctrl, channel, slotrank); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1184 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1185 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1186 | works[lane] = !does_lane_work(ctrl, channel, slotrank, lane); |
| 1187 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1188 | if (works[lane]) |
| 1189 | some_works = 1; |
| 1190 | else |
| 1191 | all_works = 0; |
| 1192 | } |
| 1193 | if (all_works) |
| 1194 | return 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1195 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1196 | if (!some_works) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1197 | if (ctrl->timings[channel][slotrank].roundtrip_latency < 2) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1198 | printk(BIOS_EMERG, "402x discovery failed (1): %d, %d\n", |
| 1199 | channel, slotrank); |
| 1200 | return MAKE_ERR; |
| 1201 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1202 | ctrl->timings[channel][slotrank].roundtrip_latency -= 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1203 | printram("4024 -= 2;\n"); |
| 1204 | continue; |
| 1205 | } |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1206 | ctrl->timings[channel][slotrank].io_latency += 2; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1207 | printram("4028 += 2;\n"); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1208 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1209 | if (ctrl->timings[channel][slotrank].io_latency >= 0x10) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1210 | printk(BIOS_EMERG, "402x discovery failed (2): %d, %d\n", |
| 1211 | channel, slotrank); |
| 1212 | return MAKE_ERR; |
| 1213 | } |
| 1214 | FOR_ALL_LANES if (works[lane]) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1215 | ctrl->timings[channel][slotrank].lanes[lane].timA += 128; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1216 | upperA[lane] += 128; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1217 | printram("increment %d, %d, %d\n", channel, slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1218 | } |
| 1219 | } |
| 1220 | return 0; |
| 1221 | } |
| 1222 | |
| 1223 | struct timA_minmax { |
| 1224 | int timA_min_high, timA_max_high; |
| 1225 | }; |
| 1226 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1227 | static void pre_timA_change(ramctr_timing *ctrl, int channel, int slotrank, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1228 | struct timA_minmax *mnmx) |
| 1229 | { |
| 1230 | int lane; |
| 1231 | mnmx->timA_min_high = 7; |
| 1232 | mnmx->timA_max_high = 0; |
| 1233 | |
| 1234 | FOR_ALL_LANES { |
| 1235 | if (mnmx->timA_min_high > |
| 1236 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6)) |
| 1237 | mnmx->timA_min_high = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1238 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1239 | if (mnmx->timA_max_high < |
| 1240 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6)) |
| 1241 | mnmx->timA_max_high = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1242 | (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1243 | } |
| 1244 | } |
| 1245 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1246 | static void post_timA_change(ramctr_timing *ctrl, int channel, int slotrank, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1247 | struct timA_minmax *mnmx) |
| 1248 | { |
| 1249 | struct timA_minmax post; |
| 1250 | int shift_402x = 0; |
| 1251 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1252 | /* Get changed maxima */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1253 | pre_timA_change(ctrl, channel, slotrank, &post); |
| 1254 | |
| 1255 | if (mnmx->timA_max_high - mnmx->timA_min_high < |
| 1256 | post.timA_max_high - post.timA_min_high) |
| 1257 | shift_402x = +1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1258 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1259 | else if (mnmx->timA_max_high - mnmx->timA_min_high > |
| 1260 | post.timA_max_high - post.timA_min_high) |
| 1261 | shift_402x = -1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1262 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1263 | else |
| 1264 | shift_402x = 0; |
| 1265 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1266 | ctrl->timings[channel][slotrank].io_latency += shift_402x; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1267 | ctrl->timings[channel][slotrank].roundtrip_latency += shift_402x; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1268 | printram("4024 += %d;\n", shift_402x); |
| 1269 | printram("4028 += %d;\n", shift_402x); |
| 1270 | } |
| 1271 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1272 | /* |
| 1273 | * Compensate the skew between DQS and DQs. |
| 1274 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1275 | * To ease PCB design, a small skew between Data Strobe signals and Data Signals is allowed. |
| 1276 | * The controller has to measure and compensate this skew for every byte-lane. By delaying |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1277 | * either all DQ signals or DQS signal, a full phase shift can be introduced. It is assumed |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1278 | * that one byte-lane's DQs signals have the same routing delay. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1279 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1280 | * To measure the actual skew, the DRAM is placed in "read leveling" mode. In read leveling |
| 1281 | * mode the DRAM-chip outputs an alternating periodic pattern. The memory controller iterates |
| 1282 | * over all possible values to do a full phase shift and issues read commands. With DQS and |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1283 | * DQ in phase the data being read is expected to alternate on every byte: |
| 1284 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1285 | * 0xFF 0x00 0xFF ... |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1286 | * |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1287 | * Once the controller has detected this pattern a bit in the result register is set for the |
| 1288 | * current phase shift. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1289 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1290 | int read_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1291 | { |
| 1292 | int channel, slotrank, lane; |
| 1293 | int err; |
| 1294 | |
| 1295 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1296 | int all_high, some_high; |
| 1297 | int upperA[NUM_LANES]; |
| 1298 | struct timA_minmax mnmx; |
| 1299 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1300 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1301 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1302 | /* DRAM command PREA */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1303 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1304 | IOSAV_PRE | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1305 | 1, 3, ctrl->tRP, SSQ_NA, |
| 1306 | 1024, 6, 0, slotrank, |
| 1307 | ADDR_UPDATE_NONE); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1308 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1309 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1310 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1311 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1312 | MCHBAR32(GDCRTRAININGMOD) = (slotrank << 2) | 0x8001; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1313 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1314 | ctrl->timings[channel][slotrank].io_latency = 4; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1315 | ctrl->timings[channel][slotrank].roundtrip_latency = 55; |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1316 | program_timings(ctrl, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1317 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1318 | discover_timA_coarse(ctrl, channel, slotrank, upperA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1319 | |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1320 | all_high = 1; |
| 1321 | some_high = 0; |
| 1322 | FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1323 | if (ctrl->timings[channel][slotrank].lanes[lane].timA >= 0x40) |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1324 | some_high = 1; |
| 1325 | else |
| 1326 | all_high = 0; |
| 1327 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1328 | |
| 1329 | if (all_high) { |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1330 | ctrl->timings[channel][slotrank].io_latency--; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1331 | printram("4028--;\n"); |
| 1332 | FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1333 | ctrl->timings[channel][slotrank].lanes[lane].timA -= 0x40; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1334 | upperA[lane] -= 0x40; |
| 1335 | |
| 1336 | } |
| 1337 | } else if (some_high) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1338 | ctrl->timings[channel][slotrank].roundtrip_latency++; |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1339 | ctrl->timings[channel][slotrank].io_latency++; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1340 | printram("4024++;\n"); |
| 1341 | printram("4028++;\n"); |
| 1342 | } |
| 1343 | |
| 1344 | program_timings(ctrl, channel); |
| 1345 | |
| 1346 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1347 | |
| 1348 | err = discover_402x(ctrl, channel, slotrank, upperA); |
| 1349 | if (err) |
| 1350 | return err; |
| 1351 | |
| 1352 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1353 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1354 | |
| 1355 | discover_timA_fine(ctrl, channel, slotrank, upperA); |
| 1356 | |
| 1357 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1358 | pre_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1359 | |
| 1360 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1361 | ctrl->timings[channel][slotrank].lanes[lane].timA -= |
| 1362 | mnmx.timA_min_high * 0x40; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1363 | } |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1364 | ctrl->timings[channel][slotrank].io_latency -= mnmx.timA_min_high; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1365 | printram("4028 -= %d;\n", mnmx.timA_min_high); |
| 1366 | |
| 1367 | post_timA_change(ctrl, channel, slotrank, &mnmx); |
| 1368 | |
| 1369 | printram("4/8: %d, %d, %x, %x\n", channel, slotrank, |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1370 | ctrl->timings[channel][slotrank].roundtrip_latency, |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 1371 | ctrl->timings[channel][slotrank].io_latency); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1372 | |
| 1373 | printram("final results:\n"); |
| 1374 | FOR_ALL_LANES |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1375 | printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1376 | ctrl->timings[channel][slotrank].lanes[lane].timA); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1377 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1378 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1379 | |
| 1380 | toggle_io_reset(); |
| 1381 | } |
| 1382 | |
| 1383 | FOR_ALL_POPULATED_CHANNELS { |
| 1384 | program_timings(ctrl, channel); |
| 1385 | } |
| 1386 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1387 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1388 | } |
| 1389 | return 0; |
| 1390 | } |
| 1391 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1392 | static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1393 | { |
| 1394 | int lane; |
| 1395 | |
| 1396 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1397 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 1398 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1399 | } |
| 1400 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1401 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1402 | |
| 1403 | /* DRAM command ACT */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1404 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1405 | IOSAV_ACT | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1406 | 4, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->tRCD, SSQ_NA, |
| 1407 | 0, 6, 0, slotrank, |
| 1408 | ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1409 | |
| 1410 | /* DRAM command NOP */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1411 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1412 | IOSAV_NOP | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1413 | 1, 4, 4, SSQ_WR, |
| 1414 | 8, 0, 0, slotrank, |
| 1415 | ADDR_UPDATE_WRAP(31)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1416 | |
| 1417 | /* DRAM command WR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1418 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1419 | IOSAV_WR | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1420 | 500, 4, 4, SSQ_WR, |
| 1421 | 0, 0, 0, slotrank, |
| 1422 | ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1423 | |
| 1424 | /* DRAM command NOP */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1425 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1426 | IOSAV_NOP | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1427 | 1, 3, ctrl->CWL + ctrl->tWTR + 5, SSQ_WR, |
| 1428 | 8, 0, 0, slotrank, |
| 1429 | ADDR_UPDATE_WRAP(31)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1430 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1431 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1432 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1433 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1434 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1435 | |
| 1436 | /* DRAM command PREA */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1437 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1438 | IOSAV_PRE | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1439 | 1, 3, ctrl->tRP, SSQ_NA, |
| 1440 | 1024, 6, 0, slotrank, |
| 1441 | ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1442 | |
| 1443 | /* DRAM command ACT */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1444 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1445 | IOSAV_ACT | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1446 | 8, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->CAS, SSQ_NA, |
| 1447 | 0, 6, 0, slotrank, |
| 1448 | ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1449 | |
| 1450 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1451 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1452 | IOSAV_RD | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1453 | 500, 4, MAX(ctrl->tRTP, 8), SSQ_RD, |
| 1454 | 0, 0, 0, slotrank, |
| 1455 | ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1456 | |
| 1457 | /* DRAM command PREA */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1458 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1459 | IOSAV_PRE | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1460 | 1, 3, ctrl->tRP, SSQ_NA, |
| 1461 | 1024, 6, 0, slotrank, |
| 1462 | ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1463 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1464 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1465 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1466 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1467 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1468 | } |
| 1469 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1470 | static void timC_threshold_process(int *data, const int count) |
| 1471 | { |
| 1472 | int min = data[0]; |
| 1473 | int max = min; |
| 1474 | int i; |
| 1475 | for (i = 1; i < count; i++) { |
| 1476 | if (min > data[i]) |
| 1477 | min = data[i]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1478 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1479 | if (max < data[i]) |
| 1480 | max = data[i]; |
| 1481 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1482 | int threshold = min / 2 + max / 2; |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1483 | for (i = 0; i < count; i++) |
| 1484 | data[i] = data[i] > threshold; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1485 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1486 | printram("threshold=%d min=%d max=%d\n", threshold, min, max); |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1487 | } |
| 1488 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1489 | static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) |
| 1490 | { |
| 1491 | int timC; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1492 | int stats[NUM_LANES][MAX_TIMC + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1493 | int lane; |
| 1494 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1495 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1496 | |
| 1497 | /* DRAM command PREA */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1498 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1499 | IOSAV_PRE | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1500 | 1, 3, ctrl->tRP, SSQ_NA, |
| 1501 | 1024, 6, 0, slotrank, |
| 1502 | ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1503 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1504 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1505 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1506 | |
| 1507 | for (timC = 0; timC <= MAX_TIMC; timC++) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1508 | FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = timC; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1509 | program_timings(ctrl, channel); |
| 1510 | |
| 1511 | test_timC(ctrl, channel, slotrank); |
| 1512 | |
| 1513 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1514 | stats[lane][timC] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1515 | } |
| 1516 | } |
| 1517 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1518 | struct run rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1519 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1520 | if (rn.all || rn.length < 8) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1521 | printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", |
| 1522 | channel, slotrank, lane); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1523 | /* |
| 1524 | * With command training not being done yet, the lane can be erroneous. |
| 1525 | * Take the average as reference and try again to find a run. |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1526 | */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1527 | timC_threshold_process(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1528 | rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane])); |
| 1529 | |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1530 | if (rn.all || rn.length < 8) { |
| 1531 | printk(BIOS_EMERG, "timC recovery failed\n"); |
| 1532 | return MAKE_ERR; |
| 1533 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1534 | } |
Tobias Diedrich | 87c4f11 | 2017-12-07 22:40:20 +0100 | [diff] [blame] | 1535 | ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1536 | printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1537 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1538 | } |
| 1539 | return 0; |
| 1540 | } |
| 1541 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1542 | static int get_precedening_channels(ramctr_timing *ctrl, int target_channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1543 | { |
| 1544 | int channel, ret = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1545 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1546 | FOR_ALL_POPULATED_CHANNELS if (channel < target_channel) |
| 1547 | ret++; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1548 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1549 | return ret; |
| 1550 | } |
| 1551 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1552 | static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1553 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1554 | unsigned int j; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1555 | unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1556 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1557 | for (j = 0; j < 16; j++) |
| 1558 | write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1559 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1560 | sfence(); |
| 1561 | } |
| 1562 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1563 | static int num_of_channels(const ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1564 | { |
| 1565 | int ret = 0; |
| 1566 | int channel; |
| 1567 | FOR_ALL_POPULATED_CHANNELS ret++; |
| 1568 | return ret; |
| 1569 | } |
| 1570 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1571 | static void fill_pattern1(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1572 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1573 | unsigned int j; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1574 | unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 1575 | unsigned int channel_step = 0x40 * num_of_channels(ctrl); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1576 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1577 | for (j = 0; j < 16; j++) |
| 1578 | write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1579 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1580 | for (j = 0; j < 16; j++) |
| 1581 | write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1582 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1583 | sfence(); |
| 1584 | } |
| 1585 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1586 | static void precharge(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1587 | { |
| 1588 | int channel, slotrank, lane; |
| 1589 | |
| 1590 | FOR_ALL_POPULATED_CHANNELS { |
| 1591 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1592 | ctrl->timings[channel][slotrank].lanes[lane].falling = 16; |
| 1593 | ctrl->timings[channel][slotrank].lanes[lane].rising = 16; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1594 | } |
| 1595 | |
| 1596 | program_timings(ctrl, channel); |
| 1597 | |
| 1598 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1599 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1600 | |
| 1601 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1602 | write MR3 MPR enable |
| 1603 | in this mode only RD and RDA are allowed |
| 1604 | all reads return a predefined pattern */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1605 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1606 | IOSAV_MRS | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1607 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 1608 | 4, 6, 3, slotrank, |
| 1609 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1610 | |
| 1611 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1612 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1613 | IOSAV_RD | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1614 | 3, 4, 4, SSQ_RD, |
| 1615 | 0, 0, 0, slotrank, |
| 1616 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1617 | |
| 1618 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1619 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1620 | IOSAV_RD | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1621 | 1, 4, ctrl->CAS + 8, SSQ_NA, |
| 1622 | 0, 6, 0, slotrank, |
| 1623 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1624 | |
| 1625 | /* DRAM command MRS |
| 1626 | * write MR3 MPR disable */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1627 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1628 | IOSAV_MRS | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1629 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 1630 | 0, 6, 3, slotrank, |
| 1631 | ADDR_UPDATE_NONE); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1632 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1633 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1634 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1635 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1636 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1637 | } |
| 1638 | |
| 1639 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1640 | ctrl->timings[channel][slotrank].lanes[lane].falling = 48; |
| 1641 | ctrl->timings[channel][slotrank].lanes[lane].rising = 48; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1642 | } |
| 1643 | |
| 1644 | program_timings(ctrl, channel); |
| 1645 | |
| 1646 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1647 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1648 | /* DRAM command MRS |
| 1649 | * write MR3 MPR enable |
| 1650 | * in this mode only RD and RDA are allowed |
| 1651 | * all reads return a predefined pattern */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1652 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1653 | IOSAV_MRS | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1654 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 1655 | 4, 6, 3, slotrank, |
| 1656 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1657 | |
| 1658 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1659 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1660 | IOSAV_RD | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1661 | 3, 4, 4, SSQ_RD, |
| 1662 | 0, 0, 0, slotrank, |
| 1663 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1664 | |
| 1665 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1666 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1667 | IOSAV_RD | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1668 | 1, 4, ctrl->CAS + 8, SSQ_NA, |
| 1669 | 0, 6, 0, slotrank, |
| 1670 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1671 | |
| 1672 | /* DRAM command MRS |
| 1673 | * write MR3 MPR disable */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1674 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1675 | IOSAV_MRS | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1676 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 1677 | 0, 6, 3, slotrank, |
| 1678 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1679 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1680 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1681 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1682 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1683 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1684 | } |
| 1685 | } |
| 1686 | } |
| 1687 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1688 | static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1689 | { |
| 1690 | /* enable DQs on this slotrank */ |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1691 | write_mrreg(ctrl, channel, slotrank, 1, 0x80 | make_mr1(ctrl, slotrank, channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1692 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1693 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1694 | /* DRAM command NOP */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1695 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1696 | IOSAV_NOP | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1697 | 1, 3, ctrl->CWL + ctrl->tWLO, SSQ_WR, |
| 1698 | 8, 0, 0, slotrank, |
| 1699 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1700 | |
| 1701 | /* DRAM command NOP */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1702 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1703 | IOSAV_NOP_ALT | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1704 | 1, 3, ctrl->CAS + 38, SSQ_RD, |
| 1705 | 4, 0, 0, slotrank, |
| 1706 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1707 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1708 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1709 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(2); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1710 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1711 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1712 | |
| 1713 | /* disable DQs on this slotrank */ |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1714 | write_mrreg(ctrl, channel, slotrank, 1, 0x1080 | make_mr1(ctrl, slotrank, channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1715 | } |
| 1716 | |
| 1717 | static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) |
| 1718 | { |
| 1719 | int timB; |
| 1720 | int statistics[NUM_LANES][128]; |
| 1721 | int lane; |
| 1722 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1723 | MCHBAR32(GDCRTRAININGMOD) = 0x108052 | (slotrank << 2); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1724 | |
| 1725 | for (timB = 0; timB < 128; timB++) { |
| 1726 | FOR_ALL_LANES { |
| 1727 | ctrl->timings[channel][slotrank].lanes[lane].timB = timB; |
| 1728 | } |
| 1729 | program_timings(ctrl, channel); |
| 1730 | |
| 1731 | test_timB(ctrl, channel, slotrank); |
| 1732 | |
| 1733 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1734 | statistics[lane][timB] = !((MCHBAR32(lane_base[lane] + |
| 1735 | GDCRTRAININGRESULT(channel, (timB / 32) & 1)) >> |
| 1736 | (timB % 32)) & 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1737 | } |
| 1738 | } |
| 1739 | FOR_ALL_LANES { |
| 1740 | struct run rn = get_longest_zero_run(statistics[lane], 128); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1741 | /* |
| 1742 | * timC is a direct function of timB's 6 LSBs. Some tests increments the value |
| 1743 | * of timB by a small value, which might cause the 6-bit value to overflow if |
| 1744 | * it's close to 0x3f. Increment the value by a small offset if it's likely |
| 1745 | * to overflow, to make sure it won't overflow while running tests and bricks |
| 1746 | * the system due to a non matching timC. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1747 | * |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1748 | * TODO: find out why some tests (edge write discovery) increment timB. |
| 1749 | */ |
| 1750 | if ((rn.start & 0x3f) == 0x3e) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1751 | rn.start += 2; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1752 | else if ((rn.start & 0x3f) == 0x3f) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1753 | rn.start += 1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1754 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1755 | ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start; |
| 1756 | if (rn.all) { |
| 1757 | printk(BIOS_EMERG, "timB discovery failed: %d, %d, %d\n", |
| 1758 | channel, slotrank, lane); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1759 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1760 | return MAKE_ERR; |
| 1761 | } |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 1762 | printram("timB: %d, %d, %d: 0x%02x-0x%02x-0x%02x\n", |
| 1763 | channel, slotrank, lane, rn.start, rn.middle, rn.end); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1764 | } |
| 1765 | return 0; |
| 1766 | } |
| 1767 | |
| 1768 | static int get_timB_high_adjust(u64 val) |
| 1769 | { |
| 1770 | int i; |
| 1771 | |
| 1772 | /* good */ |
| 1773 | if (val == 0xffffffffffffffffLL) |
| 1774 | return 0; |
| 1775 | |
| 1776 | if (val >= 0xf000000000000000LL) { |
| 1777 | /* needs negative adjustment */ |
| 1778 | for (i = 0; i < 8; i++) |
| 1779 | if (val << (8 * (7 - i) + 4)) |
| 1780 | return -i; |
| 1781 | } else { |
| 1782 | /* needs positive adjustment */ |
| 1783 | for (i = 0; i < 8; i++) |
| 1784 | if (val >> (8 * (7 - i) + 4)) |
| 1785 | return i; |
| 1786 | } |
| 1787 | return 8; |
| 1788 | } |
| 1789 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1790 | static void adjust_high_timB(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1791 | { |
| 1792 | int channel, slotrank, lane, old; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1793 | MCHBAR32(GDCRTRAININGMOD) = 0x200; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1794 | FOR_ALL_POPULATED_CHANNELS { |
| 1795 | fill_pattern1(ctrl, channel); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1796 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1797 | } |
| 1798 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1799 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1800 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x10001; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1801 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1802 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1803 | |
| 1804 | /* DRAM command ACT */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1805 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1806 | IOSAV_ACT | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1807 | 1, 3, ctrl->tRCD, SSQ_NA, |
| 1808 | 0, 6, 0, slotrank, |
| 1809 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1810 | |
| 1811 | /* DRAM command NOP */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1812 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1813 | IOSAV_NOP | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1814 | 1, 3, 4, SSQ_WR, |
| 1815 | 8, 0, 0, slotrank, |
| 1816 | ADDR_UPDATE_WRAP(31)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1817 | |
| 1818 | /* DRAM command WR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1819 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1820 | IOSAV_WR | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1821 | 3, 4, 4, SSQ_WR, |
| 1822 | 0, 0, 0, slotrank, |
| 1823 | ADDR_UPDATE(0, 1, 0, 0, 31, 0, 0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1824 | |
| 1825 | /* DRAM command NOP */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1826 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1827 | IOSAV_NOP | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1828 | 1, 3, ctrl->CWL + ctrl->tWTR + 5, SSQ_WR, |
| 1829 | 8, 0, 0, slotrank, |
| 1830 | ADDR_UPDATE_WRAP(31)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1831 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1832 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1833 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1834 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1835 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1836 | |
| 1837 | /* DRAM command PREA */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1838 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1839 | IOSAV_PRE | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1840 | 1, 3, ctrl->tRP, SSQ_NA, |
| 1841 | 1024, 6, 0, slotrank, |
| 1842 | ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1843 | |
| 1844 | /* DRAM command ACT */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1845 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 1846 | IOSAV_ACT | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1847 | 1, 3, ctrl->tRCD, SSQ_NA, |
| 1848 | 0, 6, 0, slotrank, |
| 1849 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1850 | |
| 1851 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1852 | IOSAV_SUBSEQUENCE(channel, 2, |
| 1853 | IOSAV_RD | (3 << 16), |
| 1854 | 1, 3, ctrl->tRP + |
| 1855 | ctrl->timings[channel][slotrank].roundtrip_latency + |
| 1856 | ctrl->timings[channel][slotrank].io_latency, SSQ_RD, |
| 1857 | 8, 6, 0, slotrank, |
| 1858 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1859 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1860 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1861 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1862 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1863 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1864 | FOR_ALL_LANES { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1865 | u64 res = MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT1(channel)); |
Felix Held | 283b4466 | 2020-01-14 21:14:42 +0100 | [diff] [blame] | 1866 | res |= ((u64) MCHBAR32(lane_base[lane] + |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 1867 | GDCRTRAININGRESULT2(channel))) << 32; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1868 | old = ctrl->timings[channel][slotrank].lanes[lane].timB; |
| 1869 | ctrl->timings[channel][slotrank].lanes[lane].timB += |
| 1870 | get_timB_high_adjust(res) * 64; |
| 1871 | |
| 1872 | printram("High adjust %d:%016llx\n", lane, res); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 1873 | printram("Bval+: %d, %d, %d, %x -> %x\n", channel, slotrank, lane, |
| 1874 | old, ctrl->timings[channel][slotrank].lanes[lane].timB); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1875 | } |
| 1876 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1877 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1878 | } |
| 1879 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1880 | static void write_op(ramctr_timing *ctrl, int channel) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1881 | { |
| 1882 | int slotrank; |
| 1883 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1884 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1885 | |
| 1886 | /* choose an existing rank. */ |
| 1887 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 1888 | |
Angel Pons | 69e1714 | 2020-03-23 12:26:29 +0100 | [diff] [blame] | 1889 | /* DRAM command ZQCS */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1890 | IOSAV_SUBSEQUENCE(channel, 0, |
| 1891 | IOSAV_ZQCS & NO_RANKSEL, |
| 1892 | 1, 4, 4, SSQ_NA, |
| 1893 | 0, 6, 0, slotrank, |
| 1894 | ADDR_UPDATE_WRAP(31)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1895 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1896 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1897 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1898 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1899 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1900 | } |
| 1901 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1902 | /* |
| 1903 | * Compensate the skew between CMD/ADDR/CLK and DQ/DQS lanes. |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1904 | * |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1905 | * Since DDR3 uses a fly-by topology, the data and strobes signals reach the chips at different |
| 1906 | * times with respect to command, address and clock signals. By delaying either all DQ/DQS or |
| 1907 | * all CMD/ADDR/CLK signals, a full phase shift can be introduced. It is assumed that the |
| 1908 | * CLK/ADDR/CMD signals have the same routing delay. |
| 1909 | * |
| 1910 | * To find the required phase shift the DRAM is placed in "write leveling" mode. In this mode, |
| 1911 | * the DRAM-chip samples the CLK on every DQS edge and feeds back the sampled value on the data |
| 1912 | * lanes (DQ). |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1913 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1914 | int write_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1915 | { |
| 1916 | int channel, slotrank, lane; |
| 1917 | int err; |
| 1918 | |
| 1919 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1920 | MCHBAR32_OR(TC_RWP_ch(channel), 0x8000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1921 | |
| 1922 | FOR_ALL_POPULATED_CHANNELS { |
| 1923 | write_op(ctrl, channel); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1924 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1925 | } |
| 1926 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1927 | /* Refresh disable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1928 | MCHBAR32_AND(MC_INIT_STATE_G, ~8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1929 | FOR_ALL_POPULATED_CHANNELS { |
| 1930 | write_op(ctrl, channel); |
| 1931 | } |
| 1932 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1933 | /* Enable write leveling on all ranks |
| 1934 | Disable all DQ outputs |
| 1935 | Only NOP is allowed in this mode */ |
| 1936 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS |
| 1937 | write_mrreg(ctrl, channel, slotrank, 1, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 1938 | make_mr1(ctrl, slotrank, channel) | 0x1080); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1939 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1940 | MCHBAR32(GDCRTRAININGMOD) = 0x108052; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1941 | |
| 1942 | toggle_io_reset(); |
| 1943 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1944 | /* Set any valid value for timB, it gets corrected later */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1945 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1946 | err = discover_timB(ctrl, channel, slotrank); |
| 1947 | if (err) |
| 1948 | return err; |
| 1949 | } |
| 1950 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1951 | /* Disable write leveling on all ranks */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1952 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1953 | write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1954 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1955 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1956 | |
| 1957 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1958 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1959 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1960 | /* Refresh enable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1961 | MCHBAR32_OR(MC_INIT_STATE_G, 8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1962 | |
| 1963 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1964 | MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x00200000); |
| 1965 | MCHBAR32(IOSAV_STATUS_ch(channel)); |
| 1966 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1967 | |
| 1968 | /* DRAM command ZQCS */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 1969 | IOSAV_SUBSEQUENCE(channel, 0, |
| 1970 | IOSAV_ZQCS & NO_RANKSEL, |
| 1971 | 1, 36, 101, SSQ_NA, |
| 1972 | 0, 6, 0, 0, |
| 1973 | ADDR_UPDATE_WRAP(31)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1974 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 1975 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1976 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 1977 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1978 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1979 | } |
| 1980 | |
| 1981 | toggle_io_reset(); |
| 1982 | |
| 1983 | printram("CPE\n"); |
| 1984 | precharge(ctrl); |
| 1985 | printram("CPF\n"); |
| 1986 | |
| 1987 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1988 | MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1989 | } |
| 1990 | |
| 1991 | FOR_ALL_POPULATED_CHANNELS { |
| 1992 | fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 1993 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 1994 | } |
| 1995 | |
| 1996 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 1997 | err = discover_timC(ctrl, channel, slotrank); |
| 1998 | if (err) |
| 1999 | return err; |
| 2000 | } |
| 2001 | |
| 2002 | FOR_ALL_POPULATED_CHANNELS |
| 2003 | program_timings(ctrl, channel); |
| 2004 | |
| 2005 | /* measure and adjust timB timings */ |
| 2006 | adjust_high_timB(ctrl); |
| 2007 | |
| 2008 | FOR_ALL_POPULATED_CHANNELS |
| 2009 | program_timings(ctrl, channel); |
| 2010 | |
| 2011 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2012 | MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2013 | } |
| 2014 | return 0; |
| 2015 | } |
| 2016 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2017 | static int test_320c(ramctr_timing *ctrl, int channel, int slotrank) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2018 | { |
| 2019 | struct ram_rank_timings saved_rt = ctrl->timings[channel][slotrank]; |
| 2020 | int timC_delta; |
| 2021 | int lanes_ok = 0; |
| 2022 | int ctr = 0; |
| 2023 | int lane; |
| 2024 | |
| 2025 | for (timC_delta = -5; timC_delta <= 5; timC_delta++) { |
| 2026 | FOR_ALL_LANES { |
| 2027 | ctrl->timings[channel][slotrank].lanes[lane].timC = |
| 2028 | saved_rt.lanes[lane].timC + timC_delta; |
| 2029 | } |
| 2030 | program_timings(ctrl, channel); |
| 2031 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2032 | MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2033 | } |
| 2034 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2035 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2036 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2037 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2038 | /* DRAM command ACT */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2039 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2040 | IOSAV_ACT | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2041 | 8, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->tRCD, SSQ_NA, |
| 2042 | ctr, 6, 0, slotrank, |
| 2043 | ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); |
Felix Held | 9fe248f | 2018-07-31 20:59:45 +0200 | [diff] [blame] | 2044 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2045 | /* DRAM command WR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2046 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2047 | IOSAV_WR | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2048 | 32, 4, ctrl->CWL + ctrl->tWTR + 8, SSQ_WR, |
| 2049 | 0, 0, 0, slotrank, |
| 2050 | ADDR_UPDATE(0, 1, 0, 0, 18, 3, 0, 2)); |
| 2051 | |
Angel Pons | c36cd07 | 2020-05-02 16:51:39 +0200 | [diff] [blame] | 2052 | MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 1)) = 0x389abcd; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2053 | |
| 2054 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2055 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2056 | IOSAV_RD | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2057 | 32, 4, MAX(ctrl->tRTP, 8), SSQ_RD, |
| 2058 | 0, 0, 0, slotrank, |
| 2059 | ADDR_UPDATE(0, 1, 0, 0, 18, 3, 0, 2)); |
| 2060 | |
Angel Pons | c36cd07 | 2020-05-02 16:51:39 +0200 | [diff] [blame] | 2061 | MCHBAR32(IOSAV_n_ADDRESS_LFSR_ch(channel, 2)) = 0x389abcd; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2062 | |
| 2063 | /* DRAM command PRE */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2064 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2065 | IOSAV_PRE | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2066 | 1, 4, 15, SSQ_NA, |
| 2067 | 1024, 6, 0, slotrank, |
| 2068 | ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2069 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2070 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2071 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2072 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2073 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2074 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2075 | u32 r32 = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2076 | |
| 2077 | if (r32 == 0) |
| 2078 | lanes_ok |= 1 << lane; |
| 2079 | } |
| 2080 | ctr++; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2081 | if (lanes_ok == ((1 << ctrl->lanes) - 1)) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2082 | break; |
| 2083 | } |
| 2084 | |
| 2085 | ctrl->timings[channel][slotrank] = saved_rt; |
| 2086 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2087 | return lanes_ok != ((1 << ctrl->lanes) - 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2088 | } |
| 2089 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2090 | static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2091 | { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 2092 | unsigned int i, j; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2093 | unsigned int offset = get_precedening_channels(ctrl, channel) * 0x40; |
| 2094 | unsigned int step = 0x40 * num_of_channels(ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2095 | |
| 2096 | if (patno) { |
| 2097 | u8 base8 = 0x80 >> ((patno - 1) % 8); |
| 2098 | u32 base = base8 | (base8 << 8) | (base8 << 16) | (base8 << 24); |
| 2099 | for (i = 0; i < 32; i++) { |
| 2100 | for (j = 0; j < 16; j++) { |
| 2101 | u32 val = use_base[patno - 1][i] & (1 << (j / 2)) ? base : 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2102 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2103 | if (invert[patno - 1][i] & (1 << (j / 2))) |
| 2104 | val = ~val; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2105 | |
| 2106 | write32((void *)((1 << 26) + offset + i * step + j * 4), val); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2107 | } |
| 2108 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2109 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2110 | for (i = 0; i < ARRAY_SIZE(pattern); i++) { |
| 2111 | for (j = 0; j < 16; j++) { |
| 2112 | const u32 val = pattern[i][j]; |
| 2113 | write32((void *)((1 << 26) + offset + i * step + j * 4), val); |
| 2114 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2115 | } |
| 2116 | sfence(); |
| 2117 | } |
| 2118 | } |
| 2119 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2120 | static void reprogram_320c(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2121 | { |
| 2122 | int channel, slotrank; |
| 2123 | |
| 2124 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2125 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2126 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2127 | /* Choose an existing rank */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2128 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 2129 | |
| 2130 | /* DRAM command ZQCS */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2131 | IOSAV_SUBSEQUENCE(channel, 0, |
| 2132 | IOSAV_ZQCS & NO_RANKSEL, |
| 2133 | 1, 4, 4, SSQ_NA, |
| 2134 | 0, 6, 0, slotrank, |
| 2135 | ADDR_UPDATE_WRAP(31)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2136 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2137 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2138 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2139 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2140 | wait_for_iosav(channel); |
| 2141 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2142 | } |
| 2143 | |
| 2144 | /* refresh disable */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2145 | MCHBAR32_AND(MC_INIT_STATE_G, ~8); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2146 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2147 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2148 | |
| 2149 | /* choose an existing rank. */ |
| 2150 | slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; |
| 2151 | |
| 2152 | /* DRAM command ZQCS */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2153 | IOSAV_SUBSEQUENCE(channel, 0, |
| 2154 | IOSAV_ZQCS & NO_RANKSEL, |
| 2155 | 1, 4, 4, SSQ_NA, |
| 2156 | 0, 6, 0, slotrank, |
| 2157 | ADDR_UPDATE_WRAP(31)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2158 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2159 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2160 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2161 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2162 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2163 | } |
| 2164 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2165 | /* JEDEC reset */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2166 | dram_jedecreset(ctrl); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2167 | |
| 2168 | /* MRS commands */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2169 | dram_mrscommands(ctrl); |
| 2170 | |
| 2171 | toggle_io_reset(); |
| 2172 | } |
| 2173 | |
| 2174 | #define MIN_C320C_LEN 13 |
| 2175 | |
| 2176 | static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) |
| 2177 | { |
| 2178 | struct ram_rank_timings saved_timings[NUM_CHANNELS][NUM_SLOTRANKS]; |
| 2179 | int slotrank; |
| 2180 | int c320c; |
| 2181 | int stat[NUM_SLOTRANKS][256]; |
| 2182 | int delta = 0; |
| 2183 | |
| 2184 | printram("Trying cmd_stretch %d on channel %d\n", cmd_stretch, channel); |
| 2185 | |
| 2186 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2187 | saved_timings[channel][slotrank] = ctrl->timings[channel][slotrank]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2188 | } |
| 2189 | |
| 2190 | ctrl->cmd_stretch[channel] = cmd_stretch; |
| 2191 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2192 | MCHBAR32(TC_RAP_ch(channel)) = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2193 | (ctrl->tRRD << 0) |
| 2194 | | (ctrl->tRTP << 4) |
| 2195 | | (ctrl->tCKE << 8) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2196 | | (ctrl->tWTR << 12) |
| 2197 | | (ctrl->tFAW << 16) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2198 | | (ctrl->tWR << 24) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2199 | | (ctrl->cmd_stretch[channel] << 30); |
| 2200 | |
| 2201 | if (ctrl->cmd_stretch[channel] == 2) |
| 2202 | delta = 2; |
| 2203 | else if (ctrl->cmd_stretch[channel] == 0) |
| 2204 | delta = 4; |
| 2205 | |
| 2206 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2207 | ctrl->timings[channel][slotrank].roundtrip_latency -= delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2208 | } |
| 2209 | |
| 2210 | for (c320c = -127; c320c <= 127; c320c++) { |
| 2211 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2212 | ctrl->timings[channel][slotrank].pi_coding = c320c; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2213 | } |
| 2214 | program_timings(ctrl, channel); |
| 2215 | reprogram_320c(ctrl); |
| 2216 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2217 | stat[slotrank][c320c + 127] = test_320c(ctrl, channel, slotrank); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2218 | } |
| 2219 | } |
| 2220 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2221 | struct run rn = get_longest_zero_run(stat[slotrank], 255); |
| 2222 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2223 | ctrl->timings[channel][slotrank].pi_coding = rn.middle - 127; |
Patrick Rudolph | 368b615 | 2016-11-25 16:36:52 +0100 | [diff] [blame] | 2224 | printram("cmd_stretch: %d, %d: 0x%02x-0x%02x-0x%02x\n", |
| 2225 | channel, slotrank, rn.start, rn.middle, rn.end); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2226 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2227 | if (rn.all || rn.length < MIN_C320C_LEN) { |
| 2228 | FOR_ALL_POPULATED_RANKS { |
| 2229 | ctrl->timings[channel][slotrank] = |
| 2230 | saved_timings[channel][slotrank]; |
| 2231 | } |
| 2232 | return MAKE_ERR; |
| 2233 | } |
| 2234 | } |
| 2235 | |
| 2236 | return 0; |
| 2237 | } |
| 2238 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2239 | /* |
| 2240 | * Adjust CMD phase shift and try multiple command rates. |
| 2241 | * A command rate of 2T doubles the time needed for address and command decode. |
| 2242 | */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2243 | int command_training(ramctr_timing *ctrl) |
| 2244 | { |
| 2245 | int channel; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2246 | |
| 2247 | FOR_ALL_POPULATED_CHANNELS { |
| 2248 | fill_pattern5(ctrl, channel, 0); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2249 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2250 | } |
| 2251 | |
| 2252 | FOR_ALL_POPULATED_CHANNELS { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2253 | int cmdrate, err; |
| 2254 | |
| 2255 | /* |
| 2256 | * Dual DIMM per channel: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2257 | * Issue: |
| 2258 | * While c320c discovery seems to succeed raminit will fail in write training. |
| 2259 | * |
| 2260 | * Workaround: |
| 2261 | * Skip 1T in dual DIMM mode, that's only supported by a few DIMMs. |
| 2262 | * Only try 1T mode for XMP DIMMs that request it in dual DIMM mode. |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2263 | * |
| 2264 | * Single DIMM per channel: |
| 2265 | * Try command rate 1T and 2T |
| 2266 | */ |
| 2267 | cmdrate = ((ctrl->rankmap[channel] & 0x5) == 0x5); |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 2268 | if (ctrl->tCMD) |
| 2269 | /* XMP gives the CMD rate in clock ticks, not ns */ |
| 2270 | cmdrate = MIN(DIV_ROUND_UP(ctrl->tCMD, 256) - 1, 1); |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2271 | |
Elyes HAOUAS | adda3f81 | 2018-01-31 23:02:35 +0100 | [diff] [blame] | 2272 | for (; cmdrate < 2; cmdrate++) { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2273 | err = try_cmd_stretch(ctrl, channel, cmdrate << 1); |
| 2274 | |
| 2275 | if (!err) |
| 2276 | break; |
| 2277 | } |
| 2278 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2279 | if (err) { |
Patrick Rudolph | 58d16af | 2017-06-19 19:33:12 +0200 | [diff] [blame] | 2280 | printk(BIOS_EMERG, "c320c discovery failed\n"); |
| 2281 | return err; |
| 2282 | } |
| 2283 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2284 | printram("Using CMD rate %uT on channel %u\n", cmdrate + 1, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2285 | } |
| 2286 | |
| 2287 | FOR_ALL_POPULATED_CHANNELS |
| 2288 | program_timings(ctrl, channel); |
| 2289 | |
| 2290 | reprogram_320c(ctrl); |
| 2291 | return 0; |
| 2292 | } |
| 2293 | |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2294 | static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2295 | { |
| 2296 | int edge; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2297 | int stats[NUM_LANES][MAX_EDGE_TIMING + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2298 | int lane; |
| 2299 | |
| 2300 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { |
| 2301 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2302 | ctrl->timings[channel][slotrank].lanes[lane].rising = edge; |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2303 | ctrl->timings[channel][slotrank].lanes[lane].falling = edge; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2304 | } |
| 2305 | program_timings(ctrl, channel); |
| 2306 | |
| 2307 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2308 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 2309 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2310 | } |
| 2311 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2312 | wait_for_iosav(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2313 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2314 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2315 | write MR3 MPR enable |
| 2316 | in this mode only RD and RDA are allowed |
| 2317 | all reads return a predefined pattern */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2318 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2319 | IOSAV_MRS | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2320 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 2321 | 4, 6, 3, slotrank, |
| 2322 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2323 | |
| 2324 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2325 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2326 | IOSAV_RD | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2327 | 500, 4, 4, SSQ_RD, |
| 2328 | 0, 0, 0, slotrank, |
| 2329 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2330 | |
| 2331 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2332 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2333 | IOSAV_RD | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2334 | 1, 4, ctrl->CAS + 8, SSQ_NA, |
| 2335 | 0, 6, 0, slotrank, |
| 2336 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2337 | |
| 2338 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2339 | MR3 disable MPR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2340 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2341 | IOSAV_MRS | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2342 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 2343 | 0, 6, 3, slotrank, |
| 2344 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2345 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2346 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2347 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2348 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2349 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2350 | |
| 2351 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2352 | stats[lane][edge] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2353 | } |
| 2354 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2355 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2356 | FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2357 | struct run rn = get_longest_zero_run(stats[lane], MAX_EDGE_TIMING + 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2358 | edges[lane] = rn.middle; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2359 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2360 | if (rn.all) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2361 | printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", channel, |
| 2362 | slotrank, lane); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2363 | return MAKE_ERR; |
| 2364 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2365 | printram("eval %d, %d, %d: %02x\n", channel, slotrank, lane, edges[lane]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2366 | } |
| 2367 | return 0; |
| 2368 | } |
| 2369 | |
| 2370 | int discover_edges(ramctr_timing *ctrl) |
| 2371 | { |
| 2372 | int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2373 | int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2374 | int channel, slotrank, lane; |
| 2375 | int err; |
| 2376 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2377 | MCHBAR32(GDCRTRAININGMOD) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2378 | |
| 2379 | toggle_io_reset(); |
| 2380 | |
| 2381 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2382 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2383 | } |
| 2384 | |
| 2385 | FOR_ALL_POPULATED_CHANNELS { |
| 2386 | fill_pattern0(ctrl, channel, 0, 0); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2387 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2388 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2389 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2390 | } |
| 2391 | |
| 2392 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2393 | ctrl->timings[channel][slotrank].lanes[lane].falling = 16; |
| 2394 | ctrl->timings[channel][slotrank].lanes[lane].rising = 16; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2395 | } |
| 2396 | |
| 2397 | program_timings(ctrl, channel); |
| 2398 | |
| 2399 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2400 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2401 | |
| 2402 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2403 | MR3 enable MPR |
| 2404 | write MR3 MPR enable |
| 2405 | in this mode only RD and RDA are allowed |
| 2406 | all reads return a predefined pattern */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2407 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2408 | IOSAV_MRS | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2409 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 2410 | 4, 6, 3, slotrank, |
| 2411 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2412 | |
| 2413 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2414 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2415 | IOSAV_RD | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2416 | 3, 4, 4, SSQ_RD, |
| 2417 | 0, 0, 0, slotrank, |
| 2418 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2419 | |
| 2420 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2421 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2422 | IOSAV_RD | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2423 | 1, 4, ctrl->CAS + 8, SSQ_NA, |
| 2424 | 0, 6, 0, slotrank, |
| 2425 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2426 | |
| 2427 | /* DRAM command MRS |
| 2428 | * MR3 disable MPR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2429 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2430 | IOSAV_MRS | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2431 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 2432 | 0, 6, 3, slotrank, |
| 2433 | ADDR_UPDATE_NONE); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2434 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2435 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2436 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2437 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2438 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2439 | } |
| 2440 | |
| 2441 | /* XXX: check any measured value ? */ |
| 2442 | |
| 2443 | FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2444 | ctrl->timings[channel][slotrank].lanes[lane].falling = 48; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2445 | ctrl->timings[channel][slotrank].lanes[lane].rising = 48; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2446 | } |
| 2447 | |
| 2448 | program_timings(ctrl, channel); |
| 2449 | |
| 2450 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2451 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2452 | |
| 2453 | /* DRAM command MRS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2454 | MR3 enable MPR |
| 2455 | write MR3 MPR enable |
| 2456 | in this mode only RD and RDA are allowed |
| 2457 | all reads return a predefined pattern */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2458 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2459 | IOSAV_MRS | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2460 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 2461 | 4, 6, 3, slotrank, |
| 2462 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2463 | |
| 2464 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2465 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2466 | IOSAV_RD | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2467 | 3, 4, 4, SSQ_RD, |
| 2468 | 0, 0, 0, slotrank, |
| 2469 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2470 | |
| 2471 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2472 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2473 | IOSAV_RD | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2474 | 1, 4, ctrl->CAS + 8, SSQ_NA, |
| 2475 | 0, 6, 0, slotrank, |
| 2476 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2477 | |
| 2478 | /* DRAM command MRS |
| 2479 | * MR3 disable MPR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2480 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2481 | IOSAV_MRS | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2482 | 1, 3, ctrl->tMOD, SSQ_NA, |
| 2483 | 0, 6, 3, slotrank, |
| 2484 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2485 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2486 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2487 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2488 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2489 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2490 | } |
| 2491 | |
| 2492 | /* XXX: check any measured value ? */ |
| 2493 | |
| 2494 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2495 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2496 | ~MCHBAR32(IOSAV_By_BW_SERROR_ch(channel, lane)) & 0xff; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2497 | } |
| 2498 | |
| 2499 | fill_pattern0(ctrl, channel, 0, 0xffffffff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2500 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2501 | } |
| 2502 | |
Angel Pons | 0c3936e | 2020-03-22 12:49:27 +0100 | [diff] [blame] | 2503 | /* |
| 2504 | * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will |
| 2505 | * also use a single loop. It would seem that it is a debugging configuration. |
| 2506 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2507 | MCHBAR32(IOSAV_DC_MASK) = 0x300; |
| 2508 | printram("discover falling edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2509 | |
| 2510 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2511 | err = discover_edges_real(ctrl, channel, slotrank, |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2512 | falling_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2513 | if (err) |
| 2514 | return err; |
| 2515 | } |
| 2516 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2517 | MCHBAR32(IOSAV_DC_MASK) = 0x200; |
| 2518 | printram("discover rising edges:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2519 | |
| 2520 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2521 | err = discover_edges_real(ctrl, channel, slotrank, |
| 2522 | rising_edges[channel][slotrank]); |
| 2523 | if (err) |
| 2524 | return err; |
| 2525 | } |
| 2526 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2527 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2528 | |
| 2529 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2530 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
| 2531 | falling_edges[channel][slotrank][lane]; |
| 2532 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
| 2533 | rising_edges[channel][slotrank][lane]; |
| 2534 | } |
| 2535 | |
| 2536 | FOR_ALL_POPULATED_CHANNELS { |
| 2537 | program_timings(ctrl, channel); |
| 2538 | } |
| 2539 | |
| 2540 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2541 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2542 | } |
| 2543 | return 0; |
| 2544 | } |
| 2545 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2546 | static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2547 | { |
| 2548 | int edge; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2549 | u32 raw_stats[MAX_EDGE_TIMING + 1]; |
| 2550 | int stats[MAX_EDGE_TIMING + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2551 | const int reg3000b24[] = { 0, 0xc, 0x2c }; |
| 2552 | int lane, i; |
| 2553 | int lower[NUM_LANES]; |
| 2554 | int upper[NUM_LANES]; |
| 2555 | int pat; |
| 2556 | |
| 2557 | FOR_ALL_LANES { |
| 2558 | lower[lane] = 0; |
| 2559 | upper[lane] = MAX_EDGE_TIMING; |
| 2560 | } |
| 2561 | |
| 2562 | for (i = 0; i < 3; i++) { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2563 | MCHBAR32(GDCRTRAININGMOD_ch(channel)) = reg3000b24[i] << 24; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2564 | printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), reg3000b24[i] << 24); |
| 2565 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2566 | for (pat = 0; pat < NUM_PATTERNS; pat++) { |
| 2567 | fill_pattern5(ctrl, channel, pat); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2568 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2569 | printram("using pattern %d\n", pat); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2570 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2571 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { |
| 2572 | FOR_ALL_LANES { |
| 2573 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 2574 | rising = edge; |
| 2575 | ctrl->timings[channel][slotrank].lanes[lane]. |
| 2576 | falling = edge; |
| 2577 | } |
| 2578 | program_timings(ctrl, channel); |
| 2579 | |
| 2580 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2581 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)) = 0; |
| 2582 | MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2583 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2584 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2585 | |
| 2586 | /* DRAM command ACT */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2587 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2588 | IOSAV_ACT | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2589 | 4, MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), ctrl->tRCD, SSQ_NA, |
| 2590 | 0, 6, 0, slotrank, |
| 2591 | ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2592 | |
| 2593 | /* DRAM command WR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2594 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2595 | IOSAV_WR | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2596 | 32, 20, ctrl->tWTR + ctrl->CWL + 8, SSQ_WR, |
| 2597 | 0, 0, 0, slotrank, |
| 2598 | ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2599 | |
| 2600 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2601 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2602 | IOSAV_RD | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2603 | 32, 20, MAX(ctrl->tRTP, 8), SSQ_RD, |
| 2604 | 0, 0, 0, slotrank, |
| 2605 | ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2606 | |
| 2607 | /* DRAM command PRE */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2608 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2609 | IOSAV_PRE | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2610 | 1, 3, ctrl->tRP, SSQ_NA, |
| 2611 | 1024, 6, 0, slotrank, |
| 2612 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2613 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2614 | /* Execute command queue */ |
| 2615 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2616 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2617 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2618 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2619 | MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2620 | } |
| 2621 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2622 | /* FIXME: This register only exists on Ivy Bridge */ |
Angel Pons | 098240eb | 2020-03-22 12:55:32 +0100 | [diff] [blame] | 2623 | raw_stats[edge] = MCHBAR32(IOSAV_BYTE_SERROR_C_ch(channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2624 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2625 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2626 | FOR_ALL_LANES { |
| 2627 | struct run rn; |
| 2628 | for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2629 | stats[edge] = !!(raw_stats[edge] & (1 << lane)); |
| 2630 | |
| 2631 | rn = get_longest_zero_run(stats, MAX_EDGE_TIMING + 1); |
| 2632 | |
| 2633 | printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, " |
| 2634 | "0x%02x-0x%02x\n", channel, slotrank, i, rn.start, |
| 2635 | rn.middle, rn.end, rn.start + ctrl->edge_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2636 | rn.end - ctrl->edge_offset[i]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2637 | |
| 2638 | lower[lane] = MAX(rn.start + ctrl->edge_offset[i], lower[lane]); |
| 2639 | upper[lane] = MIN(rn.end - ctrl->edge_offset[i], upper[lane]); |
| 2640 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2641 | edges[lane] = (lower[lane] + upper[lane]) / 2; |
| 2642 | if (rn.all || (lower[lane] > upper[lane])) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2643 | printk(BIOS_EMERG, "edge write discovery failed: " |
| 2644 | "%d, %d, %d\n", channel, slotrank, lane); |
| 2645 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2646 | return MAKE_ERR; |
| 2647 | } |
| 2648 | } |
| 2649 | } |
| 2650 | } |
| 2651 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2652 | MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2653 | printram("CPA\n"); |
| 2654 | return 0; |
| 2655 | } |
| 2656 | |
| 2657 | int discover_edges_write(ramctr_timing *ctrl) |
| 2658 | { |
| 2659 | int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2660 | int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2661 | int channel, slotrank, lane, err; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2662 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2663 | /* |
| 2664 | * FIXME: Under some conditions, vendor BIOS sets both edges to the same value. It will |
| 2665 | * also use a single loop. It would seem that it is a debugging configuration. |
| 2666 | */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2667 | MCHBAR32(IOSAV_DC_MASK) = 0x300; |
| 2668 | printram("discover falling edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2669 | |
| 2670 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2671 | err = discover_edges_write_real(ctrl, channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2672 | falling_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2673 | if (err) |
| 2674 | return err; |
| 2675 | } |
| 2676 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2677 | MCHBAR32(IOSAV_DC_MASK) = 0x200; |
| 2678 | printram("discover rising edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2679 | |
| 2680 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2681 | err = discover_edges_write_real(ctrl, channel, slotrank, |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2682 | rising_edges[channel][slotrank]); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2683 | if (err) |
| 2684 | return err; |
| 2685 | } |
| 2686 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2687 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2688 | |
| 2689 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2690 | ctrl->timings[channel][slotrank].lanes[lane].falling = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2691 | falling_edges[channel][slotrank][lane]; |
| 2692 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2693 | ctrl->timings[channel][slotrank].lanes[lane].rising = |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2694 | rising_edges[channel][slotrank][lane]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2695 | } |
| 2696 | |
| 2697 | FOR_ALL_POPULATED_CHANNELS |
| 2698 | program_timings(ctrl, channel); |
| 2699 | |
| 2700 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2701 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2702 | } |
| 2703 | return 0; |
| 2704 | } |
| 2705 | |
| 2706 | static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) |
| 2707 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2708 | wait_for_iosav(channel); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2709 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2710 | /* DRAM command ACT */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2711 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2712 | IOSAV_ACT | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2713 | 4, MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), ctrl->tRCD, SSQ_NA, |
| 2714 | 0, 6, 0, slotrank, |
| 2715 | ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2716 | |
| 2717 | /* DRAM command WR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2718 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2719 | IOSAV_WR | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2720 | 480, 4, ctrl->tWTR + ctrl->CWL + 8, SSQ_WR, |
| 2721 | 0, 0, 0, slotrank, |
| 2722 | ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2723 | |
| 2724 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2725 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2726 | IOSAV_RD | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2727 | 480, 4, MAX(ctrl->tRTP, 8), SSQ_RD, |
| 2728 | 0, 0, 0, slotrank, |
| 2729 | ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2730 | |
| 2731 | /* DRAM command PRE */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2732 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2733 | IOSAV_PRE | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2734 | 1, 4, ctrl->tRP, SSQ_NA, |
| 2735 | 1024, 6, 0, slotrank, |
| 2736 | ADDR_UPDATE_NONE); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2737 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2738 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2739 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2740 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2741 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2742 | } |
| 2743 | |
| 2744 | int discover_timC_write(ramctr_timing *ctrl) |
| 2745 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2746 | const u8 rege3c_b24[3] = { 0, 0x0f, 0x2f }; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2747 | int i, pat; |
| 2748 | |
| 2749 | int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2750 | int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; |
| 2751 | int channel, slotrank, lane; |
| 2752 | |
| 2753 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
| 2754 | lower[channel][slotrank][lane] = 0; |
| 2755 | upper[channel][slotrank][lane] = MAX_TIMC; |
| 2756 | } |
| 2757 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2758 | /* |
| 2759 | * Enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. |
| 2760 | * FIXME: This must only be done on Ivy Bridge. |
| 2761 | */ |
| 2762 | MCHBAR32(MCMNTS_SPARE) = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2763 | printram("discover timC write:\n"); |
| 2764 | |
| 2765 | for (i = 0; i < 3; i++) |
| 2766 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2767 | |
| 2768 | /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ |
| 2769 | MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), |
| 2770 | ~0x3f000000, rege3c_b24[i] << 24); |
| 2771 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2772 | udelay(2); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2773 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2774 | for (pat = 0; pat < NUM_PATTERNS; pat++) { |
| 2775 | FOR_ALL_POPULATED_RANKS { |
| 2776 | int timC; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2777 | u32 raw_stats[MAX_TIMC + 1]; |
| 2778 | int stats[MAX_TIMC + 1]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2779 | |
| 2780 | /* Make sure rn.start < rn.end */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2781 | stats[MAX_TIMC] = 1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2782 | |
| 2783 | fill_pattern5(ctrl, channel, pat); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2784 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0x1f; |
| 2785 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2786 | for (timC = 0; timC < MAX_TIMC; timC++) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2787 | FOR_ALL_LANES { |
| 2788 | ctrl->timings[channel][slotrank] |
| 2789 | .lanes[lane].timC = timC; |
| 2790 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2791 | program_timings(ctrl, channel); |
| 2792 | |
| 2793 | test_timC_write (ctrl, channel, slotrank); |
| 2794 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2795 | /* FIXME: Another IVB-only register! */ |
Angel Pons | 098240eb | 2020-03-22 12:55:32 +0100 | [diff] [blame] | 2796 | raw_stats[timC] = MCHBAR32( |
| 2797 | IOSAV_BYTE_SERROR_C_ch(channel)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2798 | } |
| 2799 | FOR_ALL_LANES { |
| 2800 | struct run rn; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2801 | for (timC = 0; timC < MAX_TIMC; timC++) { |
| 2802 | stats[timC] = !!(raw_stats[timC] |
| 2803 | & (1 << lane)); |
| 2804 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2805 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2806 | rn = get_longest_zero_run(stats, MAX_TIMC + 1); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2807 | if (rn.all) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2808 | printk(BIOS_EMERG, |
| 2809 | "timC write discovery failed: " |
| 2810 | "%d, %d, %d\n", channel, |
| 2811 | slotrank, lane); |
| 2812 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2813 | return MAKE_ERR; |
| 2814 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2815 | printram("timC: %d, %d, %d: " |
| 2816 | "0x%02x-0x%02x-0x%02x, " |
| 2817 | "0x%02x-0x%02x\n", channel, slotrank, |
| 2818 | i, rn.start, rn.middle, rn.end, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2819 | rn.start + ctrl->timC_offset[i], |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2820 | rn.end - ctrl->timC_offset[i]); |
| 2821 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2822 | lower[channel][slotrank][lane] = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2823 | MAX(rn.start + ctrl->timC_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2824 | lower[channel][slotrank][lane]); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2825 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2826 | upper[channel][slotrank][lane] = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2827 | MIN(rn.end - ctrl->timC_offset[i], |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2828 | upper[channel][slotrank][lane]); |
| 2829 | |
| 2830 | } |
| 2831 | } |
| 2832 | } |
| 2833 | } |
| 2834 | |
| 2835 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2836 | /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2837 | MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2838 | udelay(2); |
| 2839 | } |
| 2840 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2841 | /* |
| 2842 | * Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. |
| 2843 | * FIXME: This must only be done on Ivy Bridge. |
| 2844 | */ |
| 2845 | MCHBAR32(MCMNTS_SPARE) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2846 | |
| 2847 | printram("CPB\n"); |
| 2848 | |
| 2849 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2850 | printram("timC %d, %d, %d: %x\n", channel, slotrank, lane, |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2851 | (lower[channel][slotrank][lane] + |
| 2852 | upper[channel][slotrank][lane]) / 2); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2853 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2854 | ctrl->timings[channel][slotrank].lanes[lane].timC = |
| 2855 | (lower[channel][slotrank][lane] + |
| 2856 | upper[channel][slotrank][lane]) / 2; |
| 2857 | } |
| 2858 | FOR_ALL_POPULATED_CHANNELS { |
| 2859 | program_timings(ctrl, channel); |
| 2860 | } |
| 2861 | return 0; |
| 2862 | } |
| 2863 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2864 | void normalize_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2865 | { |
| 2866 | int channel, slotrank, lane; |
Patrick Rudolph | 3c8cb97 | 2016-11-25 16:00:01 +0100 | [diff] [blame] | 2867 | int mat; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2868 | |
| 2869 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2870 | int delta; |
Patrick Rudolph | 3c8cb97 | 2016-11-25 16:00:01 +0100 | [diff] [blame] | 2871 | mat = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2872 | FOR_ALL_LANES mat = |
Elyes HAOUAS | f97c1c9 | 2019-12-03 18:22:06 +0100 | [diff] [blame] | 2873 | MAX(ctrl->timings[channel][slotrank].lanes[lane].timA, mat); |
Patrick Rudolph | 413edc8 | 2016-11-25 15:40:07 +0100 | [diff] [blame] | 2874 | printram("normalize %d, %d, %d: mat %d\n", |
| 2875 | channel, slotrank, lane, mat); |
| 2876 | |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 2877 | delta = (mat >> 6) - ctrl->timings[channel][slotrank].io_latency; |
Patrick Rudolph | 413edc8 | 2016-11-25 15:40:07 +0100 | [diff] [blame] | 2878 | printram("normalize %d, %d, %d: delta %d\n", |
| 2879 | channel, slotrank, lane, delta); |
| 2880 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2881 | ctrl->timings[channel][slotrank].roundtrip_latency += delta; |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 2882 | ctrl->timings[channel][slotrank].io_latency += delta; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2883 | } |
| 2884 | |
| 2885 | FOR_ALL_POPULATED_CHANNELS { |
| 2886 | program_timings(ctrl, channel); |
| 2887 | } |
| 2888 | } |
| 2889 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2890 | void write_controller_mr(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2891 | { |
| 2892 | int channel, slotrank; |
| 2893 | |
| 2894 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 2895 | MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT1(channel)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2896 | make_mr0(ctrl, slotrank); |
Felix Held | fb19c8a | 2020-01-14 21:27:59 +0100 | [diff] [blame] | 2897 | MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT2(channel)) = |
Felix Held | 2bb3cdf | 2018-07-28 00:23:59 +0200 | [diff] [blame] | 2898 | make_mr1(ctrl, slotrank, channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2899 | } |
| 2900 | } |
| 2901 | |
| 2902 | int channel_test(ramctr_timing *ctrl) |
| 2903 | { |
| 2904 | int channel, slotrank, lane; |
| 2905 | |
| 2906 | slotrank = 0; |
| 2907 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2908 | if (MCHBAR32(MC_INIT_STATE_ch(channel)) & 0xa000) { |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 2909 | printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2910 | return MAKE_ERR; |
| 2911 | } |
| 2912 | FOR_ALL_POPULATED_CHANNELS { |
| 2913 | fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); |
| 2914 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2915 | MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2916 | } |
| 2917 | |
| 2918 | for (slotrank = 0; slotrank < 4; slotrank++) |
| 2919 | FOR_ALL_CHANNELS |
| 2920 | if (ctrl->rankmap[channel] & (1 << slotrank)) { |
| 2921 | FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2922 | MCHBAR32(IOSAV_By_ERROR_COUNT(lane)) = 0; |
| 2923 | MCHBAR32(IOSAV_By_BW_SERROR_C(lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2924 | } |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2925 | wait_for_iosav(channel); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2926 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2927 | /* DRAM command ACT */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2928 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2929 | IOSAV_ACT | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2930 | 4, 40, 40, SSQ_NA, |
| 2931 | 0, 6, 0, slotrank, |
| 2932 | ADDR_UPDATE(0, 0, 1, 0, 18, 0, 0, 0)); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2933 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2934 | /* DRAM command WR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2935 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2936 | IOSAV_WR | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2937 | 100, 4, 40, SSQ_WR, |
| 2938 | 0, 0, 0, slotrank, |
| 2939 | ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2940 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2941 | /* DRAM command RD */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2942 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2943 | IOSAV_RD | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2944 | 100, 4, 40, SSQ_RD, |
| 2945 | 0, 0, 0, slotrank, |
| 2946 | ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2947 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2948 | /* DRAM command PRE */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2949 | IOSAV_SUBSEQUENCE(channel, 3, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2950 | IOSAV_PRE | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2951 | 1, 3, 40, SSQ_NA, |
| 2952 | 1024, 6, 0, slotrank, |
| 2953 | ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2954 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 2955 | /* Execute command queue */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2956 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(4); |
Felix Held | 9cf1dd2 | 2018-07-31 14:52:40 +0200 | [diff] [blame] | 2957 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2958 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2959 | FOR_ALL_LANES |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 2960 | if (MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane))) { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2961 | printk(BIOS_EMERG, "Mini channel test failed (2): %d, %d, %d\n", |
| 2962 | channel, slotrank, lane); |
| 2963 | return MAKE_ERR; |
| 2964 | } |
| 2965 | } |
| 2966 | return 0; |
| 2967 | } |
| 2968 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2969 | void channel_scrub(ramctr_timing *ctrl) |
| 2970 | { |
| 2971 | int channel, slotrank, row, rowsize; |
| 2972 | |
| 2973 | FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { |
| 2974 | rowsize = 1 << ctrl->info.dimm[channel][slotrank >> 1].row_bits; |
| 2975 | for (row = 0; row < rowsize; row += 16) { |
| 2976 | |
| 2977 | wait_for_iosav(channel); |
| 2978 | |
| 2979 | /* DRAM command ACT */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2980 | IOSAV_SUBSEQUENCE(channel, 0, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2981 | IOSAV_ACT | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2982 | 1, MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD), ctrl->tRCD, SSQ_NA, |
| 2983 | row, 6, 0, slotrank, |
| 2984 | ADDR_UPDATE(1, 0, 0, 0, 18, 0, 0, 0)); |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2985 | |
| 2986 | /* DRAM command WR */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2987 | IOSAV_SUBSEQUENCE(channel, 1, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2988 | IOSAV_WR | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2989 | 129, 4, 40, SSQ_WR, |
| 2990 | row, 0, 0, slotrank, |
| 2991 | ADDR_UPDATE(0, 1, 0, 0, 18, 0, 0, 0)); |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2992 | |
| 2993 | /* DRAM command PRE */ |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2994 | IOSAV_SUBSEQUENCE(channel, 2, |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 2995 | IOSAV_PRE | RANKSEL, |
Angel Pons | ca00dec | 2020-05-02 15:04:00 +0200 | [diff] [blame] | 2996 | 1, 3, 40, SSQ_NA, |
| 2997 | 1024, 6, 0, slotrank, |
| 2998 | ADDR_UPDATE(0, 0, 0, 0, 18, 0, 0, 0)); |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 2999 | |
| 3000 | /* execute command queue */ |
| 3001 | MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); |
| 3002 | |
| 3003 | wait_for_iosav(channel); |
| 3004 | } |
| 3005 | } |
| 3006 | } |
| 3007 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3008 | void set_scrambling_seed(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3009 | { |
| 3010 | int channel; |
| 3011 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3012 | /* FIXME: we hardcode seeds. Do we need to use some PRNG for them? I don't think so. */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3013 | static u32 seeds[NUM_CHANNELS][3] = { |
| 3014 | {0x00009a36, 0xbafcfdcf, 0x46d1ab68}, |
| 3015 | {0x00028bfa, 0x53fe4b49, 0x19ed5483} |
| 3016 | }; |
| 3017 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3018 | MCHBAR32(SCHED_CBIT_ch(channel)) &= ~0x10000000; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3019 | MCHBAR32(SCRAMBLING_SEED_1_ch(channel)) = seeds[channel][0]; |
| 3020 | MCHBAR32(SCRAMBLING_SEED_2_HI_ch(channel)) = seeds[channel][1]; |
| 3021 | MCHBAR32(SCRAMBLING_SEED_2_LO_ch(channel)) = seeds[channel][2]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3022 | } |
| 3023 | } |
| 3024 | |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 3025 | void set_wmm_behavior(const u32 cpu) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3026 | { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3027 | if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3028 | MCHBAR32(SC_WDBWM) = 0x141d1519; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3029 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3030 | MCHBAR32(SC_WDBWM) = 0x551d1519; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3031 | } |
| 3032 | } |
| 3033 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3034 | void prepare_training(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3035 | { |
| 3036 | int channel; |
| 3037 | |
| 3038 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3039 | /* Always drive command bus */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3040 | MCHBAR32_OR(TC_RAP_ch(channel), 0x20000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3041 | } |
| 3042 | |
| 3043 | udelay(1); |
| 3044 | |
| 3045 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3046 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3047 | } |
| 3048 | } |
| 3049 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3050 | void set_read_write_timings(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3051 | { |
| 3052 | int channel, slotrank; |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 3053 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3054 | FOR_ALL_POPULATED_CHANNELS { |
| 3055 | u32 b20, b4_8_12; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3056 | int min_pi = 10000; |
| 3057 | int max_pi = -10000; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3058 | |
| 3059 | FOR_ALL_POPULATED_RANKS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3060 | max_pi = MAX(ctrl->timings[channel][slotrank].pi_coding, max_pi); |
| 3061 | min_pi = MIN(ctrl->timings[channel][slotrank].pi_coding, min_pi); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3062 | } |
| 3063 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3064 | b20 = (max_pi - min_pi > 51) ? 0 : ctrl->ref_card_offset[channel]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3065 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3066 | b4_8_12 = (ctrl->pi_coding_threshold < max_pi - min_pi) ? 0x3330 : 0x2220; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3067 | |
Patrick Rudolph | 19c3dad | 2016-11-26 11:37:45 +0100 | [diff] [blame] | 3068 | dram_odt_stretch(ctrl, channel); |
| 3069 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3070 | MCHBAR32(TC_RWP_ch(channel)) = 0x0a000000 | (b20 << 20) | |
Felix Held | 2463aa9 | 2018-07-29 21:37:55 +0200 | [diff] [blame] | 3071 | ((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3072 | } |
| 3073 | } |
| 3074 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3075 | void set_normal_operation(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3076 | { |
| 3077 | int channel; |
| 3078 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3079 | MCHBAR32(MC_INIT_STATE_ch(channel)) = 0x00001000 | ctrl->rankmap[channel]; |
| 3080 | MCHBAR32_AND(TC_RAP_ch(channel), ~0x20000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3081 | } |
| 3082 | } |
| 3083 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3084 | /* Encode the watermark latencies in a suitable format for graphics drivers consumption */ |
| 3085 | static int encode_wm(int ns) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3086 | { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3087 | return (ns + 499) / 500; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3088 | } |
| 3089 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3090 | /* FIXME: values in this function should be hardware revision-dependent */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3091 | void final_registers(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3092 | { |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 3093 | const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; |
| 3094 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3095 | int channel; |
| 3096 | int t1_cycles = 0, t1_ns = 0, t2_ns; |
| 3097 | int t3_ns; |
| 3098 | u32 r32; |
| 3099 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3100 | /* FIXME: This register only exists on Ivy Bridge */ |
| 3101 | MCHBAR32(WMM_READ_CONFIG) = 0x46; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3102 | |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3103 | FOR_ALL_CHANNELS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3104 | MCHBAR32_AND_OR(TC_OTHP_ch(channel), 0xffffcfff, 0x1000); |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3105 | |
Patrick Rudolph | 74203de | 2017-11-20 11:57:01 +0100 | [diff] [blame] | 3106 | if (is_mobile) |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3107 | /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ |
Angel Pons | 2a9a49b | 2019-12-31 14:24:12 +0100 | [diff] [blame] | 3108 | MCHBAR32(PM_PDWN_CONFIG) = 0x00000740; |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3109 | else |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3110 | /* APD - PPD, 64 DCLKs until idle, decision per rank */ |
Angel Pons | 2a9a49b | 2019-12-31 14:24:12 +0100 | [diff] [blame] | 3111 | MCHBAR32(PM_PDWN_CONFIG) = 0x00000340; |
Patrick Rudolph | 652c491 | 2017-10-31 11:36:55 +0100 | [diff] [blame] | 3112 | |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3113 | FOR_ALL_CHANNELS |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3114 | MCHBAR32(PM_TRML_M_CONFIG_ch(channel)) = 0x00000aaa; |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3115 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3116 | MCHBAR32(PM_BW_LIMIT_CONFIG) = 0x5f7003ff; // OK |
| 3117 | MCHBAR32(PM_DLL_CONFIG) = 0x00073000 | ctrl->mdll_wake_delay; // OK |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3118 | |
| 3119 | FOR_ALL_CHANNELS { |
| 3120 | switch (ctrl->rankmap[channel]) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3121 | /* Unpopulated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3122 | case 0: |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3123 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3124 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3125 | /* Only single-ranked dimms */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3126 | case 1: |
| 3127 | case 4: |
| 3128 | case 5: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3129 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x00373131; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3130 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3131 | /* Dual-ranked dimms present */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3132 | default: |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3133 | MCHBAR32(PM_CMD_PWR_ch(channel)) = 0x009b6ea1; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3134 | break; |
| 3135 | } |
| 3136 | } |
| 3137 | |
Felix Held | 50b7ed2 | 2019-12-30 20:41:54 +0100 | [diff] [blame] | 3138 | MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3139 | MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0x00ffffff, 0x00e4d5d0); |
Felix Held | 50b7ed2 | 2019-12-30 20:41:54 +0100 | [diff] [blame] | 3140 | MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); |
Felix Held | f9b826a | 2018-07-30 17:56:52 +0200 | [diff] [blame] | 3141 | |
| 3142 | FOR_ALL_CHANNELS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3143 | MCHBAR32_AND_OR(TC_RFP_ch(channel), ~(3 << 16), 1 << 16); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3144 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3145 | MCHBAR32_OR(MC_INIT_STATE_G, 1); |
| 3146 | MCHBAR32_OR(MC_INIT_STATE_G, 0x80); |
| 3147 | MCHBAR32(BANDTIMERS_SNB) = 0xfa; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3148 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3149 | /* Find a populated channel */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3150 | FOR_ALL_POPULATED_CHANNELS |
| 3151 | break; |
| 3152 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3153 | t1_cycles = (MCHBAR32(TC_ZQCAL_ch(channel)) >> 8) & 0xff; |
| 3154 | r32 = MCHBAR32(PM_DLL_CONFIG); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3155 | if (r32 & (1 << 17)) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3156 | t1_cycles += (r32 & 0xfff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3157 | t1_cycles += MCHBAR32(TC_SRFTP_ch(channel)) & 0xfff; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3158 | t1_ns = t1_cycles * ctrl->tCK / 256 + 544; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3159 | if (!(r32 & (1 << 17))) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3160 | t1_ns += 500; |
| 3161 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3162 | t2_ns = 10 * ((MCHBAR32(SAPMTIMERS) >> 8) & 0xfff); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3163 | if (MCHBAR32(SAPMCTL) & 8) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3164 | t3_ns = 10 * ((MCHBAR32(BANDTIMERS_IVB) >> 8) & 0xfff); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3165 | t3_ns += 10 * (MCHBAR32(SAPMTIMERS2_IVB) & 0xff); |
Angel Pons | 891f2bc | 2020-01-10 01:27:28 +0100 | [diff] [blame] | 3166 | } else { |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3167 | t3_ns = 500; |
| 3168 | } |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3169 | |
| 3170 | /* The graphics driver will use these watermark values */ |
| 3171 | printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); |
| 3172 | MCHBAR32_AND_OR(SSKPD, 0xC0C0C0C0, |
| 3173 | ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | |
| 3174 | ((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3175 | } |
| 3176 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3177 | void restore_timings(ramctr_timing *ctrl) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3178 | { |
| 3179 | int channel, slotrank, lane; |
| 3180 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3181 | FOR_ALL_POPULATED_CHANNELS { |
| 3182 | MCHBAR32(TC_RAP_ch(channel)) = |
| 3183 | (ctrl->tRRD << 0) |
| 3184 | | (ctrl->tRTP << 4) |
| 3185 | | (ctrl->tCKE << 8) |
| 3186 | | (ctrl->tWTR << 12) |
| 3187 | | (ctrl->tFAW << 16) |
| 3188 | | (ctrl->tWR << 24) |
| 3189 | | (ctrl->cmd_stretch[channel] << 30); |
| 3190 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3191 | |
| 3192 | udelay(1); |
| 3193 | |
| 3194 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3195 | wait_for_iosav(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3196 | } |
| 3197 | |
| 3198 | FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3199 | MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3200 | } |
| 3201 | |
| 3202 | FOR_ALL_POPULATED_CHANNELS |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3203 | MCHBAR32_OR(TC_RWP_ch(channel), 0x08000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3204 | |
| 3205 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3206 | udelay(1); |
| 3207 | MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x00200000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3208 | } |
| 3209 | |
| 3210 | printram("CPE\n"); |
| 3211 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3212 | MCHBAR32(GDCRTRAININGMOD) = 0; |
| 3213 | MCHBAR32(IOSAV_DC_MASK) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3214 | |
| 3215 | printram("CP5b\n"); |
| 3216 | |
| 3217 | FOR_ALL_POPULATED_CHANNELS { |
| 3218 | program_timings(ctrl, channel); |
| 3219 | } |
| 3220 | |
| 3221 | u32 reg, addr; |
| 3222 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3223 | /* Poll for RCOMP */ |
| 3224 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 3225 | ; |
| 3226 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3227 | do { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3228 | reg = MCHBAR32(IOSAV_STATUS_ch(0)); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3229 | } while ((reg & 0x14) == 0); |
| 3230 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3231 | /* Set state of memory controller */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3232 | MCHBAR32(MC_INIT_STATE_G) = 0x116; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3233 | MCHBAR32(MC_INIT_STATE) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3234 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3235 | /* Wait 500us */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3236 | udelay(500); |
| 3237 | |
| 3238 | FOR_ALL_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3239 | /* Set valid rank CKE */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3240 | reg = 0; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3241 | reg = (reg & ~0x0f) | ctrl->rankmap[channel]; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3242 | addr = MC_INIT_STATE_ch(channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3243 | MCHBAR32(addr) = reg; |
| 3244 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3245 | /* Wait 10ns for ranks to settle */ |
| 3246 | // udelay(0.01); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3247 | |
| 3248 | reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4); |
| 3249 | MCHBAR32(addr) = reg; |
| 3250 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3251 | /* Write reset using a NOP */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3252 | write_reset(ctrl); |
| 3253 | } |
| 3254 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 3255 | /* MRS commands */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3256 | dram_mrscommands(ctrl); |
| 3257 | |
| 3258 | printram("CP5c\n"); |
| 3259 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3260 | MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3261 | |
| 3262 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 3263 | MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3264 | udelay(2); |
| 3265 | } |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 3266 | } |