Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2006 Tyan |
| 5 | * Copyright (C) 2006 AMD |
| 6 | * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD. |
| 7 | * |
| 8 | * Copyright (C) 2007 University of Mannheim |
| 9 | * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim |
| 10 | * Copyright (C) 2009 University of Heidelberg |
| 11 | * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License as published by |
| 15 | * the Free Software Foundation; either version 2 of the License, or |
| 16 | * (at your option) any later version. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 22 | */ |
| 23 | |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 24 | #include <stdint.h> |
| 25 | #include <string.h> |
| 26 | #include <device/pci_def.h> |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 27 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 28 | #include <device/pci_ops.h> |
Elyes HAOUAS | d2b9ec1 | 2018-10-27 09:41:02 +0200 | [diff] [blame] | 29 | #include <arch/cpu.h> |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 30 | #include <cpu/x86/lapic.h> |
| 31 | #include "option_table.h" |
| 32 | #include <console/console.h> |
Timothy Pearson | 91e9f67 | 2015-03-19 16:44:46 -0500 | [diff] [blame] | 33 | #include <timestamp.h> |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 34 | #include <cpu/amd/model_10xxx_rev.h> |
Uwe Hermann | 26535d6 | 2010-11-20 20:36:40 +0000 | [diff] [blame] | 35 | #include <spd.h> |
Edward O'Callaghan | ebe3a7a | 2015-01-05 00:27:54 +1100 | [diff] [blame] | 36 | #include <delay.h> |
Edward O'Callaghan | f18abab | 2014-03-31 21:53:32 +1100 | [diff] [blame] | 37 | #include <superio/serverengines/pilot/pilot.h> |
Edward O'Callaghan | b8f05d4 | 2015-01-04 16:17:54 +1100 | [diff] [blame] | 38 | #include <superio/nsc/pc87417/pc87417.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 39 | #include <cpu/x86/bist.h> |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 40 | #include <cpu/amd/car.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 41 | #include <cpu/amd/msr.h> |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 42 | #include <northbridge/amd/amdfam10/raminit.h> |
| 43 | #include <northbridge/amd/amdht/ht_wrapper.h> |
| 44 | #include <cpu/amd/family_10h-family_15h/init_cpus.h> |
| 45 | #include <arch/early_variables.h> |
| 46 | #include <cbmem.h> |
Nico Huber | 718c6fa | 2018-10-11 22:54:25 +0200 | [diff] [blame] | 47 | #include <southbridge/amd/common/reset.h> |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 48 | #include "southbridge/broadcom/bcm5785/early_smbus.c" |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 49 | #include "southbridge/broadcom/bcm5785/early_setup.c" |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 50 | |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 51 | #include "cpu/amd/quadcore/quadcore.c" |
| 52 | |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 53 | #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) |
| 54 | #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) |
| 55 | |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 56 | void activate_spd_rom(const struct mem_controller *ctrl); |
Elyes HAOUAS | dd35e2c | 2018-09-20 17:33:50 +0200 | [diff] [blame] | 57 | int spd_read_byte(unsigned int device, unsigned int address); |
Damien Zammit | 75a3d1f | 2016-11-28 00:29:10 +1100 | [diff] [blame] | 58 | extern struct sys_info sysinfo_car; |
| 59 | |
| 60 | inline void activate_spd_rom(const struct mem_controller *ctrl) |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 61 | { |
| 62 | u8 val; |
| 63 | outb(0x3d, 0x0cd6); |
| 64 | outb(0x87, 0x0cd7); |
| 65 | |
| 66 | outb(0x44, 0xcd6); |
| 67 | val = inb(0xcd7); |
| 68 | outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7); |
| 69 | } |
| 70 | |
Elyes HAOUAS | dd35e2c | 2018-09-20 17:33:50 +0200 | [diff] [blame] | 71 | inline int spd_read_byte(unsigned int device, unsigned int address) |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 72 | { |
| 73 | return smbus_read_byte(device, address); |
| 74 | } |
| 75 | |
Uwe Hermann | 26535d6 | 2010-11-20 20:36:40 +0000 | [diff] [blame] | 76 | static const u8 spd_addr[] = { |
| 77 | // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr |
| 78 | //first node |
| 79 | RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 80 | #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
| 81 | //second node |
| 82 | RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 83 | #endif |
| 84 | }; |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 85 | |
| 86 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 87 | { |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 88 | struct sys_info *sysinfo = &sysinfo_car; |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 89 | u32 bsp_apicid = 0, val; |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 90 | msr_t msr; |
Stefan Reinauer | 5ff7c13 | 2011-10-31 12:56:45 -0700 | [diff] [blame] | 91 | |
Timothy Pearson | 91e9f67 | 2015-03-19 16:44:46 -0500 | [diff] [blame] | 92 | timestamp_init(timestamp_get()); |
| 93 | timestamp_add_now(TS_START_ROMSTAGE); |
| 94 | |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 95 | if (!cpu_init_detectedx && boot_cpu()) { |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 96 | /* Nothing special needs to be done to find bus 0 */ |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 97 | /* Allow the HT devices to be found */ |
| 98 | /* mov bsp to bus 0xff when > 8 nodes */ |
| 99 | set_bsp_node_CHtExtNodeCfgEn(); |
| 100 | enumerate_ht_chain(); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 101 | bcm5785_enable_lpc(); |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 102 | pc87417_enable_dev(RTC_DEV); /* Enable RTC */ |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | post_code(0x30); |
| 106 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 107 | if (bist == 0) |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 108 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 109 | |
| 110 | pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 111 | |
Stefan Reinauer | 42fa7fe | 2011-04-20 20:54:07 +0000 | [diff] [blame] | 112 | console_init(); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 113 | |
| 114 | /* Halt if there was a built in self test failure */ |
| 115 | report_bist_failure(bist); |
| 116 | |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 117 | pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV |
| 118 | |
| 119 | val = cpuid_eax(1); |
| 120 | printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); |
| 121 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
| 122 | printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); |
| 123 | printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); |
| 124 | |
| 125 | /* Setup sysinfo defaults */ |
| 126 | set_sysinfo_in_ram(0); |
| 127 | |
| 128 | update_microcode(val); |
Kyösti Mälkki | f0a13ce | 2013-12-08 07:20:48 +0200 | [diff] [blame] | 129 | |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 130 | post_code(0x33); |
| 131 | |
Timothy Pearson | 730a043 | 2015-10-16 13:51:51 -0500 | [diff] [blame] | 132 | cpuSetAMDMSR(0); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 133 | post_code(0x34); |
| 134 | |
| 135 | amd_ht_init(sysinfo); |
| 136 | post_code(0x35); |
| 137 | |
| 138 | /* Setup nodes PCI space and start core 0 AP init. */ |
| 139 | finalize_node_setup(sysinfo); |
| 140 | |
| 141 | post_code(0x36); |
| 142 | |
| 143 | /* wait for all the APs core0 started by finalize_node_setup. */ |
| 144 | /* FIXME: A bunch of cores are going to start output to serial at once. |
| 145 | * It would be nice to fixup prink spinlocks for ROM XIP mode. |
| 146 | * I think it could be done by putting the spinlock flag in the cache |
| 147 | * of the BSP located right after sysinfo. |
| 148 | */ |
| 149 | |
| 150 | wait_all_core0_started(); |
| 151 | |
Martin Roth | 356b519 | 2017-06-24 21:53:37 -0600 | [diff] [blame] | 152 | #if IS_ENABLED(CONFIG_LOGICAL_CPUS) |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 153 | /* Core0 on each node is configured. Now setup any additional cores. */ |
| 154 | printk(BIOS_DEBUG, "start_other_cores()\n"); |
Timothy Pearson | 0122afb | 2015-07-30 14:07:15 -0500 | [diff] [blame] | 155 | start_other_cores(bsp_apicid); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 156 | post_code(0x37); |
| 157 | wait_all_other_cores_started(bsp_apicid); |
| 158 | #endif |
| 159 | |
Martin Roth | 356b519 | 2017-06-24 21:53:37 -0600 | [diff] [blame] | 160 | #if IS_ENABLED(CONFIG_SET_FIDVID) |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 161 | msr = rdmsr(MSR_COFVID_STS); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 162 | printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); |
| 163 | |
| 164 | /* FIXME: The sb fid change may survive the warm reset and only |
| 165 | * need to be done once.*/ |
| 166 | |
| 167 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 168 | |
| 169 | post_code(0x39); |
| 170 | |
| 171 | if (!warm_reset_detect(0)) { // BSP is node 0 |
| 172 | init_fidvid_bsp(bsp_apicid, sysinfo->nodes); |
| 173 | } else { |
| 174 | init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 |
| 175 | } |
| 176 | |
| 177 | post_code(0x3A); |
| 178 | |
| 179 | /* show final fid and vid */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 180 | msr = rdmsr(MSR_COFVID_STS); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 181 | printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); |
| 182 | #endif |
| 183 | |
| 184 | init_timer(); |
| 185 | |
| 186 | /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ |
| 187 | if (!warm_reset_detect(0)) { |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 188 | printk(BIOS_INFO, "...WARM RESET...\n\n\n"); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 189 | soft_reset(); |
Jonathan Neuschäfer | ec48c74 | 2017-09-29 02:45:31 +0200 | [diff] [blame] | 190 | die("After soft_reset - shouldn't see this message!!!\n"); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 191 | } |
| 192 | |
| 193 | /* It's the time to set ctrl in sysinfo now; */ |
| 194 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 195 | enable_smbus(); |
| 196 | |
Subrata Banik | 1f83e9d | 2019-01-30 15:04:00 +0530 | [diff] [blame] | 197 | //do we need ACPI timer, tsc...., only debug need it for better output |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 198 | /* all ap stopped? */ |
Paul Menzel | 4549e5a | 2014-02-02 22:05:48 +0100 | [diff] [blame] | 199 | // init_timer(); // Need to use TMICT to synchronize FID/VID |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 200 | |
Timothy Pearson | 91e9f67 | 2015-03-19 16:44:46 -0500 | [diff] [blame] | 201 | timestamp_add_now(TS_BEFORE_INITRAM); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 202 | printk(BIOS_DEBUG, "raminit_amdmct()\n"); |
| 203 | raminit_amdmct(sysinfo); |
Timothy Pearson | 91e9f67 | 2015-03-19 16:44:46 -0500 | [diff] [blame] | 204 | timestamp_add_now(TS_AFTER_INITRAM); |
| 205 | |
Timothy Pearson | 86f4ca5 | 2015-03-13 13:27:58 -0500 | [diff] [blame] | 206 | cbmem_initialize_empty(); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 207 | post_code(0x41); |
| 208 | |
Timothy Pearson | 2256408 | 2015-03-27 22:49:18 -0500 | [diff] [blame] | 209 | amdmct_cbmem_store_info(sysinfo); |
| 210 | |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 211 | bcm5785_early_setup(); |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 212 | } |
Scott Duplichan | 314dd0b | 2011-03-08 23:01:46 +0000 | [diff] [blame] | 213 | |
| 214 | /** |
| 215 | * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) |
| 216 | * Description: |
| 217 | * This routine is called every time a non-coherent chain is processed. |
| 218 | * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a |
| 219 | * swap list. The first part of the list controls the BUID assignment and the |
| 220 | * second part of the list provides the device to device linking. Device orientation |
| 221 | * can be detected automatically, or explicitly. See documentation for more details. |
| 222 | * |
| 223 | * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially |
| 224 | * based on each device's unit count. |
| 225 | * |
| 226 | * Parameters: |
Martin Roth | c3fde7e | 2014-12-29 22:13:37 -0700 | [diff] [blame] | 227 | * @param[in] node = The node on which this chain is located |
| 228 | * @param[in] link = The link on the host for this chain |
| 229 | * @param[out] List = supply a pointer to a list |
Scott Duplichan | 314dd0b | 2011-03-08 23:01:46 +0000 | [diff] [blame] | 230 | */ |
| 231 | BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) |
| 232 | { |
| 233 | static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; |
| 234 | /* If the BUID was adjusted in early_ht we need to do the manual override */ |
| 235 | if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { |
| 236 | printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); |
| 237 | if ((node == 0) && (link == 0)) { /* BSP SB link */ |
| 238 | *List = swaplist; |
| 239 | return 1; |
| 240 | } |
| 241 | } |
| 242 | |
| 243 | return 0; |
| 244 | } |