blob: 99f05950daf81aeee3baf242771979c92533f6d3 [file] [log] [blame]
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2006 Tyan
5 * Copyright (C) 2006 AMD
6 * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
7 *
8 * Copyright (C) 2007 University of Mannheim
9 * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
10 * Copyright (C) 2009 University of Heidelberg
11 * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
26 */
27
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +000028#define FAM10_SCAN_PCI_BUS 0
29#define FAM10_ALLOCATE_IO_RANGE 1
30
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +000031#include <stdint.h>
32#include <string.h>
33#include <device/pci_def.h>
34#include <device/pci_ids.h>
35#include <arch/io.h>
36#include <device/pnp_def.h>
37#include <arch/romcc_io.h>
38#include <cpu/x86/lapic.h>
39#include "option_table.h"
40#include <console/console.h>
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +000041#include <cpu/amd/model_10xxx_rev.h>
stepan836ae292010-12-08 05:42:47 +000042#include "southbridge/broadcom/bcm5785/early_smbus.c"
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +000043#include "northbridge/amd/amdfam10/raminit.h"
44#include "northbridge/amd/amdfam10/amdfam10.h"
Patrick Georgid0835952010-10-05 09:07:10 +000045#include <lib.h>
Uwe Hermann26535d62010-11-20 20:36:40 +000046#include <spd.h>
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +000047#include "cpu/amd/model_10xxx/apic_timer.c"
48#include "lib/delay.c"
49#include "cpu/x86/lapic/boot_cpu.c"
50#include "northbridge/amd/amdfam10/reset_test.c"
stepan8301d832010-12-08 07:07:33 +000051#include "superio/serverengines/pilot/early_serial.c"
52#include "superio/serverengines/pilot/early_init.c"
53#include "superio/nsc/pc87417/early_serial.c"
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +000054#include "cpu/x86/bist.h"
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +000055#include "northbridge/amd/amdfam10/debug.c"
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +000056#include "cpu/x86/mtrr/earlymtrr.c"
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +000057//#include "northbridge/amd/amdfam10/setup_resource_map.c"
stepan836ae292010-12-08 05:42:47 +000058#include "southbridge/broadcom/bcm5785/early_setup.c"
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +000059
60#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
61#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
62
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +000063static inline void activate_spd_rom(const struct mem_controller *ctrl)
64{
65 u8 val;
66 outb(0x3d, 0x0cd6);
67 outb(0x87, 0x0cd7);
68
69 outb(0x44, 0xcd6);
70 val = inb(0xcd7);
71 outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7);
72}
73
74static inline int spd_read_byte(unsigned device, unsigned address)
75{
76 return smbus_read_byte(device, address);
77}
78
79#include "northbridge/amd/amdfam10/amdfam10.h"
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +000080#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
stepan8301d832010-12-08 07:07:33 +000081#include "northbridge/amd/amdfam10/pci.c"
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +000082#include "cpu/amd/quadcore/quadcore.c"
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +000083#include "cpu/amd/car/post_cache_as_ram.c"
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +000084#include "cpu/amd/microcode/microcode.c"
Xavi Drudis Ferran4c28a6f2011-02-26 23:29:44 +000085
86#if CONFIG_UPDATE_CPU_MICROCODE
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +000087#include "cpu/amd/model_10xxx/update_microcode.c"
Xavi Drudis Ferran4c28a6f2011-02-26 23:29:44 +000088#endif
89
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +000090#include "cpu/amd/model_10xxx/init_cpus.c"
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +000091#include "northbridge/amd/amdfam10/early_ht.c"
92
Uwe Hermann26535d62010-11-20 20:36:40 +000093static const u8 spd_addr[] = {
94 // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr
95 //first node
96 RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
97#if CONFIG_MAX_PHYSICAL_CPUS > 1
98 //second node
99 RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
100#endif
101};
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +0000102
103void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
104{
105 struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
Uwe Hermann7b997052010-11-21 22:47:22 +0000106 u32 bsp_apicid = 0, val;
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +0000107 msr_t msr;
108
109 if (!cpu_init_detectedx && boot_cpu()) {
Uwe Hermann7b997052010-11-21 22:47:22 +0000110 /* Nothing special needs to be done to find bus 0 */
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +0000111 /* Allow the HT devices to be found */
112 /* mov bsp to bus 0xff when > 8 nodes */
113 set_bsp_node_CHtExtNodeCfgEn();
114 enumerate_ht_chain();
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +0000115 bcm5785_enable_lpc();
Uwe Hermann7b997052010-11-21 22:47:22 +0000116 pc87417_enable_dev(RTC_DEV); /* Enable RTC */
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +0000117 }
118
119 post_code(0x30);
120
Uwe Hermann7b997052010-11-21 22:47:22 +0000121 if (bist == 0)
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +0000122 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +0000123
124 pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
125
126 uart_init();
127
128 /* Halt if there was a built in self test failure */
129 report_bist_failure(bist);
130
131 console_init();
132 pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
133
134 val = cpuid_eax(1);
135 printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
136 printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
137 printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
138 printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
139
140 /* Setup sysinfo defaults */
141 set_sysinfo_in_ram(0);
142
Xavi Drudis Ferran4c28a6f2011-02-26 23:29:44 +0000143#if CONFIG_UPDATE_CPU_MICROCODE
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +0000144 update_microcode(val);
Xavi Drudis Ferran4c28a6f2011-02-26 23:29:44 +0000145#endif
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +0000146 post_code(0x33);
147
148 cpuSetAMDMSR();
149 post_code(0x34);
150
151 amd_ht_init(sysinfo);
152 post_code(0x35);
153
154 /* Setup nodes PCI space and start core 0 AP init. */
155 finalize_node_setup(sysinfo);
156
157 post_code(0x36);
158
159 /* wait for all the APs core0 started by finalize_node_setup. */
160 /* FIXME: A bunch of cores are going to start output to serial at once.
161 * It would be nice to fixup prink spinlocks for ROM XIP mode.
162 * I think it could be done by putting the spinlock flag in the cache
163 * of the BSP located right after sysinfo.
164 */
165
166 wait_all_core0_started();
167
168#if CONFIG_LOGICAL_CPUS==1
169 /* Core0 on each node is configured. Now setup any additional cores. */
170 printk(BIOS_DEBUG, "start_other_cores()\n");
171 start_other_cores();
172 post_code(0x37);
173 wait_all_other_cores_started(bsp_apicid);
174#endif
175
Patrick Georgi76e81522010-11-16 21:25:29 +0000176#if CONFIG_SET_FIDVID
Arne Georg Gleditsch9139e7b2010-09-24 17:35:32 +0000177 msr = rdmsr(0xc0010071);
178 printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
179
180 /* FIXME: The sb fid change may survive the warm reset and only
181 * need to be done once.*/
182
183 enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
184
185 post_code(0x39);
186
187 if (!warm_reset_detect(0)) { // BSP is node 0
188 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
189 } else {
190 init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
191 }
192
193 post_code(0x3A);
194
195 /* show final fid and vid */
196 msr=rdmsr(0xc0010071);
197 printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
198#endif
199
200 init_timer();
201
202 /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
203 if (!warm_reset_detect(0)) {
204 print_info("...WARM RESET...\n\n\n");
205 soft_reset();
206 die("After soft_reset_x - shouldn't see this message!!!\n");
207 }
208
209 /* It's the time to set ctrl in sysinfo now; */
210 fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
211 enable_smbus();
212
213 //do we need apci timer, tsc...., only debug need it for better output
214 /* all ap stopped? */
215// init_timer(); // Need to use TMICT to synconize FID/VID
216
217 printk(BIOS_DEBUG, "raminit_amdmct()\n");
218 raminit_amdmct(sysinfo);
219 post_code(0x41);
220
221 bcm5785_early_setup();
222
223 post_cache_as_ram();
224}
Scott Duplichan314dd0b2011-03-08 23:01:46 +0000225
226/**
227 * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
228 * Description:
229 * This routine is called every time a non-coherent chain is processed.
230 * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
231 * swap list. The first part of the list controls the BUID assignment and the
232 * second part of the list provides the device to device linking. Device orientation
233 * can be detected automatically, or explicitly. See documentation for more details.
234 *
235 * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
236 * based on each device's unit count.
237 *
238 * Parameters:
239 * @param[in] u8 node = The node on which this chain is located
240 * @param[in] u8 link = The link on the host for this chain
241 * @param[out] u8** list = supply a pointer to a list
242 * @param[out] BOOL result = true to use a manual list
243 * false to initialize the link automatically
244 */
245BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
246{
247 static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
248 /* If the BUID was adjusted in early_ht we need to do the manual override */
249 if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
250 printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
251 if ((node == 0) && (link == 0)) { /* BSP SB link */
252 *List = swaplist;
253 return 1;
254 }
255 }
256
257 return 0;
258}