Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2006 Tyan |
| 5 | * Copyright (C) 2006 AMD |
| 6 | * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD. |
| 7 | * |
| 8 | * Copyright (C) 2007 University of Mannheim |
| 9 | * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim |
| 10 | * Copyright (C) 2009 University of Heidelberg |
| 11 | * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or modify |
| 14 | * it under the terms of the GNU General Public License as published by |
| 15 | * the Free Software Foundation; either version 2 of the License, or |
| 16 | * (at your option) any later version. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License |
| 24 | * along with this program; if not, write to the Free Software |
| 25 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 26 | */ |
| 27 | |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 28 | #define FAM10_SCAN_PCI_BUS 0 |
| 29 | #define FAM10_ALLOCATE_IO_RANGE 1 |
| 30 | |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 31 | #include <stdint.h> |
| 32 | #include <string.h> |
| 33 | #include <device/pci_def.h> |
| 34 | #include <device/pci_ids.h> |
| 35 | #include <arch/io.h> |
| 36 | #include <device/pnp_def.h> |
| 37 | #include <arch/romcc_io.h> |
| 38 | #include <cpu/x86/lapic.h> |
| 39 | #include "option_table.h" |
| 40 | #include <console/console.h> |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 41 | #include <cpu/amd/model_10xxx_rev.h> |
| 42 | #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" |
Patrick Georgi | 9d4212f | 2010-10-26 15:51:57 +0000 | [diff] [blame] | 43 | #include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c" |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 44 | #include "northbridge/amd/amdfam10/raminit.h" |
| 45 | #include "northbridge/amd/amdfam10/amdfam10.h" |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 46 | #include <lib.h> |
Uwe Hermann | 26535d6 | 2010-11-20 20:36:40 +0000 | [diff] [blame^] | 47 | #include <spd.h> |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 48 | |
| 49 | #include "cpu/amd/model_10xxx/apic_timer.c" |
| 50 | #include "lib/delay.c" |
| 51 | #include "cpu/x86/lapic/boot_cpu.c" |
| 52 | #include "northbridge/amd/amdfam10/reset_test.c" |
| 53 | |
| 54 | #include "superio/serverengines/pilot/pilot_early_serial.c" |
| 55 | #include "superio/serverengines/pilot/pilot_early_init.c" |
| 56 | #include "superio/nsc/pc87417/pc87417_early_serial.c" |
| 57 | |
| 58 | #include "cpu/x86/bist.h" |
| 59 | |
| 60 | #include "northbridge/amd/amdfam10/debug.c" |
| 61 | |
| 62 | #include "cpu/x86/mtrr/earlymtrr.c" |
| 63 | |
| 64 | //#include "northbridge/amd/amdfam10/setup_resource_map.c" |
| 65 | |
| 66 | #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) |
| 67 | #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) |
| 68 | |
| 69 | #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" |
| 70 | |
| 71 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 72 | { |
| 73 | u8 val; |
| 74 | outb(0x3d, 0x0cd6); |
| 75 | outb(0x87, 0x0cd7); |
| 76 | |
| 77 | outb(0x44, 0xcd6); |
| 78 | val = inb(0xcd7); |
| 79 | outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7); |
| 80 | } |
| 81 | |
| 82 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 83 | { |
| 84 | return smbus_read_byte(device, address); |
| 85 | } |
| 86 | |
| 87 | #include "northbridge/amd/amdfam10/amdfam10.h" |
| 88 | |
| 89 | #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" |
| 90 | #include "northbridge/amd/amdfam10/amdfam10_pci.c" |
| 91 | |
| 92 | #include "cpu/amd/quadcore/quadcore.c" |
| 93 | |
| 94 | #include "cpu/amd/car/post_cache_as_ram.c" |
| 95 | |
| 96 | #include "cpu/amd/microcode/microcode.c" |
| 97 | #include "cpu/amd/model_10xxx/update_microcode.c" |
| 98 | #include "cpu/amd/model_10xxx/init_cpus.c" |
| 99 | |
| 100 | #include "northbridge/amd/amdfam10/early_ht.c" |
| 101 | |
Uwe Hermann | 26535d6 | 2010-11-20 20:36:40 +0000 | [diff] [blame^] | 102 | static const u8 spd_addr[] = { |
| 103 | // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr |
| 104 | //first node |
| 105 | RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 106 | #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
| 107 | //second node |
| 108 | RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, |
| 109 | #endif |
| 110 | }; |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 111 | |
| 112 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 113 | { |
| 114 | struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); |
| 115 | |
| 116 | |
| 117 | u32 bsp_apicid = 0; |
| 118 | u32 val; |
| 119 | msr_t msr; |
| 120 | |
| 121 | if (!cpu_init_detectedx && boot_cpu()) { |
| 122 | /* Nothing special needs to be done to find bus 0 */ |
| 123 | /* Allow the HT devices to be found */ |
| 124 | /* mov bsp to bus 0xff when > 8 nodes */ |
| 125 | set_bsp_node_CHtExtNodeCfgEn(); |
| 126 | enumerate_ht_chain(); |
| 127 | |
| 128 | /* Setup the rom access for 4M */ |
| 129 | bcm5785_enable_rom(); |
| 130 | bcm5785_enable_lpc(); |
| 131 | //enable RTC |
| 132 | pc87417_enable_dev(RTC_DEV); |
| 133 | } |
| 134 | |
| 135 | post_code(0x30); |
| 136 | |
| 137 | if (bist == 0) { |
| 138 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
| 139 | } |
| 140 | |
| 141 | pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 142 | |
| 143 | uart_init(); |
| 144 | |
| 145 | /* Halt if there was a built in self test failure */ |
| 146 | report_bist_failure(bist); |
| 147 | |
| 148 | console_init(); |
| 149 | pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV |
| 150 | |
| 151 | val = cpuid_eax(1); |
| 152 | printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); |
| 153 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
| 154 | printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); |
| 155 | printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); |
| 156 | |
| 157 | /* Setup sysinfo defaults */ |
| 158 | set_sysinfo_in_ram(0); |
| 159 | |
| 160 | update_microcode(val); |
| 161 | post_code(0x33); |
| 162 | |
| 163 | cpuSetAMDMSR(); |
| 164 | post_code(0x34); |
| 165 | |
| 166 | amd_ht_init(sysinfo); |
| 167 | post_code(0x35); |
| 168 | |
| 169 | /* Setup nodes PCI space and start core 0 AP init. */ |
| 170 | finalize_node_setup(sysinfo); |
| 171 | |
| 172 | post_code(0x36); |
| 173 | |
| 174 | /* wait for all the APs core0 started by finalize_node_setup. */ |
| 175 | /* FIXME: A bunch of cores are going to start output to serial at once. |
| 176 | * It would be nice to fixup prink spinlocks for ROM XIP mode. |
| 177 | * I think it could be done by putting the spinlock flag in the cache |
| 178 | * of the BSP located right after sysinfo. |
| 179 | */ |
| 180 | |
| 181 | wait_all_core0_started(); |
| 182 | |
| 183 | #if CONFIG_LOGICAL_CPUS==1 |
| 184 | /* Core0 on each node is configured. Now setup any additional cores. */ |
| 185 | printk(BIOS_DEBUG, "start_other_cores()\n"); |
| 186 | start_other_cores(); |
| 187 | post_code(0x37); |
| 188 | wait_all_other_cores_started(bsp_apicid); |
| 189 | #endif |
| 190 | |
Patrick Georgi | 76e8152 | 2010-11-16 21:25:29 +0000 | [diff] [blame] | 191 | #if CONFIG_SET_FIDVID |
Arne Georg Gleditsch | 9139e7b | 2010-09-24 17:35:32 +0000 | [diff] [blame] | 192 | msr = rdmsr(0xc0010071); |
| 193 | printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); |
| 194 | |
| 195 | /* FIXME: The sb fid change may survive the warm reset and only |
| 196 | * need to be done once.*/ |
| 197 | |
| 198 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 199 | |
| 200 | post_code(0x39); |
| 201 | |
| 202 | if (!warm_reset_detect(0)) { // BSP is node 0 |
| 203 | init_fidvid_bsp(bsp_apicid, sysinfo->nodes); |
| 204 | } else { |
| 205 | init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 |
| 206 | } |
| 207 | |
| 208 | post_code(0x3A); |
| 209 | |
| 210 | /* show final fid and vid */ |
| 211 | msr=rdmsr(0xc0010071); |
| 212 | printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); |
| 213 | #endif |
| 214 | |
| 215 | init_timer(); |
| 216 | |
| 217 | /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ |
| 218 | if (!warm_reset_detect(0)) { |
| 219 | print_info("...WARM RESET...\n\n\n"); |
| 220 | soft_reset(); |
| 221 | die("After soft_reset_x - shouldn't see this message!!!\n"); |
| 222 | } |
| 223 | |
| 224 | /* It's the time to set ctrl in sysinfo now; */ |
| 225 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 226 | enable_smbus(); |
| 227 | |
| 228 | //do we need apci timer, tsc...., only debug need it for better output |
| 229 | /* all ap stopped? */ |
| 230 | // init_timer(); // Need to use TMICT to synconize FID/VID |
| 231 | |
| 232 | printk(BIOS_DEBUG, "raminit_amdmct()\n"); |
| 233 | raminit_amdmct(sysinfo); |
| 234 | post_code(0x41); |
| 235 | |
| 236 | bcm5785_early_setup(); |
| 237 | |
| 238 | post_cache_as_ram(); |
| 239 | } |