Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2 | |
| 3 | #ifndef RAMINIT_COMMON_H |
| 4 | #define RAMINIT_COMMON_H |
| 5 | |
Felix Held | 380c6b2 | 2020-01-26 05:06:38 +0100 | [diff] [blame] | 6 | #include <stdint.h> |
| 7 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 8 | #define BASEFREQ 133 |
| 9 | #define tDLLK 512 |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 10 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 11 | #define NUM_CHANNELS 2 |
| 12 | #define NUM_SLOTRANKS 4 |
| 13 | #define NUM_SLOTS 2 |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 14 | #define NUM_LANES 9 |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 15 | |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 16 | /* IOSAV_n_SP_CMD_CTRL DRAM commands */ |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 17 | #define IOSAV_MRS (0xf000) |
| 18 | #define IOSAV_PRE (0xf002) |
| 19 | #define IOSAV_ZQCS (0xf003) |
| 20 | #define IOSAV_ACT (0xf006) |
| 21 | #define IOSAV_RD (0xf105) |
| 22 | #define IOSAV_NOP_ALT (0xf107) |
| 23 | #define IOSAV_WR (0xf201) |
| 24 | #define IOSAV_NOP (0xf207) |
Angel Pons | 69e1714 | 2020-03-23 12:26:29 +0100 | [diff] [blame] | 25 | |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 26 | /* IOSAV_n_SUBSEQ_CTRL data direction */ |
| 27 | #define SSQ_NA 0 /* Non-data */ |
| 28 | #define SSQ_RD 1 /* Read */ |
| 29 | #define SSQ_WR 2 /* Write */ |
| 30 | #define SSQ_RW 3 /* Read and write */ |
| 31 | |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 32 | struct iosav_ssq { |
| 33 | /* IOSAV_n_SP_CMD_CTRL */ |
| 34 | union { |
| 35 | struct { |
Angel Pons | 19c5cd2 | 2020-08-10 14:27:23 +0200 | [diff] [blame] | 36 | u32 command : 16; /* [15.. 0] */ |
| 37 | u32 ranksel_ap : 2; /* [17..16] */ |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 38 | u32 : 14; |
| 39 | }; |
| 40 | u32 raw; |
| 41 | } sp_cmd_ctrl; |
| 42 | |
| 43 | /* IOSAV_n_SUBSEQ_CTRL */ |
| 44 | union { |
| 45 | struct { |
Angel Pons | 19c5cd2 | 2020-08-10 14:27:23 +0200 | [diff] [blame] | 46 | u32 cmd_executions : 9; /* [ 8.. 0] */ |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 47 | u32 : 1; |
Angel Pons | 19c5cd2 | 2020-08-10 14:27:23 +0200 | [diff] [blame] | 48 | u32 cmd_delay_gap : 5; /* [14..10] */ |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 49 | u32 : 1; |
Angel Pons | 19c5cd2 | 2020-08-10 14:27:23 +0200 | [diff] [blame] | 50 | u32 post_ssq_wait : 9; /* [24..16] */ |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 51 | u32 : 1; |
Angel Pons | 19c5cd2 | 2020-08-10 14:27:23 +0200 | [diff] [blame] | 52 | u32 data_direction : 2; /* [27..26] */ |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 53 | u32 : 4; |
| 54 | }; |
| 55 | u32 raw; |
| 56 | } subseq_ctrl; |
| 57 | |
| 58 | /* IOSAV_n_SP_CMD_ADDR */ |
| 59 | union { |
| 60 | struct { |
Angel Pons | 19c5cd2 | 2020-08-10 14:27:23 +0200 | [diff] [blame] | 61 | u32 address : 16; /* [15.. 0] */ |
| 62 | u32 rowbits : 3; /* [18..16] */ |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 63 | u32 : 1; |
Angel Pons | 19c5cd2 | 2020-08-10 14:27:23 +0200 | [diff] [blame] | 64 | u32 bank : 3; /* [22..20] */ |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 65 | u32 : 1; |
Angel Pons | 19c5cd2 | 2020-08-10 14:27:23 +0200 | [diff] [blame] | 66 | u32 rank : 2; /* [25..24] */ |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 67 | u32 : 6; |
| 68 | }; |
| 69 | u32 raw; |
| 70 | } sp_cmd_addr; |
| 71 | |
| 72 | /* IOSAV_n_ADDR_UPDATE */ |
| 73 | union { |
| 74 | struct { |
Angel Pons | 19c5cd2 | 2020-08-10 14:27:23 +0200 | [diff] [blame] | 75 | u32 inc_addr_1 : 1; /* [ 0.. 0] */ |
| 76 | u32 inc_addr_8 : 1; /* [ 1.. 1] */ |
| 77 | u32 inc_bank : 1; /* [ 2.. 2] */ |
| 78 | u32 inc_rank : 2; /* [ 4.. 3] */ |
| 79 | u32 addr_wrap : 5; /* [ 9.. 5] */ |
| 80 | u32 lfsr_upd : 2; /* [11..10] */ |
| 81 | u32 upd_rate : 4; /* [15..12] */ |
| 82 | u32 lfsr_xors : 2; /* [17..16] */ |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 83 | u32 : 14; |
| 84 | }; |
| 85 | u32 raw; |
| 86 | } addr_update; |
| 87 | }; |
| 88 | |
Angel Pons | 9fcc110 | 2020-11-19 22:23:13 +0100 | [diff] [blame] | 89 | union gdcr_rx_reg { |
| 90 | struct { |
| 91 | u32 rcven_pi_code : 6; /* [ 5.. 0] */ |
| 92 | u32 : 2; |
| 93 | u32 rx_dqs_p_pi_code : 7; /* [14.. 8] */ |
| 94 | u32 : 1; |
| 95 | u32 rcven_logic_delay : 3; /* [18..16] */ |
| 96 | u32 : 1; |
| 97 | u32 rx_dqs_n_pi_code : 7; /* [26..20] */ |
| 98 | u32 : 5; |
| 99 | }; |
| 100 | u32 raw; |
| 101 | }; |
| 102 | |
| 103 | union gdcr_tx_reg { |
| 104 | struct { |
| 105 | u32 tx_dq_pi_code : 6; /* [ 5.. 0] */ |
| 106 | u32 : 2; |
| 107 | u32 tx_dqs_pi_code : 6; /* [13.. 8] */ |
| 108 | u32 : 1; |
| 109 | u32 tx_dqs_logic_delay : 3; /* [17..15] */ |
| 110 | u32 : 1; |
| 111 | u32 tx_dq_logic_delay : 1; /* [19..19] */ |
| 112 | u32 : 12; |
| 113 | }; |
| 114 | u32 raw; |
| 115 | }; |
| 116 | |
Angel Pons | 737f111 | 2020-11-13 14:07:30 +0100 | [diff] [blame] | 117 | union gdcr_cmd_pi_coding_reg { |
| 118 | struct { |
| 119 | u32 cmd_pi_code : 6; /* [ 5.. 0] */ |
| 120 | u32 ctl_pi_code_d0 : 6; /* [11.. 6] */ |
| 121 | u32 cmd_logic_delay : 1; /* [12..12] */ |
| 122 | u32 cmd_phase_delay : 1; /* [13..13] */ |
| 123 | u32 cmd_xover_enable : 1; /* [14..14] */ |
| 124 | u32 ctl_logic_delay_d0 : 1; /* [15..15] */ |
| 125 | u32 ctl_phase_delay_d0 : 1; /* [16..16] */ |
| 126 | u32 ctl_xover_enable_d0 : 1; /* [17..17] */ |
| 127 | u32 ctl_pi_code_d1 : 6; /* [23..18] */ |
| 128 | u32 ctl_logic_delay_d1 : 1; /* [24..24] */ |
| 129 | u32 ctl_phase_delay_d1 : 1; /* [25..25] */ |
| 130 | u32 ctl_xover_enable_d1 : 1; /* [26..26] */ |
| 131 | u32 : 5; |
| 132 | }; |
| 133 | u32 raw; |
| 134 | }; |
| 135 | |
Angel Pons | 58b609b | 2020-11-13 14:35:29 +0100 | [diff] [blame] | 136 | union gdcr_training_mod_reg { |
| 137 | struct { |
| 138 | u32 receive_enable_mode : 1; /* [ 0.. 0] */ |
| 139 | u32 write_leveling_mode : 1; /* [ 1.. 1] */ |
| 140 | u32 training_rank_sel : 2; /* [ 3.. 2] */ |
| 141 | u32 enable_dqs_wl : 4; /* [ 7.. 4] */ |
| 142 | u32 dqs_logic_delay_wl : 1; /* [ 8.. 8] */ |
| 143 | u32 dq_dqs_training_res : 1; /* [ 9.. 9] */ |
| 144 | u32 : 4; |
| 145 | u32 delay_dq : 1; /* [14..14] */ |
| 146 | u32 odt_always_on : 1; /* [15..15] */ |
| 147 | u32 : 4; |
| 148 | u32 force_drive_enable : 1; /* [20..20] */ |
| 149 | u32 dft_tx_pi_clk_view : 1; /* [21..21] */ |
| 150 | u32 dft_tx_pi_clk_swap : 1; /* [22..22] */ |
| 151 | u32 early_odt_en : 1; /* [23..23] */ |
| 152 | u32 vref_gen_ctl : 6; /* [29..24] */ |
| 153 | u32 ext_vref_sel : 1; /* [30..30] */ |
| 154 | u32 tx_fifo_always_on : 1; /* [31..31] */ |
| 155 | }; |
| 156 | u32 raw; |
| 157 | }; |
| 158 | |
Angel Pons | 4f86d63 | 2020-11-19 17:18:46 +0100 | [diff] [blame] | 159 | union comp_ofst_1_reg { |
| 160 | struct { |
| 161 | u32 dq_odt_down : 3; /* [ 2.. 0] */ |
| 162 | u32 dq_odt_up : 3; /* [ 5.. 3] */ |
| 163 | u32 clk_odt_down : 3; /* [ 8.. 6] */ |
| 164 | u32 clk_odt_up : 3; /* [11.. 9] */ |
| 165 | u32 dq_drv_down : 3; /* [14..12] */ |
| 166 | u32 dq_drv_up : 3; /* [17..15] */ |
| 167 | u32 clk_drv_down : 3; /* [20..18] */ |
| 168 | u32 clk_drv_up : 3; /* [23..21] */ |
| 169 | u32 ctl_drv_down : 3; /* [26..24] */ |
| 170 | u32 ctl_drv_up : 3; /* [29..27] */ |
| 171 | u32 : 2; |
| 172 | }; |
| 173 | u32 raw; |
| 174 | }; |
| 175 | |
Angel Pons | 7a61274 | 2020-11-12 13:34:03 +0100 | [diff] [blame] | 176 | union tc_dbp_reg { |
| 177 | struct { |
| 178 | u32 tRCD : 4; /* [ 3.. 0] */ |
| 179 | u32 tRP : 4; /* [ 7.. 4] */ |
| 180 | u32 tAA : 4; /* [11.. 8] */ |
| 181 | u32 tCWL : 4; /* [15..12] */ |
| 182 | u32 tRAS : 8; /* [23..16] */ |
| 183 | u32 : 8; |
| 184 | }; |
| 185 | u32 raw; |
| 186 | }; |
| 187 | |
| 188 | union tc_rap_reg { |
| 189 | struct { |
| 190 | u32 tRRD : 4; /* [ 3.. 0] */ |
| 191 | u32 tRTP : 4; /* [ 7.. 4] */ |
| 192 | u32 tCKE : 4; /* [11.. 8] */ |
| 193 | u32 tWTR : 4; /* [15..12] */ |
| 194 | u32 tFAW : 8; /* [23..16] */ |
| 195 | u32 tWR : 5; /* [28..24] */ |
| 196 | u32 dis_3st : 1; /* [29..29] */ |
| 197 | u32 tCMD : 2; /* [31..30] */ |
| 198 | }; |
| 199 | u32 raw; |
| 200 | }; |
| 201 | |
| 202 | union tc_rwp_reg { |
| 203 | struct { |
| 204 | u32 tRRDR : 3; /* [ 2.. 0] */ |
| 205 | u32 : 1; |
| 206 | u32 tRRDD : 3; /* [ 6.. 4] */ |
| 207 | u32 : 1; |
| 208 | u32 tWWDR : 3; /* [10.. 8] */ |
| 209 | u32 : 1; |
| 210 | u32 tWWDD : 3; /* [14..12] */ |
| 211 | u32 : 1; |
| 212 | u32 tRWDRDD : 3; /* [18..16] */ |
| 213 | u32 : 1; |
| 214 | u32 tWRDRDD : 3; /* [22..20] */ |
| 215 | u32 : 1; |
| 216 | u32 tRWSR : 3; /* [26..24] */ |
| 217 | u32 dec_wrd : 1; /* [27..27] */ |
| 218 | u32 : 4; |
| 219 | }; |
| 220 | u32 raw; |
| 221 | }; |
| 222 | |
| 223 | union tc_othp_reg { |
| 224 | struct { |
| 225 | u32 tXPDLL : 5; /* [ 4.. 0] */ |
| 226 | u32 tXP : 3; /* [ 7.. 5] */ |
| 227 | u32 tAONPD : 4; /* [11.. 8] */ |
| 228 | u32 tCPDED : 2; /* [13..12] */ |
| 229 | u32 tPRPDEN : 2; /* [15..14] */ |
| 230 | u32 odt_delay_d0 : 2; /* [17..16] */ |
| 231 | u32 odt_delay_d1 : 2; /* [19..18] */ |
| 232 | u32 : 12; |
| 233 | }; |
| 234 | u32 raw; |
| 235 | }; |
| 236 | |
| 237 | union tc_dtp_reg { |
| 238 | struct { |
| 239 | u32 : 12; |
| 240 | u32 overclock_tXP : 1; /* [12..12] */ |
| 241 | u32 overclock_tXPDLL : 1; /* [13..13] */ |
| 242 | u32 : 18; |
| 243 | }; |
| 244 | u32 raw; |
| 245 | }; |
| 246 | |
| 247 | union tc_rfp_reg { |
| 248 | struct { |
| 249 | u32 oref_ri : 8; /* [ 7.. 0] */ |
| 250 | u32 refresh_high_wm : 4; /* [11.. 8] */ |
| 251 | u32 refresh_panic_wm : 4; /* [15..12] */ |
| 252 | u32 refresh_2x_control : 2; /* [17..16] */ |
| 253 | u32 : 14; |
| 254 | }; |
| 255 | u32 raw; |
| 256 | }; |
| 257 | |
| 258 | union tc_rftp_reg { |
| 259 | struct { |
| 260 | u32 tREFI : 16; /* [15.. 0] */ |
| 261 | u32 tRFC : 9; /* [24..16] */ |
| 262 | u32 tREFIx9 : 7; /* [31..25] */ |
| 263 | }; |
| 264 | u32 raw; |
| 265 | }; |
| 266 | |
| 267 | union tc_srftp_reg { |
| 268 | struct { |
| 269 | u32 tXSDLL : 12; /* [11.. 0] */ |
| 270 | u32 tXS_offset : 4; /* [15..12] */ |
| 271 | u32 tZQOPER : 10; /* [25..16] */ |
| 272 | u32 : 2; |
| 273 | u32 tMOD : 4; /* [31..28] */ |
| 274 | }; |
| 275 | u32 raw; |
| 276 | }; |
| 277 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 278 | typedef struct ramctr_timing_st ramctr_timing; |
| 279 | |
Angel Pons | 8f0757e | 2020-11-11 23:03:36 +0100 | [diff] [blame] | 280 | void iosav_write_sequence(const int ch, const struct iosav_ssq *seq, const unsigned int length); |
Angel Pons | 1c505f8 | 2020-11-11 20:55:35 +0100 | [diff] [blame] | 281 | void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer); |
Angel Pons | 1c505f8 | 2020-11-11 20:55:35 +0100 | [diff] [blame] | 282 | void wait_for_iosav(int channel); |
Angel Pons | a853e7a | 2020-12-07 12:28:38 +0100 | [diff] [blame] | 283 | void iosav_run_once_and_wait(const int ch); |
Angel Pons | 1c505f8 | 2020-11-11 20:55:35 +0100 | [diff] [blame] | 284 | |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 285 | void iosav_write_zqcs_sequence(int channel, int slotrank, u32 gap, u32 post, u32 wrap); |
| 286 | void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap); |
| 287 | void iosav_write_read_mpr_sequence( |
| 288 | int channel, int slotrank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2); |
Angel Pons | 801a5cb | 2020-11-15 15:48:29 +0100 | [diff] [blame] | 289 | void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int slotrank); |
Angel Pons | 9426721 | 2020-11-14 16:49:29 +0100 | [diff] [blame] | 290 | void iosav_write_jedec_write_leveling_sequence( |
| 291 | ramctr_timing *ctrl, int channel, int slotrank, int bank, u32 mr1reg); |
Angel Pons | ffd5015 | 2020-11-12 11:03:10 +0100 | [diff] [blame] | 292 | void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, |
| 293 | u32 gap0, u32 loops0, u32 gap1, u32 loops2, u32 wrap2); |
| 294 | void iosav_write_command_training_sequence( |
| 295 | ramctr_timing *ctrl, int channel, int slotrank, unsigned int address); |
| 296 | void iosav_write_data_write_sequence(ramctr_timing *ctrl, int channel, int slotrank); |
| 297 | void iosav_write_aggressive_write_read_sequence(ramctr_timing *ctrl, int channel, int slotrank); |
| 298 | void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int slotrank); |
| 299 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 300 | /* FIXME: Vendor BIOS uses 64 but our algorithms are less |
| 301 | performant and even 1 seems to be enough in practice. */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 302 | #define NUM_PATTERNS 4 |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 303 | |
Angel Pons | 5c1baf5 | 2020-03-22 12:23:35 +0100 | [diff] [blame] | 304 | /* |
| 305 | * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed! |
| 306 | */ |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 307 | #define MRC_CACHE_VERSION 5 |
Angel Pons | 5c1baf5 | 2020-03-22 12:23:35 +0100 | [diff] [blame] | 308 | |
Angel Pons | 09fc4b9 | 2020-11-19 12:02:07 +0100 | [diff] [blame] | 309 | enum pdwm_mode { |
| 310 | PDM_NONE = 0, |
| 311 | PDM_APD = 1, |
| 312 | PDM_PPD = 2, |
| 313 | PDM_APD_PPD = 3, |
| 314 | PDM_DLL_OFF = 6, |
| 315 | PDM_APD_DLL_OFF = 7, |
| 316 | }; |
| 317 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 318 | typedef struct odtmap_st { |
| 319 | u16 rttwr; |
| 320 | u16 rttnom; |
| 321 | } odtmap; |
| 322 | |
Angel Pons | 5c1baf5 | 2020-03-22 12:23:35 +0100 | [diff] [blame] | 323 | /* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 324 | typedef struct dimm_info_st { |
| 325 | dimm_attr dimm[NUM_CHANNELS][NUM_SLOTS]; |
| 326 | } dimm_info; |
| 327 | |
Angel Pons | 5c1baf5 | 2020-03-22 12:23:35 +0100 | [diff] [blame] | 328 | /* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 329 | struct ram_rank_timings { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 330 | /* ROUNDT_LAT register: One byte per slotrank */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 331 | u8 roundtrip_latency; |
| 332 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 333 | /* IO_LATENCY register: One nibble per slotrank */ |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 334 | u8 io_latency; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 335 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 336 | /* Phase interpolator coding for command and control */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 337 | int pi_coding; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 338 | |
| 339 | struct ram_lane_timings { |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 340 | /* GDCR RX timings */ |
| 341 | u16 rcven; |
| 342 | u8 rx_dqs_p; |
| 343 | u8 rx_dqs_n; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 344 | |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 345 | /* GDCR TX timings */ |
| 346 | int tx_dq; |
| 347 | u16 tx_dqs; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 348 | } lanes[NUM_LANES]; |
| 349 | }; |
| 350 | |
Angel Pons | 5c1baf5 | 2020-03-22 12:23:35 +0100 | [diff] [blame] | 351 | /* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 352 | typedef struct ramctr_timing_st { |
| 353 | u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; |
Angel Pons | 80037f7 | 2020-03-21 13:12:37 +0100 | [diff] [blame] | 354 | |
| 355 | /* CPUID value */ |
| 356 | u32 cpu; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 357 | |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 358 | /* DDR base_freq = 100 Mhz / 133 Mhz */ |
| 359 | u8 base_freq; |
| 360 | |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 361 | /* Frequency index */ |
| 362 | u32 FRQ; |
| 363 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 364 | u16 cas_supported; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 365 | /* Latencies are in units of ns, scaled by x256 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 366 | u32 tCK; |
| 367 | u32 tAA; |
| 368 | u32 tWR; |
| 369 | u32 tRCD; |
| 370 | u32 tRRD; |
| 371 | u32 tRP; |
| 372 | u32 tRAS; |
| 373 | u32 tRFC; |
| 374 | u32 tWTR; |
| 375 | u32 tRTP; |
| 376 | u32 tFAW; |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 377 | u32 tCWL; |
| 378 | u32 tCMD; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 379 | /* Latencies in terms of clock cycles |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 380 | They are saved separately as they are needed for DRAM MRS commands */ |
| 381 | u8 CAS; /* CAS read latency */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 382 | u8 CWL; /* CAS write latency */ |
| 383 | |
| 384 | u32 tREFI; |
| 385 | u32 tMOD; |
| 386 | u32 tXSOffset; |
| 387 | u32 tWLO; |
| 388 | u32 tCKE; |
| 389 | u32 tXPDLL; |
| 390 | u32 tXP; |
| 391 | u32 tAONPD; |
| 392 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 393 | /* Bits [0..11] of PM_DLL_CONFIG: Master DLL wakeup delay timer */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 394 | u16 mdll_wake_delay; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 395 | |
| 396 | u8 rankmap[NUM_CHANNELS]; |
| 397 | int ref_card_offset[NUM_CHANNELS]; |
| 398 | u32 mad_dimm[NUM_CHANNELS]; |
| 399 | int channel_size_mb[NUM_CHANNELS]; |
| 400 | u32 cmd_stretch[NUM_CHANNELS]; |
| 401 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 402 | int pi_code_offset; |
| 403 | int pi_coding_threshold; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 404 | |
Patrick Rudolph | 05d4bf7e | 2017-10-28 16:36:09 +0200 | [diff] [blame] | 405 | bool ecc_supported; |
| 406 | bool ecc_forced; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 407 | bool ecc_enabled; |
| 408 | int lanes; /* active lanes: 8 or 9 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 409 | int edge_offset[3]; |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 410 | int tx_dq_offset[3]; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 411 | |
| 412 | int extended_temperature_range; |
| 413 | int auto_self_refresh; |
| 414 | |
| 415 | int rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS]; |
| 416 | |
| 417 | struct ram_rank_timings timings[NUM_CHANNELS][NUM_SLOTRANKS]; |
| 418 | |
| 419 | dimm_info info; |
| 420 | } ramctr_timing; |
| 421 | |
Felix Held | 87ddea2 | 2020-01-26 04:55:27 +0100 | [diff] [blame] | 422 | #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) |
| 423 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 424 | #define FOR_ALL_LANES for (lane = 0; lane < ctrl->lanes; lane++) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 425 | #define FOR_ALL_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++) |
| 426 | #define FOR_ALL_POPULATED_RANKS for (slotrank = 0; slotrank < NUM_SLOTRANKS; slotrank++) if (ctrl->rankmap[channel] & (1 << slotrank)) |
| 427 | #define FOR_ALL_POPULATED_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++) if (ctrl->rankmap[channel]) |
| 428 | #define MAX_EDGE_TIMING 71 |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 429 | #define MAX_TX_DQ 127 |
| 430 | #define MAX_TX_DQS 511 |
| 431 | #define MAX_RCVEN 127 |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 432 | #define MAX_CAS 18 |
| 433 | #define MIN_CAS 4 |
| 434 | |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 435 | /* |
Angel Pons | ec38570 | 2021-01-12 21:08:27 +0100 | [diff] [blame] | 436 | * 1 QCLK (quadrature clock) is one half of a full clock cycle (tCK). |
| 437 | * In addition, 64 PI (phase interpolator) ticks are equal to 1 QCLK. |
Angel Pons | 42d033a | 2021-01-03 15:26:37 +0100 | [diff] [blame] | 438 | * Logic delay values in I/O register bitfields are expressed in QCLKs. |
| 439 | */ |
| 440 | #define QCLK_PI 64 |
| 441 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 442 | #define MAKE_ERR ((channel << 16) | (slotrank << 8) | 1) |
| 443 | #define GET_ERR_CHANNEL(x) (x >> 16) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 444 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 445 | void dram_mrscommands(ramctr_timing *ctrl); |
| 446 | void program_timings(ramctr_timing *ctrl, int channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 447 | void dram_find_common_params(ramctr_timing *ctrl); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 448 | void dram_xover(ramctr_timing *ctrl); |
| 449 | void dram_timing_regs(ramctr_timing *ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 450 | void dram_dimm_mapping(ramctr_timing *ctrl); |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 451 | void dram_dimm_set_mapping(ramctr_timing *ctrl, int training); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 452 | void dram_zones(ramctr_timing *ctrl, int training); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 453 | void dram_memorymap(ramctr_timing *ctrl, int me_uma_size); |
| 454 | void dram_jedecreset(ramctr_timing *ctrl); |
Angel Pons | 7f5a97c | 2020-11-13 16:58:46 +0100 | [diff] [blame] | 455 | int receive_enable_calibration(ramctr_timing *ctrl); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 456 | int write_training(ramctr_timing *ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 457 | int command_training(ramctr_timing *ctrl); |
Angel Pons | 4c79f93 | 2020-11-14 01:26:52 +0100 | [diff] [blame] | 458 | int read_mpr_training(ramctr_timing *ctrl); |
Angel Pons | 08f749d | 2020-11-17 16:50:56 +0100 | [diff] [blame] | 459 | int aggressive_read_training(ramctr_timing *ctrl); |
Angel Pons | 2a7d752 | 2020-11-19 12:49:07 +0100 | [diff] [blame] | 460 | int aggressive_write_training(ramctr_timing *ctrl); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 461 | void normalize_training(ramctr_timing *ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 462 | int channel_test(ramctr_timing *ctrl); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 463 | void set_scrambling_seed(ramctr_timing *ctrl); |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 464 | void set_wmm_behavior(const u32 cpu); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 465 | void prepare_training(ramctr_timing *ctrl); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 466 | void set_read_write_timings(ramctr_timing *ctrl); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 467 | void set_normal_operation(ramctr_timing *ctrl); |
| 468 | void final_registers(ramctr_timing *ctrl); |
| 469 | void restore_timings(ramctr_timing *ctrl); |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 470 | int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 471 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 472 | void channel_scrub(ramctr_timing *ctrl); |
Patrick Rudolph | 05d4bf7e | 2017-10-28 16:36:09 +0200 | [diff] [blame] | 473 | bool get_host_ecc_cap(void); |
| 474 | bool get_host_ecc_forced(void); |
| 475 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 476 | #endif |