Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 2 | |
| 3 | #ifndef RAMINIT_COMMON_H |
| 4 | #define RAMINIT_COMMON_H |
| 5 | |
Felix Held | 380c6b2 | 2020-01-26 05:06:38 +0100 | [diff] [blame] | 6 | #include <stdint.h> |
| 7 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 8 | #define BASEFREQ 133 |
| 9 | #define tDLLK 512 |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 10 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 11 | #define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0) |
| 12 | #define IS_SANDY_CPU_C(x) ((x & 0xf) == 4) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 13 | #define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5) |
| 14 | #define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6) |
| 15 | #define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7) |
| 16 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 17 | #define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 18 | #define IS_IVY_CPU_C(x) ((x & 0xf) == 4) |
| 19 | #define IS_IVY_CPU_K(x) ((x & 0xf) == 5) |
| 20 | #define IS_IVY_CPU_D(x) ((x & 0xf) == 6) |
| 21 | #define IS_IVY_CPU_E(x) ((x & 0xf) >= 8) |
| 22 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 23 | #define NUM_CHANNELS 2 |
| 24 | #define NUM_SLOTRANKS 4 |
| 25 | #define NUM_SLOTS 2 |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 26 | #define NUM_LANES 9 |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 27 | |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 28 | /* IOSAV_n_SP_CMD_CTRL DRAM commands */ |
Angel Pons | 6aa7cca | 2020-05-02 19:38:34 +0200 | [diff] [blame] | 29 | #define IOSAV_MRS (0xf000) |
| 30 | #define IOSAV_PRE (0xf002) |
| 31 | #define IOSAV_ZQCS (0xf003) |
| 32 | #define IOSAV_ACT (0xf006) |
| 33 | #define IOSAV_RD (0xf105) |
| 34 | #define IOSAV_NOP_ALT (0xf107) |
| 35 | #define IOSAV_WR (0xf201) |
| 36 | #define IOSAV_NOP (0xf207) |
Angel Pons | 69e1714 | 2020-03-23 12:26:29 +0100 | [diff] [blame] | 37 | |
Angel Pons | 3abd206 | 2020-05-03 00:25:02 +0200 | [diff] [blame] | 38 | /* IOSAV_n_SUBSEQ_CTRL data direction */ |
| 39 | #define SSQ_NA 0 /* Non-data */ |
| 40 | #define SSQ_RD 1 /* Read */ |
| 41 | #define SSQ_WR 2 /* Write */ |
| 42 | #define SSQ_RW 3 /* Read and write */ |
| 43 | |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 44 | struct iosav_ssq { |
| 45 | /* IOSAV_n_SP_CMD_CTRL */ |
| 46 | union { |
| 47 | struct { |
Angel Pons | 19c5cd2 | 2020-08-10 14:27:23 +0200 | [diff] [blame] | 48 | u32 command : 16; /* [15.. 0] */ |
| 49 | u32 ranksel_ap : 2; /* [17..16] */ |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 50 | u32 : 14; |
| 51 | }; |
| 52 | u32 raw; |
| 53 | } sp_cmd_ctrl; |
| 54 | |
| 55 | /* IOSAV_n_SUBSEQ_CTRL */ |
| 56 | union { |
| 57 | struct { |
Angel Pons | 19c5cd2 | 2020-08-10 14:27:23 +0200 | [diff] [blame] | 58 | u32 cmd_executions : 9; /* [ 8.. 0] */ |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 59 | u32 : 1; |
Angel Pons | 19c5cd2 | 2020-08-10 14:27:23 +0200 | [diff] [blame] | 60 | u32 cmd_delay_gap : 5; /* [14..10] */ |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 61 | u32 : 1; |
Angel Pons | 19c5cd2 | 2020-08-10 14:27:23 +0200 | [diff] [blame] | 62 | u32 post_ssq_wait : 9; /* [24..16] */ |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 63 | u32 : 1; |
Angel Pons | 19c5cd2 | 2020-08-10 14:27:23 +0200 | [diff] [blame] | 64 | u32 data_direction : 2; /* [27..26] */ |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 65 | u32 : 4; |
| 66 | }; |
| 67 | u32 raw; |
| 68 | } subseq_ctrl; |
| 69 | |
| 70 | /* IOSAV_n_SP_CMD_ADDR */ |
| 71 | union { |
| 72 | struct { |
Angel Pons | 19c5cd2 | 2020-08-10 14:27:23 +0200 | [diff] [blame] | 73 | u32 address : 16; /* [15.. 0] */ |
| 74 | u32 rowbits : 3; /* [18..16] */ |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 75 | u32 : 1; |
Angel Pons | 19c5cd2 | 2020-08-10 14:27:23 +0200 | [diff] [blame] | 76 | u32 bank : 3; /* [22..20] */ |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 77 | u32 : 1; |
Angel Pons | 19c5cd2 | 2020-08-10 14:27:23 +0200 | [diff] [blame] | 78 | u32 rank : 2; /* [25..24] */ |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 79 | u32 : 6; |
| 80 | }; |
| 81 | u32 raw; |
| 82 | } sp_cmd_addr; |
| 83 | |
| 84 | /* IOSAV_n_ADDR_UPDATE */ |
| 85 | union { |
| 86 | struct { |
Angel Pons | 19c5cd2 | 2020-08-10 14:27:23 +0200 | [diff] [blame] | 87 | u32 inc_addr_1 : 1; /* [ 0.. 0] */ |
| 88 | u32 inc_addr_8 : 1; /* [ 1.. 1] */ |
| 89 | u32 inc_bank : 1; /* [ 2.. 2] */ |
| 90 | u32 inc_rank : 2; /* [ 4.. 3] */ |
| 91 | u32 addr_wrap : 5; /* [ 9.. 5] */ |
| 92 | u32 lfsr_upd : 2; /* [11..10] */ |
| 93 | u32 upd_rate : 4; /* [15..12] */ |
| 94 | u32 lfsr_xors : 2; /* [17..16] */ |
Angel Pons | d5b780c | 2020-05-02 21:48:46 +0200 | [diff] [blame] | 95 | u32 : 14; |
| 96 | }; |
| 97 | u32 raw; |
| 98 | } addr_update; |
| 99 | }; |
| 100 | |
Angel Pons | 1c505f8 | 2020-11-11 20:55:35 +0100 | [diff] [blame^] | 101 | void iosav_write_ssq(const int ch, const struct iosav_ssq *ssq); |
| 102 | void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer); |
| 103 | void iosav_run_once(const int ch); |
| 104 | void wait_for_iosav(int channel); |
| 105 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 106 | /* FIXME: Vendor BIOS uses 64 but our algorithms are less |
| 107 | performant and even 1 seems to be enough in practice. */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 108 | #define NUM_PATTERNS 4 |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 109 | |
Angel Pons | 5c1baf5 | 2020-03-22 12:23:35 +0100 | [diff] [blame] | 110 | /* |
| 111 | * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed! |
| 112 | */ |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 113 | #define MRC_CACHE_VERSION 5 |
Angel Pons | 5c1baf5 | 2020-03-22 12:23:35 +0100 | [diff] [blame] | 114 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 115 | typedef struct odtmap_st { |
| 116 | u16 rttwr; |
| 117 | u16 rttnom; |
| 118 | } odtmap; |
| 119 | |
Angel Pons | 5c1baf5 | 2020-03-22 12:23:35 +0100 | [diff] [blame] | 120 | /* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 121 | typedef struct dimm_info_st { |
| 122 | dimm_attr dimm[NUM_CHANNELS][NUM_SLOTS]; |
| 123 | } dimm_info; |
| 124 | |
Angel Pons | 5c1baf5 | 2020-03-22 12:23:35 +0100 | [diff] [blame] | 125 | /* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 126 | struct ram_rank_timings { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 127 | /* ROUNDT_LAT register: One byte per slotrank */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 128 | u8 roundtrip_latency; |
| 129 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 130 | /* IO_LATENCY register: One nibble per slotrank */ |
Felix Held | ef4fe3e | 2019-12-31 14:15:05 +0100 | [diff] [blame] | 131 | u8 io_latency; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 132 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 133 | /* Phase interpolator coding for command and control */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 134 | int pi_coding; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 135 | |
| 136 | struct ram_lane_timings { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 137 | /* Lane register offset 0x10 */ |
| 138 | u16 timA; /* bits 0 - 5, bits 16 - 18 */ |
| 139 | u8 rising; /* bits 8 - 14 */ |
| 140 | u8 falling; /* bits 20 - 26 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 141 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 142 | /* Lane register offset 0x20 */ |
| 143 | int timC; /* bits 0 - 5, 19 */ |
| 144 | u16 timB; /* bits 8 - 13, 15 - 17 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 145 | } lanes[NUM_LANES]; |
| 146 | }; |
| 147 | |
Angel Pons | 5c1baf5 | 2020-03-22 12:23:35 +0100 | [diff] [blame] | 148 | /* WARNING: Do not forget to increase MRC_CACHE_VERSION when this struct is changed! */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 149 | typedef struct ramctr_timing_st { |
| 150 | u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; |
Angel Pons | 80037f7 | 2020-03-21 13:12:37 +0100 | [diff] [blame] | 151 | |
| 152 | /* CPUID value */ |
| 153 | u32 cpu; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 154 | |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 155 | /* DDR base_freq = 100 Mhz / 133 Mhz */ |
| 156 | u8 base_freq; |
| 157 | |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 158 | /* Frequency index */ |
| 159 | u32 FRQ; |
| 160 | |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 161 | u16 cas_supported; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 162 | /* Latencies are in units of ns, scaled by x256 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 163 | u32 tCK; |
| 164 | u32 tAA; |
| 165 | u32 tWR; |
| 166 | u32 tRCD; |
| 167 | u32 tRRD; |
| 168 | u32 tRP; |
| 169 | u32 tRAS; |
| 170 | u32 tRFC; |
| 171 | u32 tWTR; |
| 172 | u32 tRTP; |
| 173 | u32 tFAW; |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 174 | u32 tCWL; |
| 175 | u32 tCMD; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 176 | /* Latencies in terms of clock cycles |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 177 | They are saved separately as they are needed for DRAM MRS commands */ |
| 178 | u8 CAS; /* CAS read latency */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 179 | u8 CWL; /* CAS write latency */ |
| 180 | |
| 181 | u32 tREFI; |
| 182 | u32 tMOD; |
| 183 | u32 tXSOffset; |
| 184 | u32 tWLO; |
| 185 | u32 tCKE; |
| 186 | u32 tXPDLL; |
| 187 | u32 tXP; |
| 188 | u32 tAONPD; |
| 189 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 190 | /* Bits [0..11] of PM_DLL_CONFIG: Master DLL wakeup delay timer */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 191 | u16 mdll_wake_delay; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 192 | |
| 193 | u8 rankmap[NUM_CHANNELS]; |
| 194 | int ref_card_offset[NUM_CHANNELS]; |
| 195 | u32 mad_dimm[NUM_CHANNELS]; |
| 196 | int channel_size_mb[NUM_CHANNELS]; |
| 197 | u32 cmd_stretch[NUM_CHANNELS]; |
| 198 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 199 | int pi_code_offset; |
| 200 | int pi_coding_threshold; |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 201 | |
Patrick Rudolph | 05d4bf7e | 2017-10-28 16:36:09 +0200 | [diff] [blame] | 202 | bool ecc_supported; |
| 203 | bool ecc_forced; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 204 | bool ecc_enabled; |
| 205 | int lanes; /* active lanes: 8 or 9 */ |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 206 | int edge_offset[3]; |
| 207 | int timC_offset[3]; |
| 208 | |
| 209 | int extended_temperature_range; |
| 210 | int auto_self_refresh; |
| 211 | |
| 212 | int rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS]; |
| 213 | |
| 214 | struct ram_rank_timings timings[NUM_CHANNELS][NUM_SLOTRANKS]; |
| 215 | |
| 216 | dimm_info info; |
| 217 | } ramctr_timing; |
| 218 | |
Felix Held | 87ddea2 | 2020-01-26 04:55:27 +0100 | [diff] [blame] | 219 | #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) |
| 220 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 221 | #define FOR_ALL_LANES for (lane = 0; lane < ctrl->lanes; lane++) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 222 | #define FOR_ALL_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++) |
| 223 | #define FOR_ALL_POPULATED_RANKS for (slotrank = 0; slotrank < NUM_SLOTRANKS; slotrank++) if (ctrl->rankmap[channel] & (1 << slotrank)) |
| 224 | #define FOR_ALL_POPULATED_CHANNELS for (channel = 0; channel < NUM_CHANNELS; channel++) if (ctrl->rankmap[channel]) |
| 225 | #define MAX_EDGE_TIMING 71 |
| 226 | #define MAX_TIMC 127 |
| 227 | #define MAX_TIMB 511 |
| 228 | #define MAX_TIMA 127 |
| 229 | #define MAX_CAS 18 |
| 230 | #define MIN_CAS 4 |
| 231 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 232 | #define MAKE_ERR ((channel << 16) | (slotrank << 8) | 1) |
| 233 | #define GET_ERR_CHANNEL(x) (x >> 16) |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 234 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 235 | void dram_mrscommands(ramctr_timing *ctrl); |
| 236 | void program_timings(ramctr_timing *ctrl, int channel); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 237 | void dram_find_common_params(ramctr_timing *ctrl); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 238 | void dram_xover(ramctr_timing *ctrl); |
| 239 | void dram_timing_regs(ramctr_timing *ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 240 | void dram_dimm_mapping(ramctr_timing *ctrl); |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 241 | void dram_dimm_set_mapping(ramctr_timing *ctrl, int training); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 242 | void dram_zones(ramctr_timing *ctrl, int training); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 243 | void dram_memorymap(ramctr_timing *ctrl, int me_uma_size); |
| 244 | void dram_jedecreset(ramctr_timing *ctrl); |
| 245 | int read_training(ramctr_timing *ctrl); |
| 246 | int write_training(ramctr_timing *ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 247 | int command_training(ramctr_timing *ctrl); |
| 248 | int discover_edges(ramctr_timing *ctrl); |
| 249 | int discover_edges_write(ramctr_timing *ctrl); |
| 250 | int discover_timC_write(ramctr_timing *ctrl); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 251 | void normalize_training(ramctr_timing *ctrl); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 252 | int channel_test(ramctr_timing *ctrl); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 253 | void set_scrambling_seed(ramctr_timing *ctrl); |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 254 | void set_wmm_behavior(const u32 cpu); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 255 | void prepare_training(ramctr_timing *ctrl); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 256 | void set_read_write_timings(ramctr_timing *ctrl); |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 257 | void set_normal_operation(ramctr_timing *ctrl); |
| 258 | void final_registers(ramctr_timing *ctrl); |
| 259 | void restore_timings(ramctr_timing *ctrl); |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 260 | int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size); |
Patrick Rudolph | fd5fa2a | 2016-11-11 18:22:33 +0100 | [diff] [blame] | 261 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 262 | void channel_scrub(ramctr_timing *ctrl); |
Patrick Rudolph | 05d4bf7e | 2017-10-28 16:36:09 +0200 | [diff] [blame] | 263 | bool get_host_ecc_cap(void); |
| 264 | bool get_host_ecc_forced(void); |
| 265 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 266 | #endif |