Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 2 | |
Felix Held | 972d9f2 | 2022-02-23 16:32:20 +0100 | [diff] [blame] | 3 | #include <arch/hpet.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <console/usb.h> |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 6 | #include <cf9_reset.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 7 | #include <string.h> |
Nico Huber | 47bf498 | 2019-11-17 02:58:00 +0100 | [diff] [blame] | 8 | #include <device/device.h> |
Elyes HAOUAS | 921b99e | 2022-01-26 08:01:08 +0100 | [diff] [blame] | 9 | #include <device/dram/ddr3.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 10 | #include <device/pci_ops.h> |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 11 | #include <arch/cpu.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 12 | #include <cbmem.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 13 | #include <cbfs.h> |
| 14 | #include <ip_checksum.h> |
| 15 | #include <pc80/mc146818rtc.h> |
| 16 | #include <device/pci_def.h> |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 17 | #include <lib.h> |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 18 | #include <mrc_cache.h> |
Elyes HAOUAS | a233eb4 | 2022-01-26 07:51:28 +0100 | [diff] [blame] | 19 | #include <spd.h> |
Elyes HAOUAS | 62b23c1 | 2022-01-26 07:43:51 +0100 | [diff] [blame] | 20 | #include <smbios.h> |
Elyes HAOUAS | 1d6484a | 2020-07-10 11:18:11 +0200 | [diff] [blame] | 21 | #include <stddef.h> |
| 22 | #include <stdint.h> |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 23 | #include <timestamp.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 24 | #include "raminit.h" |
| 25 | #include "pei_data.h" |
| 26 | #include "sandybridge.h" |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 27 | #include "chip.h" |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 28 | #include <security/vboot/vboot_common.h> |
Patrick Georgi | 27fbbcf | 2019-04-23 12:33:23 +0200 | [diff] [blame] | 29 | #include <southbridge/intel/bd82x6x/pch.h> |
Matt DeVillier | ff1ef8d | 2016-12-24 15:36:24 -0600 | [diff] [blame] | 30 | #include <memory_info.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 31 | |
| 32 | /* Management Engine is in the southbridge */ |
Elyes HAOUAS | 21b71ce6 | 2018-06-16 18:43:52 +0200 | [diff] [blame] | 33 | #include <southbridge/intel/bd82x6x/me.h> |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 34 | |
| 35 | /* |
| 36 | * MRC scrambler seed offsets should be reserved in |
| 37 | * mainboard cmos.layout and not covered by checksum. |
| 38 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 39 | #if CONFIG(USE_OPTION_TABLE) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 40 | #include "option_table.h" |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 41 | #define CMOS_OFFSET_MRC_SEED (CMOS_VSTART_mrc_scrambler_seed >> 3) |
| 42 | #define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 43 | #define CMOS_OFFSET_MRC_SEED_CHK (CMOS_VSTART_mrc_scrambler_seed_chk >> 3) |
| 44 | #else |
| 45 | #define CMOS_OFFSET_MRC_SEED 152 |
| 46 | #define CMOS_OFFSET_MRC_SEED_S3 156 |
| 47 | #define CMOS_OFFSET_MRC_SEED_CHK 160 |
| 48 | #endif |
| 49 | |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 50 | #define MRC_CACHE_VERSION 0 |
| 51 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 52 | void save_mrc_data(struct pei_data *pei_data) |
| 53 | { |
| 54 | u16 c1, c2, checksum; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 55 | |
| 56 | /* Save the MRC S3 restore data to cbmem */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 57 | mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, pei_data->mrc_output, |
Arthur Heymans | 7539b8c | 2017-12-24 10:42:57 +0100 | [diff] [blame] | 58 | pei_data->mrc_output_len); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 59 | |
| 60 | /* Save the MRC seed values to CMOS */ |
Kyösti Mälkki | 2879107 | 2020-01-04 12:58:53 +0200 | [diff] [blame] | 61 | cmos_write32(pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 62 | printk(BIOS_DEBUG, "Save scrambler seed 0x%08x to CMOS 0x%02x\n", |
| 63 | pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); |
| 64 | |
Kyösti Mälkki | 2879107 | 2020-01-04 12:58:53 +0200 | [diff] [blame] | 65 | cmos_write32(pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 66 | printk(BIOS_DEBUG, "Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n", |
| 67 | pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); |
| 68 | |
| 69 | /* Save a simple checksum of the seed values */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 70 | c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, sizeof(u32)); |
| 71 | c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, sizeof(u32)); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 72 | checksum = add_ip_checksums(sizeof(u32), c1, c2); |
| 73 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 74 | cmos_write((checksum >> 0) & 0xff, CMOS_OFFSET_MRC_SEED_CHK); |
| 75 | cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK + 1); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 76 | } |
| 77 | |
| 78 | static void prepare_mrc_cache(struct pei_data *pei_data) |
| 79 | { |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 80 | u16 c1, c2, checksum, seed_checksum; |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 81 | size_t mrc_size; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 82 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 83 | /* Preset just in case there is an error */ |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 84 | pei_data->mrc_input = NULL; |
| 85 | pei_data->mrc_input_len = 0; |
| 86 | |
| 87 | /* Read scrambler seeds from CMOS */ |
| 88 | pei_data->scrambler_seed = cmos_read32(CMOS_OFFSET_MRC_SEED); |
| 89 | printk(BIOS_DEBUG, "Read scrambler seed 0x%08x from CMOS 0x%02x\n", |
| 90 | pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED); |
| 91 | |
| 92 | pei_data->scrambler_seed_s3 = cmos_read32(CMOS_OFFSET_MRC_SEED_S3); |
| 93 | printk(BIOS_DEBUG, "Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n", |
| 94 | pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3); |
| 95 | |
| 96 | /* Compute seed checksum and compare */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 97 | c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed, sizeof(u32)); |
| 98 | c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3, sizeof(u32)); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 99 | checksum = add_ip_checksums(sizeof(u32), c1, c2); |
| 100 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 101 | seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK); |
| 102 | seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK + 1) << 8; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 103 | |
| 104 | if (checksum != seed_checksum) { |
| 105 | printk(BIOS_ERR, "%s: invalid seed checksum\n", __func__); |
| 106 | pei_data->scrambler_seed = 0; |
| 107 | pei_data->scrambler_seed_s3 = 0; |
| 108 | return; |
| 109 | } |
| 110 | |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 111 | pei_data->mrc_input = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, |
| 112 | MRC_CACHE_VERSION, |
| 113 | &mrc_size); |
| 114 | if (pei_data->mrc_input == NULL) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 115 | /* Error message printed in find_current_mrc_cache */ |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 116 | return; |
| 117 | } |
| 118 | |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 119 | pei_data->mrc_input_len = mrc_size; |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 120 | |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 121 | printk(BIOS_DEBUG, "%s: at %p, size %zx\n", __func__, |
| 122 | pei_data->mrc_input, mrc_size); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 123 | } |
| 124 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 125 | /** |
| 126 | * Find PEI executable in coreboot filesystem and execute it. |
| 127 | * |
| 128 | * @param pei_data: configuration data for UEFI PEI reference code |
| 129 | */ |
| 130 | void sdram_initialize(struct pei_data *pei_data) |
| 131 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 132 | int (*entry)(struct pei_data *pei_data) __attribute__((regparm(1))); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 133 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 134 | /* Wait for ME to be ready */ |
| 135 | intel_early_me_init(); |
| 136 | intel_early_me_uma_size(); |
| 137 | |
| 138 | printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); |
| 139 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 140 | /* |
Shelley Chen | 6615c6e | 2020-10-27 15:58:31 -0700 | [diff] [blame] | 141 | * Always pass in mrc_cache data. The driver will determine |
| 142 | * whether to use the data or not. |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 143 | */ |
Shelley Chen | 6615c6e | 2020-10-27 15:58:31 -0700 | [diff] [blame] | 144 | prepare_mrc_cache(pei_data); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 145 | |
| 146 | /* If MRC data is not found we cannot continue S3 resume. */ |
| 147 | if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { |
Elyes HAOUAS | 3cd4327 | 2020-03-05 22:01:17 +0100 | [diff] [blame] | 148 | printk(BIOS_DEBUG, "Giving up in %s: No MRC data\n", __func__); |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 149 | system_reset(); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 150 | } |
| 151 | |
| 152 | /* Pass console handler in pei_data */ |
| 153 | pei_data->tx_byte = do_putchar; |
| 154 | |
| 155 | /* Locate and call UEFI System Agent binary. */ |
Julius Werner | 834b3ec | 2020-03-04 16:52:08 -0800 | [diff] [blame] | 156 | entry = cbfs_map("mrc.bin", NULL); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 157 | if (entry) { |
| 158 | int rv; |
| 159 | rv = entry (pei_data); |
| 160 | if (rv) { |
| 161 | switch (rv) { |
| 162 | case -1: |
| 163 | printk(BIOS_ERR, "PEI version mismatch.\n"); |
| 164 | break; |
| 165 | case -2: |
| 166 | printk(BIOS_ERR, "Invalid memory frequency.\n"); |
| 167 | break; |
| 168 | default: |
| 169 | printk(BIOS_ERR, "MRC returned %x.\n", rv); |
| 170 | } |
Keith Short | bb41aba | 2019-05-16 14:07:43 -0600 | [diff] [blame] | 171 | die_with_post_code(POST_INVALID_VENDOR_BINARY, |
| 172 | "Nonzero MRC return value.\n"); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 173 | } |
| 174 | } else { |
| 175 | die("UEFI PEI System Agent not found.\n"); |
| 176 | } |
| 177 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 178 | /* mrc.bin reconfigures USB, so reinit it to have debug */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 179 | if (CONFIG(USBDEBUG_IN_PRE_RAM)) |
Kyösti Mälkki | 63649d2 | 2018-12-29 09:40:40 +0200 | [diff] [blame] | 180 | usbdebug_hw_init(true); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 181 | |
Angel Pons | 9f3bc371 | 2020-10-13 23:57:10 +0200 | [diff] [blame] | 182 | /* Print the MRC version after executing the UEFI PEI stage */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 183 | u32 version = mchbar_read32(MRC_REVISION); |
Angel Pons | c1328a6 | 2021-06-14 12:43:11 +0200 | [diff] [blame] | 184 | printk(BIOS_DEBUG, "MRC Version %u.%u.%u Build %u\n", |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 185 | (version >> 24) & 0xff, (version >> 16) & 0xff, |
| 186 | (version >> 8) & 0xff, (version >> 0) & 0xff); |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 187 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 188 | /* |
| 189 | * Send ME init done for SandyBridge here. |
| 190 | * This is done inside the SystemAgent binary on IvyBridge. |
| 191 | */ |
| 192 | if (BASE_REV_SNB == (pci_read_config16(PCI_CPU_DEVICE, PCI_DEVICE_ID) & BASE_REV_MASK)) |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 193 | intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); |
| 194 | else |
| 195 | intel_early_me_status(); |
| 196 | |
Alexandru Gagniuc | ecf2eb4 | 2015-09-28 21:39:12 -0700 | [diff] [blame] | 197 | report_memory_config(); |
| 198 | } |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 199 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 200 | /* |
| 201 | * These are the location and structure of MRC_VAR data in CAR. |
| 202 | * The CAR region looks like this: |
| 203 | * +------------------+ -> DCACHE_RAM_BASE |
| 204 | * | | |
| 205 | * | | |
| 206 | * | COREBOOT STACK | |
| 207 | * | | |
| 208 | * | | |
| 209 | * +------------------+ -> DCACHE_RAM_BASE + DCACHE_RAM_SIZE |
| 210 | * | | |
| 211 | * | MRC HEAP | |
| 212 | * | size = 0x5000 | |
| 213 | * | | |
| 214 | * +------------------+ |
| 215 | * | | |
| 216 | * | MRC VAR | |
| 217 | * | size = 0x4000 | |
| 218 | * | | |
| 219 | * +------------------+ -> DACHE_RAM_BASE + DACHE_RAM_SIZE |
| 220 | * + DCACHE_RAM_MRC_VAR_SIZE |
Arthur Heymans | 01c83a2 | 2019-06-05 13:36:55 +0200 | [diff] [blame] | 221 | */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 222 | #define DCACHE_RAM_MRC_VAR_BASE (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE \ |
| 223 | + CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 0x4000) |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 224 | |
| 225 | struct mrc_var_data { |
| 226 | u32 acpi_timer_flag; |
| 227 | u32 pool_used; |
| 228 | u32 pool_base; |
| 229 | u32 tx_byte; |
| 230 | u32 reserved[4]; |
| 231 | } __packed; |
| 232 | |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 233 | static void northbridge_fill_pei_data(struct pei_data *pei_data) |
| 234 | { |
Angel Pons | d9e58dc | 2021-01-20 01:22:20 +0100 | [diff] [blame] | 235 | pei_data->mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE; |
| 236 | pei_data->dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE; |
| 237 | pei_data->epbar = CONFIG_FIXED_EPBAR_MMIO_BASE; |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 238 | pei_data->pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS; |
Felix Held | 972d9f2 | 2022-02-23 16:32:20 +0100 | [diff] [blame] | 239 | pei_data->hpet_address = HPET_BASE_ADDRESS; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 240 | pei_data->thermalbase = 0xfed08000; |
| 241 | pei_data->system_type = !(get_platform_type() == PLATFORM_MOBILE); |
| 242 | pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 243 | |
| 244 | if ((cpu_get_cpuid() & 0xffff0) == 0x306a0) { |
| 245 | const struct device *dev = pcidev_on_root(1, 0); |
| 246 | pei_data->pcie_init = dev && dev->enabled; |
| 247 | } else { |
| 248 | pei_data->pcie_init = 0; |
| 249 | } |
| 250 | } |
| 251 | |
| 252 | static void southbridge_fill_pei_data(struct pei_data *pei_data) |
| 253 | { |
| 254 | const struct device *dev = pcidev_on_root(0x19, 0); |
| 255 | |
Angel Pons | b21bffa | 2020-07-03 01:02:28 +0200 | [diff] [blame] | 256 | pei_data->smbusbar = CONFIG_FIXED_SMBUS_IO_BASE; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 257 | pei_data->wdbbar = 0x04000000; |
| 258 | pei_data->wdbsize = 0x1000; |
Angel Pons | 92717ff | 2020-09-14 16:22:22 +0200 | [diff] [blame] | 259 | pei_data->rcba = (uintptr_t)DEFAULT_RCBA; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 260 | pei_data->pmbase = DEFAULT_PMBASE; |
| 261 | pei_data->gpiobase = DEFAULT_GPIOBASE; |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 262 | pei_data->gbe_enable = dev && dev->enabled; |
| 263 | } |
| 264 | |
| 265 | static void devicetree_fill_pei_data(struct pei_data *pei_data) |
| 266 | { |
| 267 | const struct northbridge_intel_sandybridge_config *cfg; |
| 268 | |
| 269 | const struct device *dev = pcidev_on_root(0, 0); |
| 270 | if (!dev || !dev->chip_info) |
| 271 | return; |
| 272 | |
| 273 | cfg = dev->chip_info; |
| 274 | |
| 275 | switch (cfg->max_mem_clock_mhz) { |
| 276 | /* MRC only supports fixed numbers of frequencies */ |
| 277 | default: |
| 278 | printk(BIOS_WARNING, "RAMINIT: Limiting DDR3 clock to 800 Mhz\n"); |
Arthur Heymans | fff2021 | 2021-03-15 14:56:16 +0100 | [diff] [blame] | 279 | __fallthrough; |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 280 | case 400: |
| 281 | pei_data->max_ddr3_freq = 800; |
| 282 | break; |
| 283 | case 533: |
| 284 | pei_data->max_ddr3_freq = 1066; |
| 285 | break; |
| 286 | case 666: |
| 287 | pei_data->max_ddr3_freq = 1333; |
| 288 | break; |
| 289 | case 800: |
| 290 | pei_data->max_ddr3_freq = 1600; |
| 291 | break; |
| 292 | |
| 293 | } |
| 294 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 295 | memcpy(pei_data->spd_addresses, cfg->spd_addresses, sizeof(pei_data->spd_addresses)); |
| 296 | memcpy(pei_data->ts_addresses, cfg->ts_addresses, sizeof(pei_data->ts_addresses)); |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 297 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 298 | pei_data->ec_present = cfg->ec_present; |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 299 | pei_data->ddr3lv_support = cfg->ddr3lv_support; |
| 300 | |
| 301 | pei_data->nmode = cfg->nmode; |
| 302 | pei_data->ddr_refresh_rate_config = cfg->ddr_refresh_rate_config; |
| 303 | |
| 304 | memcpy(pei_data->usb_port_config, cfg->usb_port_config, |
| 305 | sizeof(pei_data->usb_port_config)); |
| 306 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 307 | pei_data->usb3.mode = cfg->usb3.mode; |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 308 | pei_data->usb3.hs_port_switch_mask = cfg->usb3.hs_port_switch_mask; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 309 | pei_data->usb3.preboot_support = cfg->usb3.preboot_support; |
| 310 | pei_data->usb3.xhci_streams = cfg->usb3.xhci_streams; |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 311 | } |
| 312 | |
Nico Huber | 47bf498 | 2019-11-17 02:58:00 +0100 | [diff] [blame] | 313 | static void disable_p2p(void) |
| 314 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 315 | /* Disable PCI-to-PCI bridge early to prevent probing by MRC */ |
Nico Huber | 47bf498 | 2019-11-17 02:58:00 +0100 | [diff] [blame] | 316 | const struct device *const p2p = pcidev_on_root(0x1e, 0); |
| 317 | if (p2p && p2p->enabled) |
| 318 | return; |
| 319 | |
| 320 | RCBA32(FD) |= PCH_DISABLE_P2P; |
| 321 | } |
| 322 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 323 | void perform_raminit(int s3resume) |
| 324 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 325 | struct pei_data pei_data; |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 326 | struct mrc_var_data *mrc_var; |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 327 | |
| 328 | /* Prepare USB controller early in S3 resume */ |
| 329 | if (!mainboard_should_reset_usb(s3resume)) |
| 330 | enable_usb_bar(); |
| 331 | |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 332 | memset(&pei_data, 0, sizeof(pei_data)); |
| 333 | pei_data.pei_version = PEI_VERSION, |
| 334 | |
| 335 | northbridge_fill_pei_data(&pei_data); |
| 336 | southbridge_fill_pei_data(&pei_data); |
| 337 | devicetree_fill_pei_data(&pei_data); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 338 | mainboard_fill_pei_data(&pei_data); |
| 339 | |
| 340 | post_code(0x3a); |
Patrick Rudolph | 59b4255 | 2019-05-08 12:44:15 +0200 | [diff] [blame] | 341 | |
Patrick Rudolph | 5709e03 | 2019-03-25 10:12:14 +0100 | [diff] [blame] | 342 | /* Fill after mainboard_fill_pei_data as it might provide spd_data */ |
| 343 | pei_data.dimm_channel0_disabled = |
| 344 | (!pei_data.spd_addresses[0] && !pei_data.spd_data[0][0]) + |
| 345 | (!pei_data.spd_addresses[1] && !pei_data.spd_data[1][0]) * 2; |
| 346 | |
| 347 | pei_data.dimm_channel1_disabled = |
| 348 | (!pei_data.spd_addresses[2] && !pei_data.spd_data[2][0]) + |
| 349 | (!pei_data.spd_addresses[3] && !pei_data.spd_data[3][0]) * 2; |
| 350 | |
Patrick Rudolph | 59b4255 | 2019-05-08 12:44:15 +0200 | [diff] [blame] | 351 | /* Fix spd_data. MRC only uses spd_data[0] and ignores the other */ |
| 352 | for (size_t i = 1; i < ARRAY_SIZE(pei_data.spd_data); i++) { |
| 353 | if (pei_data.spd_data[i][0] && !pei_data.spd_data[0][0]) { |
| 354 | memcpy(pei_data.spd_data[0], pei_data.spd_data[i], |
| 355 | sizeof(pei_data.spd_data[0])); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 356 | |
Patrick Rudolph | 59b4255 | 2019-05-08 12:44:15 +0200 | [diff] [blame] | 357 | } else if (pei_data.spd_data[i][0] && pei_data.spd_data[0][0]) { |
| 358 | if (memcmp(pei_data.spd_data[i], pei_data.spd_data[0], |
| 359 | sizeof(pei_data.spd_data[0])) != 0) |
| 360 | die("Onboard SPDs must match each other"); |
| 361 | } |
| 362 | } |
| 363 | |
Nico Huber | 47bf498 | 2019-11-17 02:58:00 +0100 | [diff] [blame] | 364 | disable_p2p(); |
| 365 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 366 | pei_data.boot_mode = s3resume ? 2 : 0; |
| 367 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 368 | sdram_initialize(&pei_data); |
Kyösti Mälkki | b33c6fb | 2021-02-17 20:43:04 +0200 | [diff] [blame] | 369 | timestamp_add_now(TS_AFTER_INITRAM); |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 370 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 371 | /* Sanity check mrc_var location by verifying a known field */ |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 372 | mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE; |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 373 | if (mrc_var->tx_byte == (uintptr_t)pei_data.tx_byte) { |
| 374 | printk(BIOS_DEBUG, "MRC_VAR pool occupied [%08x,%08x]\n", |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 375 | mrc_var->pool_base, mrc_var->pool_base + mrc_var->pool_used); |
| 376 | |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 377 | } else { |
| 378 | printk(BIOS_ERR, "Could not parse MRC_VAR data\n"); |
Felix Held | 2a29d45 | 2021-05-25 19:15:11 +0200 | [diff] [blame] | 379 | hexdump(mrc_var, sizeof(*mrc_var)); |
Kyösti Mälkki | b697c90 | 2019-01-30 08:19:49 +0200 | [diff] [blame] | 380 | } |
| 381 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 382 | const int cbmem_was_initted = !cbmem_recovery(s3resume); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 383 | if (!s3resume) |
| 384 | save_mrc_data(&pei_data); |
| 385 | |
| 386 | if (s3resume && !cbmem_was_initted) { |
| 387 | /* Failed S3 resume, reset to come up cleanly */ |
Elyes HAOUAS | c056729 | 2019-04-28 17:57:47 +0200 | [diff] [blame] | 388 | system_reset(); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 389 | } |
Matt DeVillier | ff1ef8d | 2016-12-24 15:36:24 -0600 | [diff] [blame] | 390 | setup_sdram_meminfo(&pei_data); |
| 391 | } |
| 392 | |
| 393 | void setup_sdram_meminfo(struct pei_data *pei_data) |
| 394 | { |
| 395 | u32 addr_decoder_common, addr_decode_ch[2]; |
| 396 | struct memory_info *mem_info; |
| 397 | struct dimm_info *dimm; |
| 398 | int dimm_size; |
| 399 | int i; |
| 400 | int dimm_cnt = 0; |
| 401 | |
| 402 | mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); |
| 403 | memset(mem_info, 0, sizeof(struct memory_info)); |
| 404 | |
| 405 | addr_decoder_common = mchbar_read32(MAD_CHNL); |
| 406 | addr_decode_ch[0] = mchbar_read32(MAD_DIMM_CH0); |
| 407 | addr_decode_ch[1] = mchbar_read32(MAD_DIMM_CH1); |
| 408 | |
| 409 | const int refclk = mchbar_read32(MC_BIOS_REQ) & 0x100 ? 100 : 133; |
| 410 | const int ddr_frequency = (mchbar_read32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100; |
| 411 | |
| 412 | for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { |
| 413 | u32 ch_conf = addr_decode_ch[i]; |
| 414 | |
| 415 | /* DIMM-A */ |
| 416 | dimm_size = ((ch_conf >> 0) & 0xff) * 256; |
| 417 | if (dimm_size) { |
| 418 | dimm = &mem_info->dimm[dimm_cnt]; |
| 419 | dimm->dimm_size = dimm_size; |
Elyes HAOUAS | 62b23c1 | 2022-01-26 07:43:51 +0100 | [diff] [blame] | 420 | dimm->ddr_type = MEMORY_TYPE_DDR3; |
Matt DeVillier | ff1ef8d | 2016-12-24 15:36:24 -0600 | [diff] [blame] | 421 | dimm->ddr_frequency = ddr_frequency; |
| 422 | dimm->rank_per_dimm = 1 + ((ch_conf >> 17) & 1); |
| 423 | dimm->channel_num = i; |
| 424 | dimm->dimm_num = 0; |
| 425 | dimm->bank_locator = i * 2; |
| 426 | memcpy(dimm->serial, /* bytes 122-125 */ |
Elyes HAOUAS | 921b99e | 2022-01-26 08:01:08 +0100 | [diff] [blame] | 427 | &pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM], |
| 428 | sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN); |
Matt DeVillier | ff1ef8d | 2016-12-24 15:36:24 -0600 | [diff] [blame] | 429 | memcpy(dimm->module_part_number, /* bytes 128-145 */ |
Elyes HAOUAS | 921b99e | 2022-01-26 08:01:08 +0100 | [diff] [blame] | 430 | &pei_data->spd_data[0][SPD_DIMM_PART_NUM], |
| 431 | sizeof(uint8_t) * SPD_DIMM_PART_LEN); |
Matt DeVillier | ff1ef8d | 2016-12-24 15:36:24 -0600 | [diff] [blame] | 432 | dimm->mod_id = /* bytes 117/118 */ |
Elyes HAOUAS | 921b99e | 2022-01-26 08:01:08 +0100 | [diff] [blame] | 433 | (pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) | |
| 434 | (pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF); |
Elyes HAOUAS | a233eb4 | 2022-01-26 07:51:28 +0100 | [diff] [blame] | 435 | dimm->mod_type = DDR3_SPD_SODIMM; |
Elyes HAOUAS | 62b23c1 | 2022-01-26 07:43:51 +0100 | [diff] [blame] | 436 | dimm->bus_width = MEMORY_BUS_WIDTH_64; |
Matt DeVillier | ff1ef8d | 2016-12-24 15:36:24 -0600 | [diff] [blame] | 437 | dimm_cnt++; |
| 438 | } |
| 439 | /* DIMM-B */ |
| 440 | dimm_size = ((ch_conf >> 8) & 0xff) * 256; |
| 441 | if (dimm_size) { |
| 442 | dimm = &mem_info->dimm[dimm_cnt]; |
| 443 | dimm->dimm_size = dimm_size; |
Elyes HAOUAS | 62b23c1 | 2022-01-26 07:43:51 +0100 | [diff] [blame] | 444 | dimm->ddr_type = MEMORY_TYPE_DDR3; |
Matt DeVillier | ff1ef8d | 2016-12-24 15:36:24 -0600 | [diff] [blame] | 445 | dimm->ddr_frequency = ddr_frequency; |
| 446 | dimm->rank_per_dimm = 1 + ((ch_conf >> 18) & 1); |
| 447 | dimm->channel_num = i; |
| 448 | dimm->dimm_num = 1; |
| 449 | dimm->bank_locator = i * 2; |
| 450 | memcpy(dimm->serial, /* bytes 122-125 */ |
Elyes HAOUAS | 921b99e | 2022-01-26 08:01:08 +0100 | [diff] [blame] | 451 | &pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM], |
| 452 | sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN); |
Matt DeVillier | ff1ef8d | 2016-12-24 15:36:24 -0600 | [diff] [blame] | 453 | memcpy(dimm->module_part_number, /* bytes 128-145 */ |
Elyes HAOUAS | 921b99e | 2022-01-26 08:01:08 +0100 | [diff] [blame] | 454 | &pei_data->spd_data[0][SPD_DIMM_PART_NUM], |
| 455 | sizeof(uint8_t) * SPD_DIMM_PART_LEN); |
Matt DeVillier | ff1ef8d | 2016-12-24 15:36:24 -0600 | [diff] [blame] | 456 | dimm->mod_id = /* bytes 117/118 */ |
Elyes HAOUAS | 921b99e | 2022-01-26 08:01:08 +0100 | [diff] [blame] | 457 | (pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) | |
| 458 | (pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF); |
Elyes HAOUAS | a233eb4 | 2022-01-26 07:51:28 +0100 | [diff] [blame] | 459 | dimm->mod_type = DDR3_SPD_SODIMM; |
Elyes HAOUAS | 62b23c1 | 2022-01-26 07:43:51 +0100 | [diff] [blame] | 460 | dimm->bus_width = MEMORY_BUS_WIDTH_64; |
Matt DeVillier | ff1ef8d | 2016-12-24 15:36:24 -0600 | [diff] [blame] | 461 | dimm_cnt++; |
| 462 | } |
| 463 | } |
| 464 | mem_info->dimm_cnt = dimm_cnt; |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 465 | } |