commit 92717ff3e475546366ac6439a4a0d4852bb2cb60
author Angel Pons <th3fanbus@gmail.com> Mon Sep 14 16:22:22 2020 +0200
committer Angel Pons <th3fanbus@gmail.com> Thu Sep 17 19:35:03 2020 +0000
tree 4141630e55b6499bf6709f3be56de170aa1082e6
parent 10240510a79901b0cf8ddfd8471ed412fb60bd36

nb/intel/sandybridge: Drop invalid `DEFAULT_RCBABASE` macro

RCBA is located in the PCH. Replace all instances with the
already-defined `DEFAULT_RCBA` macro, which is equivalent.

Change-Id: I4b92737820b126d32da09b69e09675464aa22e31
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45348
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/northbridge/intel/sandybridge/raminit_mrc.c

diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 5e5cc63..697862f 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -253,7 +253,7 @@
 	pei_data->smbusbar   = CONFIG_FIXED_SMBUS_IO_BASE;
 	pei_data->wdbbar     = 0x04000000;
 	pei_data->wdbsize    = 0x1000;
-	pei_data->rcba       = (uintptr_t)DEFAULT_RCBABASE;
+	pei_data->rcba       = (uintptr_t)DEFAULT_RCBA;
 	pei_data->pmbase     = DEFAULT_PMBASE;
 	pei_data->gpiobase   = DEFAULT_GPIOBASE;
 	pei_data->gbe_enable = dev && dev->enabled;