Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 1 | config SOC_INTEL_ICELAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Icelake support |
| 5 | |
| 6 | if SOC_INTEL_ICELAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 11 | select ARCH_X86 |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 12 | select BOOT_DEVICE_SUPPORTS_WRITES |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 13 | select CACHE_MRC_SETTINGS |
Michael Niewöhner | 6f1754d | 2020-09-29 17:26:58 +0200 | [diff] [blame] | 14 | select SET_IA32_FC_LOCK_BIT |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 15 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 16 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Subrata Banik | ffb83be | 2019-04-29 13:58:43 +0530 | [diff] [blame] | 17 | select FSP_M_XIP |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 18 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 19 | select GENERIC_GPIO_LIB |
| 20 | select HAVE_FSP_GOP |
Johanna Schander | 8a6e036 | 2019-12-08 15:54:09 +0100 | [diff] [blame] | 21 | select HAVE_INTEL_FSP_REPO |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 22 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 23 | select HAVE_SMI_HANDLER |
| 24 | select IDT_IN_EVERY_STAGE |
Shreesh Chhabbi | 87c7ec7 | 2020-12-03 14:07:15 -0800 | [diff] [blame] | 25 | select INTEL_CAR_NEM_ENHANCED |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 26 | select INTEL_GMA_ACPI |
| 27 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
| 28 | select IOAPIC |
Aamir Bohra | 30cca6c | 2021-02-04 20:57:51 +0530 | [diff] [blame] | 29 | select MP_SERVICES_PPI_V1 |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 30 | select MRC_SETTINGS_PROTECT |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 31 | select PARALLEL_MP_AP_WORK |
Nico Huber | f5ca922 | 2018-11-29 17:05:32 +0100 | [diff] [blame] | 32 | select MICROCODE_BLOB_UNDISCLOSED |
Subrata Banik | 55fb6b4 | 2018-12-19 16:50:57 +0530 | [diff] [blame] | 33 | select PLATFORM_USES_FSP2_1 |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 34 | select REG_SCRIPT |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 35 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Subrata Banik | 0359d9d | 2020-09-28 18:43:47 +0530 | [diff] [blame] | 36 | select PMC_LOW_POWER_MODE_PROGRAM |
Michael Niewöhner | 10ae1cf | 2020-10-11 14:05:32 +0200 | [diff] [blame] | 37 | select CPU_INTEL_COMMON |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 38 | select SOC_INTEL_COMMON |
| 39 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
| 40 | select SOC_INTEL_COMMON_BLOCK |
| 41 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Michael Niewöhner | 8a6c34e | 2021-01-01 21:26:42 +0100 | [diff] [blame] | 42 | select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT |
Subrata Banik | 21974ab | 2020-10-31 21:40:43 +0530 | [diff] [blame] | 43 | select SOC_INTEL_COMMON_BLOCK_CAR |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 44 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Furquan Shaikh | 23e8813 | 2020-10-08 23:44:20 -0700 | [diff] [blame] | 45 | select SOC_INTEL_COMMON_BLOCK_CNVI |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 46 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 47 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Angel Pons | a4cd911 | 2021-02-19 19:23:38 +0100 | [diff] [blame] | 48 | select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 49 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
| 50 | select SOC_INTEL_COMMON_BLOCK_HDA |
| 51 | select SOC_INTEL_COMMON_BLOCK_SA |
Duncan Laurie | 1e06611 | 2020-04-08 11:35:52 -0700 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_BLOCK_SCS |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 54 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Subrata Banik | 2fff391 | 2020-01-16 10:13:28 +0530 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_BLOCK_THERMAL |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_FSP_RESET |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_PCH_BASE |
| 58 | select SOC_INTEL_COMMON_RESET |
| 59 | select SSE2 |
| 60 | select SUPPORT_CPU_UCODE_IN_CBFS |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 61 | select TSC_MONOTONIC_TIMER |
| 62 | select UDELAY_TSC |
| 63 | select UDK_2017_BINDING |
| 64 | select DISPLAY_FSP_VERSION_INFO |
Subrata Banik | a0368a0 | 2019-06-04 14:16:02 +0530 | [diff] [blame] | 65 | select HECI_DISABLE_USING_SMM |
Subrata Banik | 9414600 | 2019-11-14 11:30:43 +0530 | [diff] [blame] | 66 | select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 67 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 68 | config DCACHE_RAM_BASE |
| 69 | default 0xfef00000 |
| 70 | |
| 71 | config DCACHE_RAM_SIZE |
| 72 | default 0x40000 |
| 73 | help |
| 74 | The size of the cache-as-ram region required during bootblock |
| 75 | and/or romstage. |
| 76 | |
| 77 | config DCACHE_BSP_STACK_SIZE |
| 78 | hex |
Subrata Banik | 645f244 | 2019-11-01 15:21:00 +0530 | [diff] [blame] | 79 | default 0x20400 |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 80 | help |
| 81 | The amount of anticipated stack usage in CAR by bootblock and |
V Sowmya | 1dcc170 | 2019-10-14 14:42:34 +0530 | [diff] [blame] | 82 | other stages. In the case of FSP_USES_CB_STACK default value will be |
| 83 | sum of FSP-M stack requirement (128KiB) and CB romstage stack requirement (~1KiB). |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 84 | |
Subrata Banik | 1d260e6 | 2019-09-09 13:55:42 +0530 | [diff] [blame] | 85 | config FSP_TEMP_RAM_SIZE |
| 86 | hex |
Subrata Banik | 1d260e6 | 2019-09-09 13:55:42 +0530 | [diff] [blame] | 87 | default 0x10000 |
| 88 | help |
| 89 | The amount of anticipated heap usage in CAR by FSP. |
| 90 | Refer to Platform FSP integration guide document to know |
| 91 | the exact FSP requirement for Heap setup. |
| 92 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 93 | config IFD_CHIPSET |
| 94 | string |
| 95 | default "icl" |
| 96 | |
| 97 | config IED_REGION_SIZE |
| 98 | hex |
| 99 | default 0x400000 |
| 100 | |
| 101 | config HEAP_SIZE |
| 102 | hex |
| 103 | default 0x8000 |
| 104 | |
| 105 | config MAX_ROOT_PORTS |
| 106 | int |
| 107 | default 16 |
| 108 | |
| 109 | config SMM_TSEG_SIZE |
| 110 | hex |
| 111 | default 0x800000 |
| 112 | |
| 113 | config SMM_RESERVED_SIZE |
| 114 | hex |
| 115 | default 0x200000 |
| 116 | |
| 117 | config PCR_BASE_ADDRESS |
| 118 | hex |
| 119 | default 0xfd000000 |
| 120 | help |
| 121 | This option allows you to select MMIO Base Address of sideband bus. |
| 122 | |
Subrata Banik | 26d706b | 2018-11-20 13:20:31 +0530 | [diff] [blame] | 123 | config MMCONF_BASE_ADDRESS |
Subrata Banik | 26d706b | 2018-11-20 13:20:31 +0530 | [diff] [blame] | 124 | default 0xc0000000 |
| 125 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 126 | config CPU_BCLK_MHZ |
| 127 | int |
| 128 | default 100 |
| 129 | |
| 130 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 131 | int |
| 132 | default 120 |
| 133 | |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 134 | config CPU_XTAL_HZ |
| 135 | default 38400000 |
| 136 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 137 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 138 | int |
| 139 | default 133 |
| 140 | |
| 141 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 142 | int |
| 143 | default 3 |
| 144 | |
| 145 | config SOC_INTEL_I2C_DEV_MAX |
| 146 | int |
| 147 | default 6 |
| 148 | |
Subrata Banik | 26d706b | 2018-11-20 13:20:31 +0530 | [diff] [blame] | 149 | config SOC_INTEL_UART_DEV_MAX |
| 150 | int |
| 151 | default 3 |
| 152 | |
Nico Huber | 9995418 | 2019-05-29 23:33:06 +0200 | [diff] [blame] | 153 | config CONSOLE_UART_BASE_ADDRESS |
| 154 | hex |
| 155 | default 0xfe032000 |
| 156 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 157 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 158 | # Clock divider parameters for 115200 baud rate |
| 159 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 160 | hex |
| 161 | default 0x30 |
| 162 | |
| 163 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 164 | hex |
| 165 | default 0xc35 |
| 166 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 167 | config VBOOT |
| 168 | select VBOOT_SEPARATE_VERSTAGE |
Joel Kitching | 6672bd8 | 2019-04-10 16:06:21 +0800 | [diff] [blame] | 169 | select VBOOT_MUST_REQUEST_DISPLAY |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 170 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 171 | select VBOOT_VBNV_CMOS |
| 172 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 173 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 174 | config CBFS_SIZE |
| 175 | hex |
| 176 | default 0x200000 |
| 177 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 178 | config FSP_HEADER_PATH |
Johanna Schander | f538d74 | 2019-12-08 11:04:09 +0100 | [diff] [blame] | 179 | default "3rdparty/fsp/IceLakeFspBinPkg/Include" |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 180 | |
| 181 | config FSP_FD_PATH |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 182 | default "3rdparty/fsp/IceLakeFspBinPkg/Fsp.fd" |
| 183 | |
Subrata Banik | 56626cf | 2020-02-27 19:39:22 +0530 | [diff] [blame] | 184 | config SOC_INTEL_ICELAKE_DEBUG_CONSENT |
| 185 | int "Debug Consent for ICL" |
| 186 | # USB DBC is more common for developers so make this default to 3 if |
| 187 | # SOC_INTEL_DEBUG_CONSENT=y |
| 188 | default 3 if SOC_INTEL_DEBUG_CONSENT |
| 189 | default 0 |
| 190 | help |
| 191 | This is to control debug interface on SOC. |
| 192 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 193 | PlatformDebugConsent in FspmUpd.h has the details. |
| 194 | |
| 195 | Desired platform debug types are |
| 196 | 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 197 | 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 198 | 6:Enable (2-wire DCI OOB), 7:Manual |
| 199 | |
Aamir Bohra | 3ee54bb | 2018-10-17 11:55:01 +0530 | [diff] [blame] | 200 | endif |