Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 2 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 3 | #include <commonlib/helpers.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 4 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 6 | #include <acpi/acpi.h> |
| 7 | #include <acpi/acpi_ivrs.h> |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 8 | #include <arch/ioapic.h> |
Felix Held | 61dd31c | 2023-06-05 19:38:36 +0200 | [diff] [blame] | 9 | #include <arch/vga.h> |
Elyes HAOUAS | 146d0c2 | 2020-07-22 11:47:08 +0200 | [diff] [blame] | 10 | #include <types.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 11 | #include <device/device.h> |
| 12 | #include <device/pci.h> |
| 13 | #include <device/pci_ids.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 14 | #include <string.h> |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 15 | #include <stdlib.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 16 | #include <lib.h> |
Michał Kopeć | dc35d2a | 2021-11-30 17:40:52 +0100 | [diff] [blame] | 17 | #include <cpu/x86/mp.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 18 | #include <Porting.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 19 | #include <Topology.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 20 | #include <cpu/amd/msr.h> |
| 21 | #include <cpu/amd/mtrr.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 22 | #include <acpi/acpigen.h> |
Angel Pons | ec5cf15 | 2020-11-10 20:42:07 +0100 | [diff] [blame] | 23 | #include <northbridge/amd/nb_common.h> |
Kyösti Mälkki | ed8d277 | 2017-07-15 17:12:44 +0300 | [diff] [blame] | 24 | #include <northbridge/amd/agesa/agesa_helper.h> |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 25 | #include <southbridge/amd/pi/hudson/pci_devs.h> |
Arthur Heymans | 44807ac | 2022-09-13 12:43:37 +0200 | [diff] [blame] | 26 | #include <amdblocks/cpu.h> |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 27 | |
Kyösti Mälkki | 113f670 | 2018-05-20 20:12:32 +0300 | [diff] [blame] | 28 | #define MAX_NODE_NUMS MAX_NODES |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 29 | #define PCIE_CAP_AER BIT(5) |
| 30 | #define PCIE_CAP_ACS BIT(6) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 31 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 32 | static struct device *__f0_dev[MAX_NODE_NUMS]; |
| 33 | static struct device *__f1_dev[MAX_NODE_NUMS]; |
| 34 | static struct device *__f2_dev[MAX_NODE_NUMS]; |
| 35 | static struct device *__f4_dev[MAX_NODE_NUMS]; |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 36 | static unsigned int fx_devs = 0; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 37 | |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 38 | static struct device *get_node_pci(u32 nodeid, u32 fn) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 39 | { |
Kyösti Mälkki | bbd2377 | 2019-01-10 05:41:23 +0200 | [diff] [blame] | 40 | return pcidev_on_root(DEV_CDB + nodeid, fn); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 41 | } |
| 42 | |
Michał Kopeć | ca1e8aa | 2021-12-03 15:17:46 +0100 | [diff] [blame] | 43 | static struct device *get_mc_dev(void) |
| 44 | { |
| 45 | return pcidev_on_root(DEV_CDB, 0); |
| 46 | } |
| 47 | |
| 48 | static unsigned int get_node_nums(void) |
| 49 | { |
| 50 | static unsigned int node_nums; |
| 51 | |
| 52 | if (node_nums) |
| 53 | return node_nums; |
| 54 | |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 55 | node_nums = ((pci_read_config32(get_mc_dev(), 0x60) >> 4) & 7) + 1; //NodeCnt[2:0] |
Michał Kopeć | ca1e8aa | 2021-12-03 15:17:46 +0100 | [diff] [blame] | 56 | |
| 57 | return node_nums; |
| 58 | } |
| 59 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 60 | static void get_fx_devs(void) |
| 61 | { |
| 62 | int i; |
| 63 | for (i = 0; i < MAX_NODE_NUMS; i++) { |
| 64 | __f0_dev[i] = get_node_pci(i, 0); |
| 65 | __f1_dev[i] = get_node_pci(i, 1); |
| 66 | __f2_dev[i] = get_node_pci(i, 2); |
| 67 | __f4_dev[i] = get_node_pci(i, 4); |
| 68 | if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 69 | fx_devs = i + 1; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 70 | } |
| 71 | if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { |
| 72 | die("Cannot find 0:0x18.[0|1]\n"); |
| 73 | } |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 74 | printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 75 | } |
| 76 | |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 77 | static int get_dram_base_limit(u32 nodeid, resource_t *basek, resource_t *limitk) |
| 78 | { |
| 79 | u32 temp; |
| 80 | |
| 81 | if (fx_devs == 0) |
| 82 | get_fx_devs(); |
| 83 | |
| 84 | |
| 85 | temp = pci_read_config32(__f1_dev[nodeid], 0x40 + (nodeid << 3)); //[39:24] at [31:16] |
| 86 | if (!(temp & 1)) |
| 87 | return 0; // this memory range is not enabled |
| 88 | /* |
| 89 | * BKDG: {DramBase[39:24], 00_0000h} <= address[39:0] so shift left by 8 bits |
| 90 | * for physical address and the convert to KiB by shifting 10 bits left |
| 91 | */ |
| 92 | *basek = ((temp & 0xffff0000)) >> (10 - 8); |
| 93 | /* |
| 94 | * BKDG address[39:0] <= {DramLimit[39:24], FF_FFFFh} converted as above but |
| 95 | * ORed with 0xffff to get real limit before shifting. |
| 96 | */ |
| 97 | temp = pci_read_config32(__f1_dev[nodeid], 0x44 + (nodeid << 3)); //[39:24] at [31:16] |
| 98 | *limitk = ((temp & 0xffff0000) | 0xffff) >> (10 - 8); |
| 99 | *limitk += 1; // round up last byte |
| 100 | |
| 101 | return 1; |
| 102 | } |
| 103 | |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 104 | static void add_fixed_resources(struct device *dev, int index) |
| 105 | { |
| 106 | /* Reserve everything between A segment and 1MB: |
| 107 | * |
| 108 | * 0xa0000 - 0xbffff: legacy VGA |
| 109 | * 0xc0000 - 0xfffff: option ROMs and SeaBIOS (if used) |
| 110 | */ |
Felix Held | 61dd31c | 2023-06-05 19:38:36 +0200 | [diff] [blame] | 111 | mmio_resource_kb(dev, index++, VGA_MMIO_BASE >> 10, VGA_MMIO_SIZE >> 10); |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 112 | reserved_ram_resource_kb(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 113 | |
| 114 | if (fx_devs == 0) |
| 115 | get_fx_devs(); |
| 116 | |
| 117 | /* Check if CC6 save area is enabled (bit 18 CC6SaveEn) */ |
| 118 | if (pci_read_config32(__f2_dev[0], 0x118) & (1 << 18)) { |
| 119 | /* Add CC6 DRAM UC resource residing at DRAM Limit of size 16MB as per BKDG */ |
| 120 | resource_t basek, limitk; |
| 121 | if (!get_dram_base_limit(0, &basek, &limitk)) |
| 122 | return; |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 123 | mmio_resource_kb(dev, index++, limitk, 16 * 1024); |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 124 | } |
| 125 | } |
| 126 | |
Michał Żygowski | fb198c6 | 2021-05-09 13:54:09 +0200 | [diff] [blame] | 127 | static void nb_read_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 128 | { |
Kyösti Mälkki | 5d49038 | 2015-05-27 07:58:22 +0300 | [diff] [blame] | 129 | /* |
| 130 | * This MMCONF resource must be reserved in the PCI domain. |
| 131 | * It is not honored by the coreboot resource allocator if it is in |
| 132 | * the CPU_CLUSTER. |
| 133 | */ |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 134 | mmconf_resource(dev, MMIO_CONF_BASE); |
Michał Żygowski | 208318c | 2020-03-20 15:54:27 +0100 | [diff] [blame] | 135 | |
| 136 | /* NB IOAPIC2 resource */ |
Felix Held | 8f0075c | 2023-08-09 19:28:39 +0200 | [diff] [blame] | 137 | mmio_range(dev, IO_APIC2_ADDR, IO_APIC2_ADDR, 0x1000); |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 138 | |
| 139 | add_fixed_resources(dev, 0); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 140 | } |
| 141 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 142 | static void northbridge_init(struct device *dev) |
| 143 | { |
Kyösti Mälkki | d1534e4 | 2023-04-09 10:01:58 +0300 | [diff] [blame] | 144 | register_new_ioapic((u8 *)IO_APIC2_ADDR); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 145 | } |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 146 | |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 147 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 148 | { |
| 149 | void *addr, *current; |
| 150 | |
| 151 | /* Skip the HEST header. */ |
| 152 | current = (void *)(hest + 1); |
| 153 | |
| 154 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 155 | if (addr != NULL) |
| 156 | current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 157 | |
| 158 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 159 | if (addr != NULL) |
| 160 | current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); |
| 161 | |
| 162 | return (unsigned long)current; |
| 163 | } |
| 164 | |
Arthur Heymans | f9ee87f | 2023-06-07 15:29:02 +0200 | [diff] [blame] | 165 | static unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 166 | { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 167 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 168 | current = ALIGN_UP(current, 8); |
| 169 | ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 170 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 171 | ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 172 | ivhd_ioapic->reserved = 0x0000; |
| 173 | ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | |
| 174 | IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | |
| 175 | IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; |
Kyösti Mälkki | d1534e4 | 2023-04-09 10:01:58 +0300 | [diff] [blame] | 176 | ivhd_ioapic->handle = get_ioapic_id(VIO_APIC_VADDR); |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 177 | ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); |
| 178 | ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; |
| 179 | current += sizeof(ivrs_ivhd_special_t); |
| 180 | |
| 181 | ivhd_ioapic = (ivrs_ivhd_special_t *)current; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 182 | ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 183 | ivhd_ioapic->reserved = 0x0000; |
| 184 | ivhd_ioapic->dte_setting = 0x00; |
Kyösti Mälkki | d1534e4 | 2023-04-09 10:01:58 +0300 | [diff] [blame] | 185 | ivhd_ioapic->handle = get_ioapic_id((u8 *)IO_APIC2_ADDR); |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 186 | ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); |
| 187 | ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; |
| 188 | current += sizeof(ivrs_ivhd_special_t); |
| 189 | |
| 190 | return current; |
| 191 | } |
| 192 | |
| 193 | static unsigned long ivhd_describe_hpet(unsigned long current) |
| 194 | { |
| 195 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 196 | current = ALIGN_UP(current, 8); |
| 197 | ivrs_ivhd_special_t *ivhd_hpet = (ivrs_ivhd_special_t *)current; |
| 198 | |
| 199 | ivhd_hpet->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; |
| 200 | ivhd_hpet->reserved = 0x0000; |
| 201 | ivhd_hpet->dte_setting = 0x00; |
| 202 | ivhd_hpet->handle = 0x00; |
| 203 | ivhd_hpet->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); |
| 204 | ivhd_hpet->variety = IVHD_SPECIAL_DEV_HPET; |
| 205 | current += sizeof(ivrs_ivhd_special_t); |
| 206 | |
| 207 | return current; |
| 208 | } |
| 209 | |
| 210 | static unsigned long ivhd_dev_range(unsigned long current, uint16_t start_devid, |
| 211 | uint16_t end_devid, uint8_t setting) |
| 212 | { |
| 213 | /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ |
| 214 | current = ALIGN_UP(current, 4); |
| 215 | ivrs_ivhd_generic_t *ivhd_range = (ivrs_ivhd_generic_t *)current; |
| 216 | |
| 217 | /* Create the start range IVHD entry */ |
| 218 | ivhd_range->type = IVHD_DEV_4_BYTE_START_RANGE; |
| 219 | ivhd_range->dev_id = start_devid; |
| 220 | ivhd_range->dte_setting = setting; |
| 221 | current += sizeof(ivrs_ivhd_generic_t); |
| 222 | |
| 223 | /* Create the end range IVHD entry */ |
| 224 | ivhd_range = (ivrs_ivhd_generic_t *)current; |
| 225 | ivhd_range->type = IVHD_DEV_4_BYTE_END_RANGE; |
| 226 | ivhd_range->dev_id = end_devid; |
| 227 | ivhd_range->dte_setting = setting; |
| 228 | current += sizeof(ivrs_ivhd_generic_t); |
| 229 | |
| 230 | return current; |
| 231 | } |
| 232 | |
| 233 | static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *dev, |
| 234 | unsigned long *current, uint8_t type, uint8_t data) |
| 235 | { |
| 236 | if (type == IVHD_DEV_4_BYTE_SELECT) { |
| 237 | /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ |
| 238 | *current = ALIGN_UP(*current, 4); |
| 239 | ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)*current; |
| 240 | |
| 241 | ivhd_entry->type = type; |
| 242 | ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); |
| 243 | ivhd_entry->dte_setting = data; |
| 244 | *current += sizeof(ivrs_ivhd_generic_t); |
| 245 | } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { |
| 246 | /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ |
| 247 | *current = ALIGN_UP(*current, 8); |
| 248 | ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)*current; |
| 249 | |
| 250 | ivhd_entry->type = type; |
| 251 | ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); |
| 252 | ivhd_entry->dte_setting = data; |
| 253 | ivhd_entry->reserved1 = 0; |
| 254 | ivhd_entry->reserved2 = 0; |
| 255 | ivhd_entry->source_dev_id = parent->path.pci.devfn | |
| 256 | (parent->bus->secondary << 8); |
| 257 | *current += sizeof(ivrs_ivhd_alias_t); |
| 258 | } |
| 259 | |
| 260 | return *current; |
| 261 | } |
| 262 | |
| 263 | static void ivrs_add_device_or_bridge(struct device *parent, struct device *dev, |
| 264 | unsigned long *current, uint16_t *ivhd_length) |
| 265 | { |
| 266 | unsigned int header_type, is_pcie; |
| 267 | unsigned long current_backup; |
| 268 | |
| 269 | header_type = dev->hdr_type & 0x7f; |
| 270 | is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); |
| 271 | |
| 272 | if (((header_type == PCI_HEADER_TYPE_NORMAL) || |
| 273 | (header_type == PCI_HEADER_TYPE_BRIDGE)) && is_pcie) { |
| 274 | /* Device or Bridge is PCIe */ |
| 275 | current_backup = *current; |
| 276 | add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_4_BYTE_SELECT, 0x0); |
| 277 | *ivhd_length += (*current - current_backup); |
| 278 | } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && !is_pcie) { |
| 279 | /* Device is legacy PCI or PCI-X */ |
| 280 | current_backup = *current; |
| 281 | add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_8_BYTE_ALIAS_SELECT, 0x0); |
| 282 | *ivhd_length += (*current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 283 | } |
| 284 | } |
| 285 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 286 | static void add_ivhd_device_entries(struct device *parent, struct device *dev, |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 287 | unsigned int depth, int linknum, int8_t *root_level, |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 288 | unsigned long *current, uint16_t *ivhd_length) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 289 | { |
| 290 | struct device *sibling; |
| 291 | struct bus *link; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 292 | |
| 293 | if (!root_level) { |
| 294 | root_level = malloc(sizeof(int8_t)); |
| 295 | *root_level = -1; |
| 296 | } |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 297 | |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 298 | if (dev->path.type == DEVICE_PATH_PCI) { |
| 299 | |
| 300 | if ((dev->bus->secondary == 0x0) && |
| 301 | (dev->path.pci.devfn == 0x0)) |
| 302 | *root_level = depth; |
| 303 | |
| 304 | if ((*root_level != -1) && (dev->enabled)) { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 305 | if (depth != *root_level) |
| 306 | ivrs_add_device_or_bridge(parent, dev, current, ivhd_length); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 307 | } |
| 308 | } |
| 309 | |
| 310 | for (link = dev->link_list; link; link = link->next) |
| 311 | for (sibling = link->children; sibling; sibling = |
| 312 | sibling->sibling) |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 313 | add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, |
| 314 | current, ivhd_length); |
| 315 | |
| 316 | free(root_level); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 317 | } |
| 318 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 319 | #define IOMMU_MMIO32(x) (*((volatile uint32_t *)(x))) |
| 320 | #define EFR_SUPPORT BIT(27) |
| 321 | |
| 322 | static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_t *ivrs_agesa) |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 323 | { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 324 | acpi_ivrs_ivhd11_t *ivhd_11; |
| 325 | unsigned long current_backup; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 326 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 327 | /* |
| 328 | * These devices should be already found by previous function. |
| 329 | * Do not perform NULL checks. |
| 330 | */ |
| 331 | struct device *nb_dev = pcidev_on_root(0, 0); |
| 332 | struct device *iommu_dev = pcidev_on_root(0, 2); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 333 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 334 | /* |
| 335 | * In order to utilize all features, firmware should expose type 11h |
| 336 | * IVHD which supersedes the type 10h. |
| 337 | */ |
| 338 | memset((void *)current, 0, sizeof(acpi_ivrs_ivhd11_t)); |
| 339 | ivhd_11 = (acpi_ivrs_ivhd11_t *)current; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 340 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 341 | /* Enable EFR */ |
| 342 | ivhd_11->type = IVHD_BLOCK_TYPE_FULL__FIXED; |
| 343 | /* For type 11h bits 6 and 7 are reserved */ |
| 344 | ivhd_11->flags = ivrs_agesa->ivhd.flags & 0x3f; |
| 345 | ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11); |
| 346 | /* BDF <bus>:00.2 */ |
| 347 | ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 348 | /* PCI Capability block 0x40 (type 0xf, "Secure device") */ |
| 349 | ivhd_11->capability_offset = 0x40; |
| 350 | ivhd_11->iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; |
| 351 | ivhd_11->iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; |
| 352 | ivhd_11->pci_segment_group = 0x0000; |
| 353 | ivhd_11->iommu_info = ivrs_agesa->ivhd.iommu_info; |
| 354 | ivhd_11->iommu_attributes.perf_counters = |
| 355 | (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 7) & 0xf; |
| 356 | ivhd_11->iommu_attributes.perf_counter_banks = |
| 357 | (IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x4000) >> 12) & 0x3f; |
| 358 | ivhd_11->iommu_attributes.msi_num_ppr = |
| 359 | (pci_read_config32(iommu_dev, ivhd_11->capability_offset + 0x10) >> 27) & 0x1f; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 360 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 361 | if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_SUPPORT) { |
| 362 | ivhd_11->efr_reg_image_low = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x30); |
| 363 | ivhd_11->efr_reg_image_high = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x34); |
| 364 | } |
| 365 | |
| 366 | current += sizeof(acpi_ivrs_ivhd11_t); |
| 367 | |
| 368 | /* Now repeat all the device entries from type 10h */ |
| 369 | current_backup = current; |
| 370 | current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); |
| 371 | ivhd_11->length += (current - current_backup); |
| 372 | add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivhd_11->length); |
| 373 | |
| 374 | /* Describe HPET */ |
| 375 | current_backup = current; |
| 376 | current = ivhd_describe_hpet(current); |
| 377 | ivhd_11->length += (current - current_backup); |
| 378 | |
| 379 | /* Describe IOAPICs */ |
| 380 | current_backup = current; |
| 381 | current = acpi_fill_ivrs_ioapic(ivrs_agesa, current); |
| 382 | ivhd_11->length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 383 | |
| 384 | return current; |
| 385 | } |
| 386 | |
| 387 | static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) |
| 388 | { |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 389 | acpi_ivrs_t *ivrs_agesa; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 390 | unsigned long current_backup; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 391 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 392 | struct device *nb_dev = pcidev_on_root(0, 0); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 393 | if (!nb_dev) { |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 394 | printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__); |
| 395 | printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); |
| 396 | |
| 397 | return (unsigned long)ivrs; |
| 398 | } |
| 399 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 400 | struct device *iommu_dev = pcidev_on_root(0, 2); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 401 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 402 | if (!iommu_dev) { |
| 403 | printk(BIOS_WARNING, "%s: IOMMU device not found\n", __func__); |
| 404 | |
| 405 | return (unsigned long)ivrs; |
| 406 | } |
| 407 | |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 408 | ivrs_agesa = agesawrapper_getlateinitptr(PICK_IVRS); |
| 409 | if (ivrs_agesa != NULL) { |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 410 | ivrs->iv_info = ivrs_agesa->iv_info; |
| 411 | ivrs->ivhd.type = IVHD_BLOCK_TYPE_LEGACY__FIXED; |
| 412 | ivrs->ivhd.flags = ivrs_agesa->ivhd.flags; |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 413 | ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); |
| 414 | /* BDF <bus>:00.2 */ |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 415 | ivrs->ivhd.device_id = 0x02 | (nb_dev->bus->secondary << 8); |
| 416 | /* PCI Capability block 0x40 (type 0xf, "Secure device") */ |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 417 | ivrs->ivhd.capability_offset = 0x40; |
| 418 | ivrs->ivhd.iommu_base_low = ivrs_agesa->ivhd.iommu_base_low; |
| 419 | ivrs->ivhd.iommu_base_high = ivrs_agesa->ivhd.iommu_base_high; |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 420 | ivrs->ivhd.pci_segment_group = 0x0000; |
| 421 | ivrs->ivhd.iommu_info = ivrs_agesa->ivhd.iommu_info; |
| 422 | ivrs->ivhd.iommu_feature_info = ivrs_agesa->ivhd.iommu_feature_info; |
| 423 | /* Enable EFR if supported */ |
| 424 | if (pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset) & EFR_SUPPORT) |
| 425 | ivrs->iv_info |= IVINFO_EFR_SUPPORTED; |
Piotr Król | 063e156 | 2018-07-22 20:52:26 +0200 | [diff] [blame] | 426 | } else { |
| 427 | printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); |
| 428 | |
| 429 | return (unsigned long)ivrs; |
| 430 | } |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 431 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 432 | /* |
| 433 | * Add all possible PCI devices on bus 0 that can generate transactions |
| 434 | * processed by IOMMU. Start with device 00:01.0 since IOMMU does not |
| 435 | * translate transactions generated by itself. |
| 436 | */ |
| 437 | current_backup = current; |
| 438 | current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); |
| 439 | ivrs->ivhd.length += (current - current_backup); |
| 440 | add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivrs->ivhd.length); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 441 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 442 | /* Describe HPET */ |
| 443 | current_backup = current; |
| 444 | current = ivhd_describe_hpet(current); |
| 445 | ivrs->ivhd.length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 446 | |
| 447 | /* Describe IOAPICs */ |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 448 | current_backup = current; |
| 449 | current = acpi_fill_ivrs_ioapic(ivrs_agesa, current); |
| 450 | ivrs->ivhd.length += (current - current_backup); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 451 | |
Michał Żygowski | 2f399b7 | 2020-04-02 19:51:37 +0200 | [diff] [blame] | 452 | /* If EFR is not supported, IVHD type 11h is reserved */ |
| 453 | if (!(ivrs->iv_info & IVINFO_EFR_SUPPORTED)) |
| 454 | return current; |
| 455 | |
| 456 | return acpi_fill_ivrs11(current, ivrs_agesa); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 457 | } |
| 458 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 459 | static void northbridge_fill_ssdt_generator(const struct device *device) |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 460 | { |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 461 | char pscope[] = "\\_SB.PCI0"; |
| 462 | |
| 463 | acpigen_write_scope(pscope); |
Felix Held | e345378 | 2023-04-20 13:06:08 +0200 | [diff] [blame] | 464 | acpigen_write_name_dword("TOM1", get_top_of_mem_below_4gb()); |
| 465 | |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 466 | /* |
| 467 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 468 | * here. |
| 469 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 470 | * slide 22ff. |
| 471 | * Shift value right by 20 bit to make it fit into 32bit, |
| 472 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 473 | */ |
Felix Held | 27af3e6 | 2023-04-22 05:59:52 +0200 | [diff] [blame] | 474 | acpigen_write_name_dword("TOM2", get_top_of_mem_above_4gb() >> 20); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 475 | acpigen_pop_len(); |
| 476 | } |
| 477 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 478 | static unsigned long agesa_write_acpi_tables(const struct device *device, |
Alexander Couzens | 83fc32f | 2015-04-12 22:28:37 +0200 | [diff] [blame] | 479 | unsigned long current, |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 480 | acpi_rsdp_t *rsdp) |
| 481 | { |
| 482 | acpi_srat_t *srat; |
| 483 | acpi_slit_t *slit; |
| 484 | acpi_header_t *ssdt; |
| 485 | acpi_header_t *alib; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 486 | acpi_ivrs_t *ivrs; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 487 | |
| 488 | /* HEST */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 489 | current = ALIGN_UP(current, 8); |
Vladimir Serbinenko | 807127f | 2014-11-09 13:36:18 +0100 | [diff] [blame] | 490 | acpi_write_hest((void *)current, acpi_fill_hest); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 491 | acpi_add_table(rsdp, (void *)current); |
| 492 | current += ((acpi_header_t *)current)->length; |
| 493 | |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 494 | /* IVRS */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 495 | current = ALIGN_UP(current, 8); |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 496 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 497 | ivrs = (acpi_ivrs_t *)current; |
Timothy Pearson | 9ef07d8 | 2016-06-13 13:48:58 -0500 | [diff] [blame] | 498 | acpi_create_ivrs(ivrs, acpi_fill_ivrs); |
| 499 | current += ivrs->header.length; |
| 500 | acpi_add_table(rsdp, ivrs); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 501 | |
| 502 | /* SRAT */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 503 | current = ALIGN_UP(current, 8); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 504 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 505 | srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 506 | if (srat != NULL) { |
| 507 | memcpy((void *)current, srat, srat->header.length); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 508 | srat = (acpi_srat_t *)current; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 509 | current += srat->header.length; |
| 510 | acpi_add_table(rsdp, srat); |
| 511 | } else { |
| 512 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 513 | } |
| 514 | |
| 515 | /* SLIT */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 516 | current = ALIGN_UP(current, 8); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 517 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 518 | slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 519 | if (slit != NULL) { |
| 520 | memcpy((void *)current, slit, slit->header.length); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 521 | slit = (acpi_slit_t *)current; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 522 | current += slit->header.length; |
| 523 | acpi_add_table(rsdp, slit); |
| 524 | } else { |
| 525 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 526 | } |
| 527 | |
| 528 | /* ALIB */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 529 | current = ALIGN_UP(current, 16); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 530 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 531 | alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 532 | if (alib != NULL) { |
| 533 | memcpy((void *)current, alib, alib->length); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 534 | alib = (acpi_header_t *)current; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 535 | current += alib->length; |
| 536 | acpi_add_table(rsdp, (void *)alib); |
| 537 | } |
| 538 | else { |
| 539 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); |
| 540 | } |
| 541 | |
| 542 | /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ |
| 543 | /* SSDT */ |
Elyes Haouas | d6b6b22 | 2022-10-10 12:34:21 +0200 | [diff] [blame] | 544 | current = ALIGN_UP(current, 16); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 545 | printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 546 | ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 547 | if (ssdt != NULL) { |
| 548 | memcpy((void *)current, ssdt, ssdt->length); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 549 | ssdt = (acpi_header_t *)current; |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 550 | current += ssdt->length; |
| 551 | } |
| 552 | else { |
| 553 | printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); |
| 554 | } |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 555 | acpi_add_table(rsdp, ssdt); |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 556 | |
| 557 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 558 | return current; |
| 559 | } |
| 560 | |
Felix Held | 7b9c647 | 2023-11-16 16:06:49 +0100 | [diff] [blame] | 561 | struct device_operations amd_pi_northbridge_ops = { |
Michał Żygowski | fb198c6 | 2021-05-09 13:54:09 +0200 | [diff] [blame] | 562 | .read_resources = nb_read_resources, |
Felix Held | b986e21 | 2023-12-16 00:58:09 +0100 | [diff] [blame^] | 563 | .set_resources = pci_dev_set_resources, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 564 | .enable_resources = pci_dev_enable_resources, |
| 565 | .init = northbridge_init, |
Michał Żygowski | fb198c6 | 2021-05-09 13:54:09 +0200 | [diff] [blame] | 566 | .ops_pci = &pci_dev_ops_pci, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 567 | .acpi_fill_ssdt = northbridge_fill_ssdt_generator, |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 568 | .write_acpi_tables = agesa_write_acpi_tables, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 569 | }; |
| 570 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 571 | static void fam16_finalize(void *chip_info) |
| 572 | { |
Kyösti Mälkki | 90ac736 | 2018-05-20 20:59:52 +0300 | [diff] [blame] | 573 | struct device *dev; |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 574 | dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */ |
Elyes Haouas | a1f5ad0 | 2022-02-17 18:14:08 +0100 | [diff] [blame] | 575 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 576 | pci_write_config32(dev, 0xF8, 0); |
| 577 | pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ |
| 578 | |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 579 | /* |
| 580 | * Currently it is impossible to enable ACS with AGESA by setting the |
| 581 | * correct bit for AmdInitMid phase. AGESA code path does not call the |
| 582 | * right function that enables these functionalities. Disabled ACS |
| 583 | * result in multiple PCIe devices to be assigned to the same IOMMU |
| 584 | * group. Without IOMMU group separation the devices cannot be passed |
| 585 | * through independently. |
| 586 | */ |
| 587 | |
| 588 | /* Select GPP link core IO Link Strap Control register 0xB0 */ |
| 589 | pci_write_config32(dev, 0xE0, 0x014000B0); |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 590 | |
| 591 | /* Enable AER (bit 5) and ACS (bit 6 undocumented) */ |
Elyes Haouas | a1f5ad0 | 2022-02-17 18:14:08 +0100 | [diff] [blame] | 592 | pci_or_config32(dev, 0xE4, PCIE_CAP_AER | PCIE_CAP_ACS); |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 593 | |
| 594 | /* Select GPP link core Wrapper register 0x00 (undocumented) */ |
| 595 | pci_write_config32(dev, 0xE0, 0x01300000); |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 596 | |
| 597 | /* |
| 598 | * Enable ACS capabilities straps including sub-items. From lspci it |
| 599 | * looks like these bits enable: Source Validation and Translation |
| 600 | * Blocking |
| 601 | */ |
Elyes Haouas | a1f5ad0 | 2022-02-17 18:14:08 +0100 | [diff] [blame] | 602 | pci_or_config32(dev, 0xE4, (BIT(24) | BIT(25) | BIT(26))); |
Michał Żygowski | 6ca5b47 | 2019-09-10 15:10:22 +0200 | [diff] [blame] | 603 | |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 604 | /* disable No Snoop */ |
Kyösti Mälkki | 33ff44c | 2018-05-22 01:15:22 +0300 | [diff] [blame] | 605 | dev = pcidev_on_root(1, 1); |
Kyösti Mälkki | 69f6fd4 | 2019-01-21 14:19:01 +0200 | [diff] [blame] | 606 | if (dev != NULL) { |
Elyes Haouas | a1f5ad0 | 2022-02-17 18:14:08 +0100 | [diff] [blame] | 607 | pci_and_config32(dev, 0x60, ~(1 << 11)); |
Kyösti Mälkki | 69f6fd4 | 2019-01-21 14:19:01 +0200 | [diff] [blame] | 608 | } |
Dave Frodin | 891f71a | 2015-01-19 15:58:24 -0700 | [diff] [blame] | 609 | } |
| 610 | |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 611 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 612 | struct hw_mem_hole_info { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 613 | unsigned int hole_startk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 614 | int node_id; |
| 615 | }; |
| 616 | static struct hw_mem_hole_info get_hw_mem_hole_info(void) |
| 617 | { |
| 618 | struct hw_mem_hole_info mem_hole; |
| 619 | int i; |
| 620 | mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; |
| 621 | mem_hole.node_id = -1; |
Michał Kopeć | ca1e8aa | 2021-12-03 15:17:46 +0100 | [diff] [blame] | 622 | for (i = 0; i < get_node_nums(); i++) { |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 623 | resource_t basek, limitk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 624 | u32 hole; |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 625 | if (!get_dram_base_limit(i, &basek, &limitk)) |
| 626 | continue; // no memory on this node |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 627 | hole = pci_read_config32(__f1_dev[i], 0xf0); |
| 628 | if (hole & 2) { // we find the hole |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 629 | mem_hole.hole_startk = (hole & (0xff << 24)) >> 10; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 630 | mem_hole.node_id = i; // record the node No with hole |
| 631 | break; // only one hole |
| 632 | } |
| 633 | } |
| 634 | |
| 635 | /* We need to double check if there is special set on base reg and limit reg |
| 636 | * are not continuous instead of hole, it will find out its hole_startk. |
| 637 | */ |
| 638 | if (mem_hole.node_id == -1) { |
| 639 | resource_t limitk_pri = 0; |
Michał Kopeć | ca1e8aa | 2021-12-03 15:17:46 +0100 | [diff] [blame] | 640 | for (i = 0; i < get_node_nums(); i++) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 641 | resource_t base_k, limit_k; |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 642 | if (!get_dram_base_limit(i, &base_k, &limit_k)) |
| 643 | continue; // no memory on this node |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 644 | if (base_k > 4 * 1024 * 1024) break; // don't need to go to check |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 645 | if (limitk_pri != base_k) { // we find the hole |
Elyes HAOUAS | 38a4f2a9 | 2020-01-07 19:53:36 +0100 | [diff] [blame] | 646 | mem_hole.hole_startk = (unsigned int)limitk_pri; // must be below 4G |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 647 | mem_hole.node_id = i; |
| 648 | break; //only one hole |
| 649 | } |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 650 | limitk_pri = limit_k; |
| 651 | } |
| 652 | } |
| 653 | return mem_hole; |
| 654 | } |
| 655 | #endif |
| 656 | |
Michał Żygowski | f5d457d | 2021-05-09 13:58:04 +0200 | [diff] [blame] | 657 | static void domain_read_resources(struct device *dev) |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 658 | { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 659 | unsigned long mmio_basek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 660 | int i, idx; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 661 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 662 | struct hw_mem_hole_info mem_hole; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 663 | #endif |
| 664 | |
Michał Żygowski | f5d457d | 2021-05-09 13:58:04 +0200 | [diff] [blame] | 665 | pci_domain_read_resources(dev); |
| 666 | |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 667 | /* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */ |
Felix Held | 5e9afe7 | 2023-04-20 12:55:55 +0200 | [diff] [blame] | 668 | mmio_basek = get_top_of_mem_below_4gb() >> 10; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 669 | |
| 670 | #if CONFIG_HW_MEM_HOLE_SIZEK != 0 |
| 671 | /* if the hw mem hole is already set in raminit stage, here we will compare |
| 672 | * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will |
| 673 | * use hole_basek as mmio_basek and we don't need to reset hole. |
| 674 | * otherwise We reset the hole to the mmio_basek |
| 675 | */ |
| 676 | |
| 677 | mem_hole = get_hw_mem_hole_info(); |
| 678 | |
| 679 | // Use hole_basek as mmio_basek, and we don't need to reset hole anymore |
| 680 | if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { |
| 681 | mmio_basek = mem_hole.hole_startk; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 682 | } |
| 683 | #endif |
| 684 | |
| 685 | idx = 0x10; |
Michał Kopeć | ca1e8aa | 2021-12-03 15:17:46 +0100 | [diff] [blame] | 686 | for (i = 0; i < get_node_nums(); i++) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 687 | resource_t basek, limitk, sizek; // 4 1T |
| 688 | |
Michał Żygowski | 88a0ce6 | 2021-05-05 09:52:59 +0200 | [diff] [blame] | 689 | if (!get_dram_base_limit(i, &basek, &limitk)) |
| 690 | continue; // no memory on this node |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 691 | |
| 692 | sizek = limitk - basek; |
| 693 | |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 694 | printk(BIOS_DEBUG, "node %d: basek=%08llx, limitk=%08llx, sizek=%08llx,\n", |
| 695 | i, basek, limitk, sizek); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 696 | |
Elyes Haouas | 5213b19 | 2022-02-25 18:13:03 +0100 | [diff] [blame] | 697 | /* See if we need a hole from 0xa0000 (640K) to 0xfffff (1024K) */ |
Elyes Haouas | 9d8df30 | 2022-02-25 18:23:01 +0100 | [diff] [blame] | 698 | if (basek < 640 && sizek > 1024) { |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 699 | ram_resource_kb(dev, (idx | i), basek, 640 - basek); |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 700 | idx += 0x10; |
Elyes Haouas | 9d8df30 | 2022-02-25 18:23:01 +0100 | [diff] [blame] | 701 | basek = 1024; |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 702 | sizek = limitk - basek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 703 | } |
| 704 | |
Michał Żygowski | 58d6f96 | 2021-05-05 10:52:08 +0200 | [diff] [blame] | 705 | printk(BIOS_DEBUG, "node %d: basek=%08llx, limitk=%08llx, sizek=%08llx,\n", |
| 706 | i, basek, limitk, sizek); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 707 | |
| 708 | /* split the region to accommodate pci memory space */ |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 709 | if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 710 | if (basek <= mmio_basek) { |
Subrata Banik | b1434fc | 2019-03-15 22:20:41 +0530 | [diff] [blame] | 711 | unsigned int pre_sizek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 712 | pre_sizek = mmio_basek - basek; |
Elyes HAOUAS | a813160 | 2016-09-19 10:27:57 -0600 | [diff] [blame] | 713 | if (pre_sizek > 0) { |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 714 | ram_resource_kb(dev, (idx | i), basek, pre_sizek); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 715 | idx += 0x10; |
| 716 | sizek -= pre_sizek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 717 | } |
| 718 | basek = mmio_basek; |
| 719 | } |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 720 | if ((basek + sizek) <= 4 * 1024 * 1024) { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 721 | sizek = 0; |
| 722 | } |
| 723 | else { |
Felix Held | 27af3e6 | 2023-04-22 05:59:52 +0200 | [diff] [blame] | 724 | uint64_t topmem2 = get_top_of_mem_above_4gb(); |
Elyes Haouas | f9b535e | 2022-07-16 09:47:42 +0200 | [diff] [blame] | 725 | basek = 4 * 1024 * 1024; |
| 726 | sizek = topmem2 / 1024 - basek; |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 727 | } |
| 728 | } |
| 729 | |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 730 | ram_resource_kb(dev, (idx | i), basek, sizek); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 731 | idx += 0x10; |
| 732 | printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", |
| 733 | i, mmio_basek, basek, limitk); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 734 | } |
| 735 | |
Kyösti Mälkki | e87564f | 2017-04-15 20:07:53 +0300 | [diff] [blame] | 736 | add_uma_resource_below_tolm(dev, 7); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 737 | } |
| 738 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 739 | static const char *domain_acpi_name(const struct device *dev) |
Philipp Deppenwiese | 3067012 | 2017-03-01 02:24:33 +0100 | [diff] [blame] | 740 | { |
| 741 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 742 | return "PCI0"; |
| 743 | |
| 744 | return NULL; |
| 745 | } |
| 746 | |
Felix Held | 8ccd314 | 2023-11-16 00:58:30 +0100 | [diff] [blame] | 747 | struct device_operations amd_fam16_mod30_pci_domain_ops = { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 748 | .read_resources = domain_read_resources, |
Michał Żygowski | f5d457d | 2021-05-09 13:58:04 +0200 | [diff] [blame] | 749 | .set_resources = pci_domain_set_resources, |
Arthur Heymans | 0b0113f | 2023-08-31 17:09:28 +0200 | [diff] [blame] | 750 | .scan_bus = pci_host_bridge_scan_bus, |
Philipp Deppenwiese | 3067012 | 2017-03-01 02:24:33 +0100 | [diff] [blame] | 751 | .acpi_name = domain_acpi_name, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 752 | }; |
| 753 | |
Michał Kopeć | dc35d2a | 2021-11-30 17:40:52 +0100 | [diff] [blame] | 754 | void mp_init_cpus(struct bus *cpu_bus) |
| 755 | { |
Arthur Heymans | 4fcaccf | 2022-06-02 13:17:37 +0200 | [diff] [blame] | 756 | extern const struct mp_ops amd_mp_ops_no_smm; |
Michał Kopeć | dc35d2a | 2021-11-30 17:40:52 +0100 | [diff] [blame] | 757 | /* TODO: Handle mp_init_with_smm failure? */ |
Arthur Heymans | 4fcaccf | 2022-06-02 13:17:37 +0200 | [diff] [blame] | 758 | mp_init_with_smm(cpu_bus, &amd_mp_ops_no_smm); |
Michał Kopeć | dc35d2a | 2021-11-30 17:40:52 +0100 | [diff] [blame] | 759 | |
| 760 | /* The flash is now no longer cacheable. Reset to WP for performance. */ |
| 761 | mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, |
| 762 | MTRR_TYPE_WRPROT); |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 763 | } |
| 764 | |
Felix Held | c391bff | 2023-02-16 19:38:49 +0100 | [diff] [blame] | 765 | void generate_cpu_entries(const struct device *device) |
| 766 | { |
| 767 | int cpu; |
| 768 | const int cores = get_cpu_count(); |
| 769 | |
| 770 | printk(BIOS_DEBUG, "ACPI \\_SB report %d core(s)\n", cores); |
| 771 | |
| 772 | /* Generate \_SB.Pxxx */ |
| 773 | for (cpu = 0; cpu < cores; cpu++) { |
| 774 | acpigen_write_processor_device(cpu); |
| 775 | acpigen_write_processor_device_end(); |
| 776 | } |
| 777 | } |
| 778 | |
Felix Held | 8ccd314 | 2023-11-16 00:58:30 +0100 | [diff] [blame] | 779 | struct device_operations amd_fam16_mod30_cpu_bus_ops = { |
Felix Held | c391bff | 2023-02-16 19:38:49 +0100 | [diff] [blame] | 780 | .read_resources = noop_read_resources, |
| 781 | .set_resources = noop_set_resources, |
| 782 | .init = mp_cpu_bus_init, |
| 783 | .acpi_fill_ssdt = generate_cpu_entries, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 784 | }; |
| 785 | |
Felix Held | 1952d13 | 2023-11-16 00:54:30 +0100 | [diff] [blame] | 786 | struct chip_operations northbridge_amd_pi_00730F01_ops = { |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 787 | CHIP_NAME("AMD FAM16 Root Complex") |
Felix Held | 1952d13 | 2023-11-16 00:54:30 +0100 | [diff] [blame] | 788 | .final = fam16_finalize, |
Bruce Griffith | 27ed80b | 2014-08-15 11:46:25 -0600 | [diff] [blame] | 789 | }; |
| 790 | |
| 791 | /********************************************************************* |
| 792 | * Change the vendor / device IDs to match the generic VBIOS header. * |
| 793 | *********************************************************************/ |
| 794 | u32 map_oprom_vendev(u32 vendev) |
| 795 | { |
| 796 | u32 new_vendev; |
| 797 | new_vendev = |
| 798 | ((0x10029850 <= vendev) && (vendev <= 0x1002986F)) ? 0x10029850 : vendev; |
| 799 | |
| 800 | if (vendev != new_vendev) |
| 801 | printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); |
| 802 | |
| 803 | return new_vendev; |
| 804 | } |