Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | /** |
| 17 | * @file |
| 18 | * |
| 19 | * AMD User options selection for a Brazos platform solution system |
| 20 | * |
| 21 | * This file is placed in the user's platform directory and contains the |
| 22 | * build option selections desired for that platform. |
| 23 | * |
| 24 | * For Information about this file, see @ref platforminstall. |
| 25 | * |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 26 | */ |
| 27 | |
Alexandru Gagniuc | c4e7db5 | 2014-04-05 13:40:33 -0500 | [diff] [blame] | 28 | #include "mainboard.h" |
| 29 | |
Edward O'Callaghan | d5339ae | 2014-07-07 19:58:53 +1000 | [diff] [blame] | 30 | #include <stdlib.h> |
| 31 | |
Alexandru Gagniuc | 1d87dac | 2014-03-28 14:48:13 -0500 | [diff] [blame] | 32 | #include <vendorcode/amd/agesa/f15tn/AGESA.h> |
| 33 | |
| 34 | /* Include the files that instantiate the configuration definitions. */ |
| 35 | #include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> |
Alexandru Gagniuc | 1d87dac | 2014-03-28 14:48:13 -0500 | [diff] [blame] | 36 | #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> |
| 37 | #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> |
| 38 | #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> |
| 39 | /* AGESA nonesense: the next two headers depend on heapManager.h */ |
| 40 | #include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h> |
| 41 | #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h> |
| 42 | /* These tables are optional and may be used to adjust memory timing settings */ |
| 43 | #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> |
| 44 | #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> |
| 45 | |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 46 | #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE |
| 47 | |
Elyes HAOUAS | 8ab989e | 2016-07-30 17:46:17 +0200 | [diff] [blame] | 48 | /* Select the CPU family. */ |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 49 | #define INSTALL_FAMILY_10_SUPPORT FALSE |
| 50 | #define INSTALL_FAMILY_12_SUPPORT FALSE |
| 51 | #define INSTALL_FAMILY_14_SUPPORT FALSE |
| 52 | #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE |
| 53 | |
Elyes HAOUAS | 8ab989e | 2016-07-30 17:46:17 +0200 | [diff] [blame] | 54 | /* Select the CPU socket type. */ |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 55 | #define INSTALL_G34_SOCKET_SUPPORT FALSE |
| 56 | #define INSTALL_C32_SOCKET_SUPPORT FALSE |
| 57 | #define INSTALL_S1G3_SOCKET_SUPPORT FALSE |
| 58 | #define INSTALL_S1G4_SOCKET_SUPPORT FALSE |
| 59 | #define INSTALL_ASB2_SOCKET_SUPPORT FALSE |
| 60 | #define INSTALL_FS1_SOCKET_SUPPORT TRUE |
| 61 | #define INSTALL_FM1_SOCKET_SUPPORT FALSE |
| 62 | #define INSTALL_FP2_SOCKET_SUPPORT TRUE |
| 63 | #define INSTALL_FT1_SOCKET_SUPPORT FALSE |
| 64 | #define INSTALL_AM3_SOCKET_SUPPORT FALSE |
| 65 | |
| 66 | #define INSTALL_FM2_SOCKET_SUPPORT FALSE |
| 67 | |
| 68 | //#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE |
| 69 | //#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE |
| 70 | #define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE |
| 71 | //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE |
| 72 | //#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE |
| 73 | //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE |
| 74 | #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE |
| 75 | #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE |
| 76 | #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE |
| 77 | //#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE |
| 78 | #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE |
| 79 | //#define BLDOPT_REMOVE_ACPI_PSTATES FALSE |
| 80 | #define BLDOPT_REMOVE_SRAT FALSE //TRUE |
| 81 | #define BLDOPT_REMOVE_SLIT FALSE //TRUE |
| 82 | #define BLDOPT_REMOVE_WHEA FALSE //TRUE |
| 83 | #define BLDOPT_REMOVE_CRAT TRUE |
| 84 | #define BLDOPT_REMOVE_DMI TRUE |
| 85 | //#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE |
| 86 | //#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE |
| 87 | //#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE |
| 88 | //#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE |
| 89 | //#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE |
| 90 | //#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE |
| 91 | |
| 92 | //This element selects whether P-States should be forced to be independent, |
| 93 | // as reported by the ACPI _PSD object. For single-link processors, |
| 94 | // setting TRUE for OS to support this feature. |
| 95 | |
| 96 | //#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE |
| 97 | |
| 98 | #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS |
| 99 | #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER |
| 100 | /* Build configuration values here. |
| 101 | */ |
| 102 | #define BLDCFG_VRM_CURRENT_LIMIT 90000 |
| 103 | #define BLDCFG_VRM_LOW_POWER_THRESHOLD 0 |
| 104 | #define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0 |
| 105 | #define BLDCFG_PLAT_NUM_IO_APICS 3 |
| 106 | #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST |
| 107 | #define BLDCFG_MEM_INIT_PSTATE 0 |
| 108 | |
| 109 | #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE |
| 110 | |
| 111 | #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY |
| 112 | #define BLDCFG_MEMORY_MODE_UNGANGED TRUE |
| 113 | #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE |
| 114 | #define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED |
| 115 | #define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE |
| 116 | #define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE |
| 117 | #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE |
| 118 | #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE |
| 119 | #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE |
| 120 | #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE |
| 121 | #define BLDCFG_MEMORY_POWER_DOWN TRUE |
| 122 | #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT |
| 123 | #define BLDCFG_ONLINE_SPARE FALSE |
| 124 | #define BLDCFG_BANK_SWIZZLE TRUE |
| 125 | #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO |
| 126 | #define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY |
| 127 | #define BLDCFG_DQS_TRAINING_CONTROL TRUE |
| 128 | #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE |
| 129 | #define BLDCFG_USE_BURST_MODE FALSE |
| 130 | #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE |
| 131 | #define BLDCFG_ENABLE_ECC_FEATURE TRUE |
| 132 | #define BLDCFG_ECC_REDIRECTION FALSE |
| 133 | #define BLDCFG_SCRUB_DRAM_RATE 0 |
| 134 | #define BLDCFG_SCRUB_L2_RATE 0 |
| 135 | #define BLDCFG_SCRUB_L3_RATE 0 |
| 136 | #define BLDCFG_SCRUB_IC_RATE 0 |
| 137 | #define BLDCFG_SCRUB_DC_RATE 0 |
| 138 | #define BLDCFG_ECC_SYMBOL_SIZE 4 |
| 139 | #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000 |
| 140 | #define BLDCFG_ECC_SYNC_FLOOD FALSE |
| 141 | #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE |
| 142 | #define BLDCFG_1GB_ALIGN FALSE |
| 143 | #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE |
| 144 | #define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36% |
| 145 | #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 |
| 146 | |
| 147 | #define BLDOPT_REMOVE_ALIB FALSE |
| 148 | #define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled |
| 149 | #define BLDCFG_PROCESSOR_SCOPE_NAME0 'P' |
| 150 | #define BLDCFG_PROCESSOR_SCOPE_NAME1 '0' |
| 151 | #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6 |
| 152 | |
| 153 | #define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200 |
| 154 | #define BLDCFG_CFG_ABM_SUPPORT 0 |
| 155 | |
| 156 | //#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770 |
| 157 | |
| 158 | // Specify the default values for the VRM controlling the VDDNB plane. |
| 159 | // If not specified, the values used for the core VRM will be applied |
| 160 | //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity |
| 161 | //#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L |
| 162 | //#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime |
| 163 | //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity |
| 164 | //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity |
| 165 | //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity |
| 166 | |
| 167 | #define BLDCFG_VRM_NB_CURRENT_LIMIT 60000 |
| 168 | |
| 169 | #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 |
| 170 | #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 |
| 171 | |
| 172 | #if CONFIG_GFXUMA |
| 173 | #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED |
| 174 | #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED |
| 175 | //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ |
| 176 | #define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M |
| 177 | #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE |
| 178 | #endif |
| 179 | |
Alexandru Gagniuc | 6d5657d | 2014-12-06 03:29:25 -0600 | [diff] [blame] | 180 | #define BLDCFG_IOMMU_SUPPORT TRUE |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 181 | |
| 182 | #define BLDCFG_CFG_GNB_HD_AUDIO TRUE |
| 183 | //#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID |
| 184 | //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID |
| 185 | //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID |
| 186 | |
| 187 | /* Process the options... |
| 188 | * This file include MUST occur AFTER the user option selection settings |
| 189 | */ |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 190 | /* |
| 191 | * Customized OEM build configurations for FCH component |
| 192 | */ |
| 193 | // #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00 |
| 194 | // #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20 |
| 195 | // #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00 |
| 196 | // #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400 |
| 197 | // #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404 |
| 198 | // #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408 |
| 199 | // #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410 |
| 200 | // #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420 |
| 201 | // #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000 |
| 202 | // #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000 |
| 203 | // #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000 |
| 204 | // #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0 |
| 205 | // #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00 |
| 206 | // #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000 |
| 207 | // #define BLDCFG_AZALIA_SSID 0x780D1022 |
| 208 | // #define BLDCFG_SMBUS_SSID 0x780B1022 |
| 209 | // #define BLDCFG_IDE_SSID 0x780C1022 |
| 210 | // #define BLDCFG_SATA_AHCI_SSID 0x78011022 |
| 211 | // #define BLDCFG_SATA_IDE_SSID 0x78001022 |
| 212 | // #define BLDCFG_SATA_RAID5_SSID 0x78031022 |
| 213 | // #define BLDCFG_SATA_RAID_SSID 0x78021022 |
| 214 | // #define BLDCFG_EHCI_SSID 0x78081022 |
| 215 | // #define BLDCFG_OHCI_SSID 0x78071022 |
| 216 | // #define BLDCFG_LPC_SSID 0x780E1022 |
| 217 | // #define BLDCFG_SD_SSID 0x78061022 |
| 218 | // #define BLDCFG_XHCI_SSID 0x78121022 |
| 219 | // #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE |
| 220 | // #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE |
| 221 | // #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4 |
| 222 | // #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE |
| 223 | // #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE |
| 224 | // #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE |
| 225 | // #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE |
| 226 | // #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE |
| 227 | // #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE |
| 228 | // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE |
| 229 | // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE |
| 230 | |
| 231 | CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = |
| 232 | { |
| 233 | { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, |
| 234 | { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, |
| 235 | { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, |
| 236 | { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, |
| 237 | { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, |
| 238 | { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, |
| 239 | { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, |
| 240 | { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, |
| 241 | { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, |
| 242 | { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, |
| 243 | { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, |
| 244 | { CPU_LIST_TERMINAL } |
| 245 | }; |
| 246 | |
| 247 | #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList |
| 248 | |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 249 | // This is the delivery package title, "BrazosPI" |
| 250 | // This string MUST be exactly 8 characters long |
| 251 | #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'} |
| 252 | |
| 253 | // This is the release version number of the AGESA component |
| 254 | // This string MUST be exactly 12 characters long |
| 255 | #define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '} |
| 256 | |
| 257 | /* MEMORY_BUS_SPEED */ |
| 258 | #define DDR400_FREQUENCY 200 ///< DDR 400 |
| 259 | #define DDR533_FREQUENCY 266 ///< DDR 533 |
| 260 | #define DDR667_FREQUENCY 333 ///< DDR 667 |
| 261 | #define DDR800_FREQUENCY 400 ///< DDR 800 |
| 262 | #define DDR1066_FREQUENCY 533 ///< DDR 1066 |
| 263 | #define DDR1333_FREQUENCY 667 ///< DDR 1333 |
| 264 | #define DDR1600_FREQUENCY 800 ///< DDR 1600 |
| 265 | #define DDR1866_FREQUENCY 933 ///< DDR 1866 |
| 266 | #define DDR2100_FREQUENCY 1050 ///< DDR 2100 |
| 267 | #define DDR2133_FREQUENCY 1066 ///< DDR 2133 |
| 268 | #define DDR2400_FREQUENCY 1200 ///< DDR 2400 |
| 269 | #define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency |
| 270 | |
| 271 | /* QUANDRANK_TYPE*/ |
| 272 | #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM |
| 273 | #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM |
| 274 | |
| 275 | /* USER_MEMORY_TIMING_MODE */ |
| 276 | #define TIMING_MODE_AUTO 0 ///< Use best rate possible |
| 277 | #define TIMING_MODE_LIMITED 1 ///< Set user top limit |
| 278 | #define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed |
| 279 | |
| 280 | /* POWER_DOWN_MODE */ |
| 281 | #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode |
| 282 | #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode |
| 283 | |
| 284 | /* |
| 285 | * Agesa optional capabilities selection. |
| 286 | * Uncomment and mark FALSE those features you wish to include in the build. |
| 287 | * Comment out or mark TRUE those features you want to REMOVE from the build. |
| 288 | */ |
| 289 | |
| 290 | #define DFLT_SMBUS0_BASE_ADDRESS 0xB00 |
| 291 | #define DFLT_SMBUS1_BASE_ADDRESS 0xB20 |
| 292 | #define DFLT_SIO_PME_BASE_ADDRESS 0xE00 |
| 293 | #define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800 |
| 294 | #define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804 |
| 295 | #define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808 |
| 296 | #define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810 |
| 297 | #define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820 |
| 298 | #define DFLT_SPI_BASE_ADDRESS 0xFEC10000 |
| 299 | #define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0 |
| 300 | #define DFLT_HPET_BASE_ADDRESS 0xFED00000 |
| 301 | #define DFLT_SMI_CMD_PORT 0xB0 |
| 302 | #define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00 |
| 303 | #define DFLT_GEC_BASE_ADDRESS 0xFED61000 |
| 304 | #define DFLT_AZALIA_SSID 0x780D1022 |
| 305 | #define DFLT_SMBUS_SSID 0x780B1022 |
| 306 | #define DFLT_IDE_SSID 0x780C1022 |
| 307 | #define DFLT_SATA_AHCI_SSID 0x78011022 |
| 308 | #define DFLT_SATA_IDE_SSID 0x78001022 |
| 309 | #define DFLT_SATA_RAID5_SSID 0x78031022 |
| 310 | #define DFLT_SATA_RAID_SSID 0x78021022 |
| 311 | #define DFLT_EHCI_SSID 0x78081022 |
| 312 | #define DFLT_OHCI_SSID 0x78071022 |
| 313 | #define DFLT_LPC_SSID 0x780E1022 |
| 314 | #define DFLT_SD_SSID 0x78061022 |
| 315 | #define DFLT_XHCI_SSID 0x78121022 |
| 316 | #define DFLT_FCH_PORT80_BEHIND_PCIB FALSE |
| 317 | #define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE |
| 318 | #define DFLT_FCH_GPP_LINK_CONFIG PortA4 |
| 319 | #define DFLT_FCH_GPP_PORT0_PRESENT FALSE |
| 320 | #define DFLT_FCH_GPP_PORT1_PRESENT FALSE |
| 321 | #define DFLT_FCH_GPP_PORT2_PRESENT FALSE |
| 322 | #define DFLT_FCH_GPP_PORT3_PRESENT FALSE |
| 323 | #define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE |
| 324 | #define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE |
| 325 | #define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE |
| 326 | #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE |
| 327 | //#define BLDCFG_IR_PIN_CONTROL 0x33 |
| 328 | |
Alexandru Gagniuc | 5405d3f | 2014-04-09 16:14:25 -0500 | [diff] [blame] | 329 | /* |
| 330 | * The GPIO control is not well documented in AGESA, but is in the BKDG |
| 331 | * |
| 332 | * Eg. FANIN1/GPIO57 on datasheet means power-on default (Function0) is to route |
| 333 | * from this ball to hardware monitor as FAN1 tacho input. Selecting Function1 |
| 334 | * routes this to the GPIO block instead. Seems ACPI GPIOs and related GEVENTs |
| 335 | * are mostly in Function1, sometimes Function2. |
| 336 | * |
| 337 | * Note that the GpioOut bit does not mean that the GPIO is an output. That bit |
| 338 | * actually controls the output value, so GpioOut means "default to set". |
| 339 | * PullUpB is an inverted logic, so setting this bit means we're actually |
| 340 | * disabling the internal pull-up. The PullDown bit is NOT inverted logic. |
| 341 | * The output driver can be disabled with the GpioOutEnB bit, which is again, |
| 342 | * inverted logic. To make the list more readable, we define a few local macros |
| 343 | * to state what we mean. |
| 344 | */ |
| 345 | #define OUTPUT_HIGH (GpioOut) |
| 346 | #define OUTPUT_LOW (0) |
| 347 | #define INPUT (GpioOutEnB) |
| 348 | #define PULL_UP (0) |
| 349 | #define PULL_DOWN (PullDown | PullUpB) |
| 350 | #define PULL_NONE (PullUpB) |
| 351 | |
| 352 | GPIO_CONTROL pavilion_m6_1035dx_gpio[] = { |
| 353 | {57, Function1, OUTPUT_HIGH | PULL_NONE}, /* WLAN enable */ |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 354 | {-1} |
| 355 | }; |
Alexandru Gagniuc | 5405d3f | 2014-04-09 16:14:25 -0500 | [diff] [blame] | 356 | #define BLDCFG_FCH_GPIO_CONTROL_LIST (&pavilion_m6_1035dx_gpio[0]) |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 357 | |
Alexandru Gagniuc | c4e7db5 | 2014-04-05 13:40:33 -0500 | [diff] [blame] | 358 | |
Alexandru Gagniuc | 7efd5fd | 2014-04-19 13:36:49 -0500 | [diff] [blame] | 359 | /* These definitions could be moved to a common Hudson header, should we decide |
| 360 | * to provide our own, saner SCI mapping function |
| 361 | */ |
Alexandru Gagniuc | c4e7db5 | 2014-04-05 13:40:33 -0500 | [diff] [blame] | 362 | #define GEVENT_PIN(gpe) ((gpe) + 0x40) |
Alexandru Gagniuc | 7efd5fd | 2014-04-19 13:36:49 -0500 | [diff] [blame] | 363 | #define SCI_MAP_OHCI_12_0 0x58 |
| 364 | #define SCI_MAP_OHCI_13_0 0x59 |
| 365 | #define SCI_MAP_XHCI_10_0 0x78 |
| 366 | #define SCI_MAP_PWRBTN 0x73 |
Alexandru Gagniuc | c4e7db5 | 2014-04-05 13:40:33 -0500 | [diff] [blame] | 367 | |
| 368 | SCI_MAP_CONTROL m6_1035dx_sci_map[] = { |
| 369 | {GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE}, |
Alexandru Gagniuc | 7efd5fd | 2014-04-19 13:36:49 -0500 | [diff] [blame] | 370 | {GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE}, |
Alexandru Gagniuc | cf38fac | 2014-04-19 16:22:53 -0500 | [diff] [blame] | 371 | {GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE}, |
Alexandru Gagniuc | 7efd5fd | 2014-04-19 13:36:49 -0500 | [diff] [blame] | 372 | {SCI_MAP_OHCI_12_0, PME_GPE}, |
| 373 | {SCI_MAP_OHCI_13_0, PME_GPE}, |
| 374 | {SCI_MAP_XHCI_10_0, PME_GPE}, |
| 375 | {SCI_MAP_PWRBTN, PME_GPE}, |
Alexandru Gagniuc | c4e7db5 | 2014-04-05 13:40:33 -0500 | [diff] [blame] | 376 | }; |
| 377 | #define BLDCFG_FCH_SCI_MAP_LIST (&m6_1035dx_sci_map[0]) |
| 378 | |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 379 | // The following definitions specify the default values for various parameters in which there are |
| 380 | // no clearly defined defaults to be used in the common file. The values below are based on product |
| 381 | // and BKDG content, please consult the AGESA Memory team for consultation. |
| 382 | #define DFLT_SCRUB_DRAM_RATE (0) |
| 383 | #define DFLT_SCRUB_L2_RATE (0) |
| 384 | #define DFLT_SCRUB_L3_RATE (0) |
| 385 | #define DFLT_SCRUB_IC_RATE (0) |
| 386 | #define DFLT_SCRUB_DC_RATE (0) |
| 387 | #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED |
| 388 | #define DFLT_VRM_SLEW_RATE (5000) |
| 389 | |
Alexandru Gagniuc | 1d87dac | 2014-03-28 14:48:13 -0500 | [diff] [blame] | 390 | /* AGESA nonsense: this header depends on the definitions above */ |
| 391 | #include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h> |