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review.coreboot.org / coreboot / fccfee3bce901dfe78af8c36656f09973c2f3846 / . / src / mainboard / hp / pavilion_m6_1035dx / buildOpts.c
blob: 1a231904c55c1b1c560291ec41c6fb895a722db4 [file] [log] [blame]
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame^]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20/**
21 * @file
22 *
23 * AMD User options selection for a Brazos platform solution system
24 *
25 * This file is placed in the user's platform directory and contains the
26 * build option selections desired for that platform.
27 *
28 * For Information about this file, see @ref platforminstall.
29 *
30 * @xrefitem bom "File Content Label" "Release Content"
31 * @e project: AGESA
32 * @e sub-project: Core
33 * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
34 */
35
36#include "AGESA.h"
37//#include "CommonReturns.h"
38#include "Filecode.h"
39#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
40
41/* Select the cpu family. */
42#define INSTALL_FAMILY_10_SUPPORT FALSE
43#define INSTALL_FAMILY_12_SUPPORT FALSE
44#define INSTALL_FAMILY_14_SUPPORT FALSE
45#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
46
47/* Select the cpu socket type. */
48#define INSTALL_G34_SOCKET_SUPPORT FALSE
49#define INSTALL_C32_SOCKET_SUPPORT FALSE
50#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
51#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
52#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
53#define INSTALL_FS1_SOCKET_SUPPORT TRUE
54#define INSTALL_FM1_SOCKET_SUPPORT FALSE
55#define INSTALL_FP2_SOCKET_SUPPORT TRUE
56#define INSTALL_FT1_SOCKET_SUPPORT FALSE
57#define INSTALL_AM3_SOCKET_SUPPORT FALSE
58
59#define INSTALL_FM2_SOCKET_SUPPORT FALSE
60
61//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
62//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
63#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
64//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
65//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
66//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
67#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
68#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
69#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
70//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
71#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
72//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
73#define BLDOPT_REMOVE_SRAT FALSE //TRUE
74#define BLDOPT_REMOVE_SLIT FALSE //TRUE
75#define BLDOPT_REMOVE_WHEA FALSE //TRUE
76#define BLDOPT_REMOVE_CRAT TRUE
77#define BLDOPT_REMOVE_DMI TRUE
78//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
79//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
80//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
81//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
82//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
83//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
84
85//This element selects whether P-States should be forced to be independent,
86// as reported by the ACPI _PSD object. For single-link processors,
87// setting TRUE for OS to support this feature.
88
89//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
90
91#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
92#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
93/* Build configuration values here.
94 */
95#define BLDCFG_VRM_CURRENT_LIMIT 90000
96#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
97#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0
98#define BLDCFG_PLAT_NUM_IO_APICS 3
99#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
100#define BLDCFG_MEM_INIT_PSTATE 0
101
102#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
103
104#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
105#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
106#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
107#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
108#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
109#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
110#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
111#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
112#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
113#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
114#define BLDCFG_MEMORY_POWER_DOWN TRUE
115#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
116#define BLDCFG_ONLINE_SPARE FALSE
117#define BLDCFG_BANK_SWIZZLE TRUE
118#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
119#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
120#define BLDCFG_DQS_TRAINING_CONTROL TRUE
121#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
122#define BLDCFG_USE_BURST_MODE FALSE
123#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
124#define BLDCFG_ENABLE_ECC_FEATURE TRUE
125#define BLDCFG_ECC_REDIRECTION FALSE
126#define BLDCFG_SCRUB_DRAM_RATE 0
127#define BLDCFG_SCRUB_L2_RATE 0
128#define BLDCFG_SCRUB_L3_RATE 0
129#define BLDCFG_SCRUB_IC_RATE 0
130#define BLDCFG_SCRUB_DC_RATE 0
131#define BLDCFG_ECC_SYMBOL_SIZE 4
132#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
133#define BLDCFG_ECC_SYNC_FLOOD FALSE
134#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
135#define BLDCFG_1GB_ALIGN FALSE
136#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
137#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
138#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
139
140#define BLDOPT_REMOVE_ALIB FALSE
141#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled
142#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
143#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
144#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
145
146#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
147#define BLDCFG_CFG_ABM_SUPPORT 0
148
149//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
150
151// Specify the default values for the VRM controlling the VDDNB plane.
152// If not specified, the values used for the core VRM will be applied
153//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
154//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
155//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
156//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
157//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
158//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
159
160#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
161
162#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
163#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
164
165#if CONFIG_GFXUMA
166#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
167#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
168//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
169#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
170#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
171#endif
172
173#define BLDCFG_IOMMU_SUPPORT FALSE
174
175#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
176//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
177//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
178//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
179
180/* Process the options...
181 * This file include MUST occur AFTER the user option selection settings
182 */
183#define AGESA_ENTRY_INIT_RESET TRUE
184#define AGESA_ENTRY_INIT_RECOVERY FALSE
185#define AGESA_ENTRY_INIT_EARLY TRUE
186#define AGESA_ENTRY_INIT_POST TRUE
187#define AGESA_ENTRY_INIT_ENV TRUE
188#define AGESA_ENTRY_INIT_MID TRUE
189#define AGESA_ENTRY_INIT_LATE TRUE
190#define AGESA_ENTRY_INIT_S3SAVE TRUE
191#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
192#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
193#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
194/*
195 * Customized OEM build configurations for FCH component
196 */
197// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
198// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
199// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
200// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
201// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
202// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
203// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
204// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
205// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
206// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
207// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
208// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
209// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
210// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
211// #define BLDCFG_AZALIA_SSID 0x780D1022
212// #define BLDCFG_SMBUS_SSID 0x780B1022
213// #define BLDCFG_IDE_SSID 0x780C1022
214// #define BLDCFG_SATA_AHCI_SSID 0x78011022
215// #define BLDCFG_SATA_IDE_SSID 0x78001022
216// #define BLDCFG_SATA_RAID5_SSID 0x78031022
217// #define BLDCFG_SATA_RAID_SSID 0x78021022
218// #define BLDCFG_EHCI_SSID 0x78081022
219// #define BLDCFG_OHCI_SSID 0x78071022
220// #define BLDCFG_LPC_SSID 0x780E1022
221// #define BLDCFG_SD_SSID 0x78061022
222// #define BLDCFG_XHCI_SSID 0x78121022
223// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
224// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
225// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
226// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
227// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
228// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
229// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
230// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
231// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
232// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
233// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
234
235CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
236{
237 { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
238 { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
239 { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
240 { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
241 { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
242 { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
243 { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
244 { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
245 { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
246 { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
247 { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
248 { CPU_LIST_TERMINAL }
249};
250
251#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
252
253//#include "VirgoInstall.h"
254
255/* Include the files that instantiate the configuration definitions. */
256#include "cpuRegisters.h"
257#include "cpuFamRegisters.h"
258#include "cpuFamilyTranslation.h"
259#include "AdvancedApi.h"
260#include "heapManager.h"
261#include "CreateStruct.h"
262#include "cpuFeatures.h"
263#include "Table.h"
264#include "CommonReturns.h"
265#include "cpuEarlyInit.h"
266#include "cpuLateInit.h"
267#include "GnbInterface.h"
268
269 // This is the delivery package title, "BrazosPI"
270 // This string MUST be exactly 8 characters long
271#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
272
273 // This is the release version number of the AGESA component
274 // This string MUST be exactly 12 characters long
275#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
276
277/* MEMORY_BUS_SPEED */
278#define DDR400_FREQUENCY 200 ///< DDR 400
279#define DDR533_FREQUENCY 266 ///< DDR 533
280#define DDR667_FREQUENCY 333 ///< DDR 667
281#define DDR800_FREQUENCY 400 ///< DDR 800
282#define DDR1066_FREQUENCY 533 ///< DDR 1066
283#define DDR1333_FREQUENCY 667 ///< DDR 1333
284#define DDR1600_FREQUENCY 800 ///< DDR 1600
285#define DDR1866_FREQUENCY 933 ///< DDR 1866
286#define DDR2100_FREQUENCY 1050 ///< DDR 2100
287#define DDR2133_FREQUENCY 1066 ///< DDR 2133
288#define DDR2400_FREQUENCY 1200 ///< DDR 2400
289#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
290
291/* QUANDRANK_TYPE*/
292#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
293#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
294
295/* USER_MEMORY_TIMING_MODE */
296#define TIMING_MODE_AUTO 0 ///< Use best rate possible
297#define TIMING_MODE_LIMITED 1 ///< Set user top limit
298#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
299
300/* POWER_DOWN_MODE */
301#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
302#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
303
304/*
305 * Agesa optional capabilities selection.
306 * Uncomment and mark FALSE those features you wish to include in the build.
307 * Comment out or mark TRUE those features you want to REMOVE from the build.
308 */
309
310#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
311#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
312#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
313#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
314#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
315#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
316#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
317#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
318#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
319#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
320#define DFLT_HPET_BASE_ADDRESS 0xFED00000
321#define DFLT_SMI_CMD_PORT 0xB0
322#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
323#define DFLT_GEC_BASE_ADDRESS 0xFED61000
324#define DFLT_AZALIA_SSID 0x780D1022
325#define DFLT_SMBUS_SSID 0x780B1022
326#define DFLT_IDE_SSID 0x780C1022
327#define DFLT_SATA_AHCI_SSID 0x78011022
328#define DFLT_SATA_IDE_SSID 0x78001022
329#define DFLT_SATA_RAID5_SSID 0x78031022
330#define DFLT_SATA_RAID_SSID 0x78021022
331#define DFLT_EHCI_SSID 0x78081022
332#define DFLT_OHCI_SSID 0x78071022
333#define DFLT_LPC_SSID 0x780E1022
334#define DFLT_SD_SSID 0x78061022
335#define DFLT_XHCI_SSID 0x78121022
336#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
337#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
338#define DFLT_FCH_GPP_LINK_CONFIG PortA4
339#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
340#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
341#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
342#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
343#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
344#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
345#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
346#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
347//#define BLDCFG_IR_PIN_CONTROL 0x33
348
349GPIO_CONTROL parmer_gpio[] = {
350 {183, Function1, GpioIn | GpioOutEnB | PullUpB},
351 {-1}
352};
353#define BLDCFG_FCH_GPIO_CONTROL_LIST (&parmer_gpio[0])
354
355// The following definitions specify the default values for various parameters in which there are
356// no clearly defined defaults to be used in the common file. The values below are based on product
357// and BKDG content, please consult the AGESA Memory team for consultation.
358#define DFLT_SCRUB_DRAM_RATE (0)
359#define DFLT_SCRUB_L2_RATE (0)
360#define DFLT_SCRUB_L3_RATE (0)
361#define DFLT_SCRUB_IC_RATE (0)
362#define DFLT_SCRUB_DC_RATE (0)
363#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
364#define DFLT_VRM_SLEW_RATE (5000)
365
366#include "PlatformInstall.h"
367
368/*----------------------------------------------------------------------------------------
369 * CUSTOMER OVERIDES MEMORY TABLE
370 *----------------------------------------------------------------------------------------
371 */
372
373/*
374 * Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
375 * (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
376 * is populated, AGESA will base its settings on the data from the table. Otherwise, it will
377 * use its default conservative settings.
378 */
379CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
380 //
381 // The following macros are supported (use comma to separate macros):
382 //
383 // MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
384 // The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
385 // AGESA will base on this value to disable unused MemClk to save power.
386 // Example:
387 // BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
388 // Bit AM3/S1g3 pin name
389 // 0 M[B,A]_CLK_H/L[0]
390 // 1 M[B,A]_CLK_H/L[1]
391 // 2 M[B,A]_CLK_H/L[2]
392 // 3 M[B,A]_CLK_H/L[3]
393 // 4 M[B,A]_CLK_H/L[4]
394 // 5 M[B,A]_CLK_H/L[5]
395 // 6 M[B,A]_CLK_H/L[6]
396 // 7 M[B,A]_CLK_H/L[7]
397 // And platform has the following routing:
398 // CS0 M[B,A]_CLK_H/L[4]
399 // CS1 M[B,A]_CLK_H/L[2]
400 // CS2 M[B,A]_CLK_H/L[3]
401 // CS3 M[B,A]_CLK_H/L[5]
402 // Then platform can specify the following macro:
403 // MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
404 //
405 // CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
406 // The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
407 // AGESA will base on this value to tristate unused CKE to save power.
408 //
409 // ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
410 // The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
411 // AGESA will base on this value to tristate unused ODT pins to save power.
412 //
413 // CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
414 // The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
415 // AGESA will base on this value to tristate unused Chip select to save power.
416 //
417 // NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
418 // Specifies the number of DIMM slots per channel.
419 //
420 // NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
421 // Specifies the number of Chip selects per channel.
422 //
423 // NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
424 // Specifies the number of channels per socket.
425 //
426 // OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
427 // Specifies DDR bus speed of channel ChannelID on socket SocketID.
428 //
429 // DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
430 // Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
431 //
432 // WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
433 // Byte6Seed, Byte7Seed, ByteEccSeed)
434 // Specifies the write leveling seed for a channel of a socket.
435 //
436 // HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
437 // Byte6Seed, Byte7Seed, ByteEccSeed)
438 // Speicifes the HW RXEN training seed for a channel of a socket
439 //
440 NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
441 NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
442 MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
443 CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
444 ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
445 CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
446
447 PSO_END
448};
449
450/*
451 * These tables are optional and may be used to adjust memory timing settings
452 */
453#include "mm.h"
454#include "mn.h"
455
456// Customer table
457UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] =
458{
459 // Hardcoded Memory Training Values
460
461 // The following macro should be used to override training values for your platform
462 //
463 // DQSACCESS(MTAfterDqsRwPosTrn, MTNodes, MTDcts, MTDIMMs, BFRdDqsDly, MTOverride, 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c, 0x20),
464 //
465 // NOTE:
466 // The following training hardcode values are example values that were taken from a tilapia motherboard
467 // with a particular DIMM configuration. To hardcode your own values, uncomment the appropriate line in
468 // the table and replace the byte lane values with your own.
469 //
470 // ------------------ BYTE LANES ----------------------
471 // BL0 BL1 BL2 BL3 BL4 BL5 BL6 Bl7 ECC
472 // Write Data Timing
473 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM0, BFWrDatDly, MTOverride, 0x1D, 0x20, 0x26, 0x2B, 0x37, 0x3A, 0x3e, 0x3F, 0x30),// DCT0, DIMM0
474 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct0, MTDIMM1, BFWrDatDly, MTOverride, 0x1D, 0x00, 0x06, 0x0B, 0x17, 0x1A, 0x1E, 0x1F, 0x10),// DCT0, DIMM1
475 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM0, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x27, 0x2B, 0x3B, 0x3B, 0x3E, 0x3E, 0x30),// DCT1, DIMM0
476 // DQSACCESS(MTAfterHwWLTrnP2, MTNode0, MTDct1, MTDIMM1, BFWrDatDly, MTOverride, 0x18, 0x1D, 0x1C, 0x0B, 0x17, 0x1A, 0x1D, 0x1C, 0x10),// DCT1, DIMM1
477
478 // DQS Receiver Enable
479 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
480 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct0, MTDIMM1, BFRcvEnDly, MTOverride, 0x7C, 0x7D, 0x7E, 0x81, 0x88, 0x8F, 0x96, 0x9F, 0x84),// DCT0, DIMM1
481 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM0, BFRcvEnDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT1, DIMM0
482 // DQSACCESS(MTAfterSwRxEnTrn, MTNode0, MTDct1, MTDIMM1, BFRcvEnDly, MTOverride, 0x1C, 0x1D, 0x1E, 0x01, 0x08, 0x0F, 0x16, 0x1F, 0x04),// DCT1, DIMM1
483
484 // Write DQS Delays
485 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFWrDqsDly, MTOverride, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),// DCT0, DIMM0
486 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFWrDqsDly, MTOverride, 0x06, 0x0D, 0x12, 0x1A, 0x25, 0x28, 0x2C, 0x2C, 0x44),// DCT0, DIMM1
487 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFWrDqsDly, MTOverride, 0x07, 0x0E, 0x14, 0x1B, 0x24, 0x29, 0x2B, 0x2C, 0x1F),// DCT1, DIMM0
488 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFWrDqsDly, MTOverride, 0x07, 0x0C, 0x14, 0x19, 0x25, 0x28, 0x2B, 0x2B, 0x1A),// DCT1, DIMM1
489
490 // Read DQS Delays
491 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x10),// DCT0, DIMM0
492 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct0, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT0, DIMM1
493 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM0, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM0
494 // DQSACCESS(MTAfterDqsRwPosTrn, MTNode0, MTDct1, MTDIMM1, BFRdDqsDly, MTOverride, 0x10, 0x10, 0x0E, 0x10, 0x10, 0x10, 0x10, 0x1E, 0x10),// DCT1, DIMM1
495 //--------------------------------------------------------------------------------------------------------------------------------------------------
496 // TABLE END
497 NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
498};
499UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]);