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review.coreboot.org / coreboot / c4e7db51fc83b99c43b25a8f698a9d007ed45dc6 / . / src / mainboard / hp / pavilion_m6_1035dx / buildOpts.c
blob: cf9ac4fab421c3980807cafeb6e7f43c1e35a5b9 [file] [log] [blame]
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20/**
21 * @file
22 *
23 * AMD User options selection for a Brazos platform solution system
24 *
25 * This file is placed in the user's platform directory and contains the
26 * build option selections desired for that platform.
27 *
28 * For Information about this file, see @ref platforminstall.
29 *
30 * @xrefitem bom "File Content Label" "Release Content"
31 * @e project: AGESA
32 * @e sub-project: Core
33 * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
34 */
35
Alexandru Gagniucc4e7db52014-04-05 13:40:33 -0500[diff] [blame^]36#include "mainboard.h"
37
Alexandru Gagniuc1d87dac2014-03-28 14:48:13 -0500[diff] [blame]38#include <vendorcode/amd/agesa/f15tn/AGESA.h>
39
40/* Include the files that instantiate the configuration definitions. */
41#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
42#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h>
43#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
44#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
45#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
46/* AGESA nonesense: the next two headers depend on heapManager.h */
47#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
48#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
49/* These tables are optional and may be used to adjust memory timing settings */
50#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
51#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
52
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]53#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
54
55/* Select the cpu family. */
56#define INSTALL_FAMILY_10_SUPPORT FALSE
57#define INSTALL_FAMILY_12_SUPPORT FALSE
58#define INSTALL_FAMILY_14_SUPPORT FALSE
59#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
60
61/* Select the cpu socket type. */
62#define INSTALL_G34_SOCKET_SUPPORT FALSE
63#define INSTALL_C32_SOCKET_SUPPORT FALSE
64#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
65#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
66#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
67#define INSTALL_FS1_SOCKET_SUPPORT TRUE
68#define INSTALL_FM1_SOCKET_SUPPORT FALSE
69#define INSTALL_FP2_SOCKET_SUPPORT TRUE
70#define INSTALL_FT1_SOCKET_SUPPORT FALSE
71#define INSTALL_AM3_SOCKET_SUPPORT FALSE
72
73#define INSTALL_FM2_SOCKET_SUPPORT FALSE
74
75//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
76//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
77#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
78//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
79//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
80//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
81#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
82#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
83#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
84//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
85#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
86//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
87#define BLDOPT_REMOVE_SRAT FALSE //TRUE
88#define BLDOPT_REMOVE_SLIT FALSE //TRUE
89#define BLDOPT_REMOVE_WHEA FALSE //TRUE
90#define BLDOPT_REMOVE_CRAT TRUE
91#define BLDOPT_REMOVE_DMI TRUE
92//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
93//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
94//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
95//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
96//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
97//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
98
99//This element selects whether P-States should be forced to be independent,
100// as reported by the ACPI _PSD object. For single-link processors,
101// setting TRUE for OS to support this feature.
102
103//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
104
105#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
106#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
107/* Build configuration values here.
108 */
109#define BLDCFG_VRM_CURRENT_LIMIT 90000
110#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
111#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0
112#define BLDCFG_PLAT_NUM_IO_APICS 3
113#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
114#define BLDCFG_MEM_INIT_PSTATE 0
115
116#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
117
118#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
119#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
120#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
121#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
122#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
123#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
124#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
125#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
126#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
127#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
128#define BLDCFG_MEMORY_POWER_DOWN TRUE
129#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
130#define BLDCFG_ONLINE_SPARE FALSE
131#define BLDCFG_BANK_SWIZZLE TRUE
132#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
133#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
134#define BLDCFG_DQS_TRAINING_CONTROL TRUE
135#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
136#define BLDCFG_USE_BURST_MODE FALSE
137#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
138#define BLDCFG_ENABLE_ECC_FEATURE TRUE
139#define BLDCFG_ECC_REDIRECTION FALSE
140#define BLDCFG_SCRUB_DRAM_RATE 0
141#define BLDCFG_SCRUB_L2_RATE 0
142#define BLDCFG_SCRUB_L3_RATE 0
143#define BLDCFG_SCRUB_IC_RATE 0
144#define BLDCFG_SCRUB_DC_RATE 0
145#define BLDCFG_ECC_SYMBOL_SIZE 4
146#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
147#define BLDCFG_ECC_SYNC_FLOOD FALSE
148#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
149#define BLDCFG_1GB_ALIGN FALSE
150#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
151#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
152#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
153
154#define BLDOPT_REMOVE_ALIB FALSE
155#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled
156#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
157#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
158#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
159
160#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
161#define BLDCFG_CFG_ABM_SUPPORT 0
162
163//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
164
165// Specify the default values for the VRM controlling the VDDNB plane.
166// If not specified, the values used for the core VRM will be applied
167//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
168//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
169//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
170//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
171//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
172//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
173
174#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
175
176#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
177#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
178
179#if CONFIG_GFXUMA
180#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
181#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
182//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
183#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
184#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
185#endif
186
187#define BLDCFG_IOMMU_SUPPORT FALSE
188
189#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
190//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
191//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
192//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
193
194/* Process the options...
195 * This file include MUST occur AFTER the user option selection settings
196 */
197#define AGESA_ENTRY_INIT_RESET TRUE
198#define AGESA_ENTRY_INIT_RECOVERY FALSE
199#define AGESA_ENTRY_INIT_EARLY TRUE
200#define AGESA_ENTRY_INIT_POST TRUE
201#define AGESA_ENTRY_INIT_ENV TRUE
202#define AGESA_ENTRY_INIT_MID TRUE
203#define AGESA_ENTRY_INIT_LATE TRUE
204#define AGESA_ENTRY_INIT_S3SAVE TRUE
205#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
206#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
207#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
208/*
209 * Customized OEM build configurations for FCH component
210 */
211// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
212// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
213// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
214// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
215// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
216// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
217// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
218// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
219// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
220// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
221// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
222// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
223// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
224// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
225// #define BLDCFG_AZALIA_SSID 0x780D1022
226// #define BLDCFG_SMBUS_SSID 0x780B1022
227// #define BLDCFG_IDE_SSID 0x780C1022
228// #define BLDCFG_SATA_AHCI_SSID 0x78011022
229// #define BLDCFG_SATA_IDE_SSID 0x78001022
230// #define BLDCFG_SATA_RAID5_SSID 0x78031022
231// #define BLDCFG_SATA_RAID_SSID 0x78021022
232// #define BLDCFG_EHCI_SSID 0x78081022
233// #define BLDCFG_OHCI_SSID 0x78071022
234// #define BLDCFG_LPC_SSID 0x780E1022
235// #define BLDCFG_SD_SSID 0x78061022
236// #define BLDCFG_XHCI_SSID 0x78121022
237// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
238// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
239// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
240// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
241// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
242// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
243// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
244// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
245// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
246// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
247// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
248
249CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
250{
251 { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
252 { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
253 { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
254 { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
255 { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
256 { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
257 { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
258 { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
259 { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
260 { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
261 { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
262 { CPU_LIST_TERMINAL }
263};
264
265#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
266
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]267 // This is the delivery package title, "BrazosPI"
268 // This string MUST be exactly 8 characters long
269#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
270
271 // This is the release version number of the AGESA component
272 // This string MUST be exactly 12 characters long
273#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
274
275/* MEMORY_BUS_SPEED */
276#define DDR400_FREQUENCY 200 ///< DDR 400
277#define DDR533_FREQUENCY 266 ///< DDR 533
278#define DDR667_FREQUENCY 333 ///< DDR 667
279#define DDR800_FREQUENCY 400 ///< DDR 800
280#define DDR1066_FREQUENCY 533 ///< DDR 1066
281#define DDR1333_FREQUENCY 667 ///< DDR 1333
282#define DDR1600_FREQUENCY 800 ///< DDR 1600
283#define DDR1866_FREQUENCY 933 ///< DDR 1866
284#define DDR2100_FREQUENCY 1050 ///< DDR 2100
285#define DDR2133_FREQUENCY 1066 ///< DDR 2133
286#define DDR2400_FREQUENCY 1200 ///< DDR 2400
287#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
288
289/* QUANDRANK_TYPE*/
290#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
291#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
292
293/* USER_MEMORY_TIMING_MODE */
294#define TIMING_MODE_AUTO 0 ///< Use best rate possible
295#define TIMING_MODE_LIMITED 1 ///< Set user top limit
296#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
297
298/* POWER_DOWN_MODE */
299#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
300#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
301
302/*
303 * Agesa optional capabilities selection.
304 * Uncomment and mark FALSE those features you wish to include in the build.
305 * Comment out or mark TRUE those features you want to REMOVE from the build.
306 */
307
308#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
309#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
310#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
311#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
312#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
313#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
314#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
315#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
316#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
317#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
318#define DFLT_HPET_BASE_ADDRESS 0xFED00000
319#define DFLT_SMI_CMD_PORT 0xB0
320#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
321#define DFLT_GEC_BASE_ADDRESS 0xFED61000
322#define DFLT_AZALIA_SSID 0x780D1022
323#define DFLT_SMBUS_SSID 0x780B1022
324#define DFLT_IDE_SSID 0x780C1022
325#define DFLT_SATA_AHCI_SSID 0x78011022
326#define DFLT_SATA_IDE_SSID 0x78001022
327#define DFLT_SATA_RAID5_SSID 0x78031022
328#define DFLT_SATA_RAID_SSID 0x78021022
329#define DFLT_EHCI_SSID 0x78081022
330#define DFLT_OHCI_SSID 0x78071022
331#define DFLT_LPC_SSID 0x780E1022
332#define DFLT_SD_SSID 0x78061022
333#define DFLT_XHCI_SSID 0x78121022
334#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
335#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
336#define DFLT_FCH_GPP_LINK_CONFIG PortA4
337#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
338#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
339#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
340#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
341#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
342#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
343#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
344#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
345//#define BLDCFG_IR_PIN_CONTROL 0x33
346
Alexandru Gagniuc5405d3f2014-04-09 16:14:25 -0500[diff] [blame]347/*
348 * The GPIO control is not well documented in AGESA, but is in the BKDG
349 *
350 * Eg. FANIN1/GPIO57 on datasheet means power-on default (Function0) is to route
351 * from this ball to hardware monitor as FAN1 tacho input. Selecting Function1
352 * routes this to the GPIO block instead. Seems ACPI GPIOs and related GEVENTs
353 * are mostly in Function1, sometimes Function2.
354 *
355 * Note that the GpioOut bit does not mean that the GPIO is an output. That bit
356 * actually controls the output value, so GpioOut means "default to set".
357 * PullUpB is an inverted logic, so setting this bit means we're actually
358 * disabling the internal pull-up. The PullDown bit is NOT inverted logic.
359 * The output driver can be disabled with the GpioOutEnB bit, which is again,
360 * inverted logic. To make the list more readable, we define a few local macros
361 * to state what we mean.
362 */
363#define OUTPUT_HIGH (GpioOut)
364#define OUTPUT_LOW (0)
365#define INPUT (GpioOutEnB)
366#define PULL_UP (0)
367#define PULL_DOWN (PullDown | PullUpB)
368#define PULL_NONE (PullUpB)
369
370GPIO_CONTROL pavilion_m6_1035dx_gpio[] = {
371 {57, Function1, OUTPUT_HIGH | PULL_NONE}, /* WLAN enable */
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]372 {-1}
373};
Alexandru Gagniuc5405d3f2014-04-09 16:14:25 -0500[diff] [blame]374#define BLDCFG_FCH_GPIO_CONTROL_LIST (&pavilion_m6_1035dx_gpio[0])
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]375
Alexandru Gagniucc4e7db52014-04-05 13:40:33 -0500[diff] [blame^]376
377#define GEVENT_PIN(gpe) ((gpe) + 0x40)
378
379SCI_MAP_CONTROL m6_1035dx_sci_map[] = {
380 {GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE},
381 {GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE}, /* EC_SMI - GPE23 */
382};
383#define BLDCFG_FCH_SCI_MAP_LIST (&m6_1035dx_sci_map[0])
384
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]385// The following definitions specify the default values for various parameters in which there are
386// no clearly defined defaults to be used in the common file. The values below are based on product
387// and BKDG content, please consult the AGESA Memory team for consultation.
388#define DFLT_SCRUB_DRAM_RATE (0)
389#define DFLT_SCRUB_L2_RATE (0)
390#define DFLT_SCRUB_L3_RATE (0)
391#define DFLT_SCRUB_IC_RATE (0)
392#define DFLT_SCRUB_DC_RATE (0)
393#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
394#define DFLT_VRM_SLEW_RATE (5000)
395
Alexandru Gagniuc1d87dac2014-03-28 14:48:13 -0500[diff] [blame]396/* AGESA nonsense: this header depends on the definitions above */
397#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]398
399/*----------------------------------------------------------------------------------------
400 * CUSTOMER OVERIDES MEMORY TABLE
401 *----------------------------------------------------------------------------------------
402 */
403
404/*
Alexandru Gagniuc0b2fa342014-04-05 18:51:33 -0500[diff] [blame]405 * Platform Specific Overriding Table allows IBV/OEM to pass in platform
406 * information to AGESA
407 * (e.g. MemClk routing, the number of DIMM slots per channel,...).
408 * If PlatformSpecificTable is populated, AGESA will base its settings on the
409 * data from the table. Otherwise, it will use its default conservative settings
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]410 */
411CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
Alexandru Gagniuc0b2fa342014-04-05 18:51:33 -0500[diff] [blame]412
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]413 NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
414 NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
415 MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
416 CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
417 ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
418 CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
419
420 PSO_END
421};
422
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]423// Customer table
424UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] =
425{
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]426 NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
427};
428UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]);