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review.coreboot.org / coreboot / 5405d3fe91ba9f218521c5f0a84561909d37ce5a / . / src / mainboard / hp / pavilion_m6_1035dx / buildOpts.c
blob: aa223cc567ccd2d2933b4cf9c69b68436fecd1fb [file] [log] [blame]
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20/**
21 * @file
22 *
23 * AMD User options selection for a Brazos platform solution system
24 *
25 * This file is placed in the user's platform directory and contains the
26 * build option selections desired for that platform.
27 *
28 * For Information about this file, see @ref platforminstall.
29 *
30 * @xrefitem bom "File Content Label" "Release Content"
31 * @e project: AGESA
32 * @e sub-project: Core
33 * @e \$Revision: 23714 $ @e \$Date: 2009-12-09 17:28:37 -0600 (Wed, 09 Dec 2009) $
34 */
35
Alexandru Gagniuc1d87dac2014-03-28 14:48:13 -0500[diff] [blame]36#include <vendorcode/amd/agesa/f15tn/AGESA.h>
37
38/* Include the files that instantiate the configuration definitions. */
39#include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h>
40#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h>
41#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h>
42#include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h>
43#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h>
44/* AGESA nonesense: the next two headers depend on heapManager.h */
45#include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h>
46#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h>
47/* These tables are optional and may be used to adjust memory timing settings */
48#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h>
49#include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h>
50
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]51#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
52
53/* Select the cpu family. */
54#define INSTALL_FAMILY_10_SUPPORT FALSE
55#define INSTALL_FAMILY_12_SUPPORT FALSE
56#define INSTALL_FAMILY_14_SUPPORT FALSE
57#define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE
58
59/* Select the cpu socket type. */
60#define INSTALL_G34_SOCKET_SUPPORT FALSE
61#define INSTALL_C32_SOCKET_SUPPORT FALSE
62#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
63#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
64#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
65#define INSTALL_FS1_SOCKET_SUPPORT TRUE
66#define INSTALL_FM1_SOCKET_SUPPORT FALSE
67#define INSTALL_FP2_SOCKET_SUPPORT TRUE
68#define INSTALL_FT1_SOCKET_SUPPORT FALSE
69#define INSTALL_AM3_SOCKET_SUPPORT FALSE
70
71#define INSTALL_FM2_SOCKET_SUPPORT FALSE
72
73//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
74//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
75#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
76//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
77//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
78//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
79#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
80#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
81#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
82//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
83#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
84//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
85#define BLDOPT_REMOVE_SRAT FALSE //TRUE
86#define BLDOPT_REMOVE_SLIT FALSE //TRUE
87#define BLDOPT_REMOVE_WHEA FALSE //TRUE
88#define BLDOPT_REMOVE_CRAT TRUE
89#define BLDOPT_REMOVE_DMI TRUE
90//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
91//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
92//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
93//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
94//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
95//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
96
97//This element selects whether P-States should be forced to be independent,
98// as reported by the ACPI _PSD object. For single-link processors,
99// setting TRUE for OS to support this feature.
100
101//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
102
103#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
104#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
105/* Build configuration values here.
106 */
107#define BLDCFG_VRM_CURRENT_LIMIT 90000
108#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
109#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 0
110#define BLDCFG_PLAT_NUM_IO_APICS 3
111#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
112#define BLDCFG_MEM_INIT_PSTATE 0
113
114#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
115
116#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY
117#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
118#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
119#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
120#define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE
121#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
122#define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
123#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
124#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
125#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE
126#define BLDCFG_MEMORY_POWER_DOWN TRUE
127#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
128#define BLDCFG_ONLINE_SPARE FALSE
129#define BLDCFG_BANK_SWIZZLE TRUE
130#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
131#define BLDCFG_MEMORY_CLOCK_SELECT DDR1866_FREQUENCY
132#define BLDCFG_DQS_TRAINING_CONTROL TRUE
133#define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
134#define BLDCFG_USE_BURST_MODE FALSE
135#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
136#define BLDCFG_ENABLE_ECC_FEATURE TRUE
137#define BLDCFG_ECC_REDIRECTION FALSE
138#define BLDCFG_SCRUB_DRAM_RATE 0
139#define BLDCFG_SCRUB_L2_RATE 0
140#define BLDCFG_SCRUB_L3_RATE 0
141#define BLDCFG_SCRUB_IC_RATE 0
142#define BLDCFG_SCRUB_DC_RATE 0
143#define BLDCFG_ECC_SYMBOL_SIZE 4
144#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
145#define BLDCFG_ECC_SYNC_FLOOD FALSE
146#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
147#define BLDCFG_1GB_ALIGN FALSE
148#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
149#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
150#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
151
152#define BLDOPT_REMOVE_ALIB FALSE
153#define BLDCFG_PLATFORM_CPB_MODE CpbModeDisabled
154#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
155#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
156#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
157
158#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
159#define BLDCFG_CFG_ABM_SUPPORT 0
160
161//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
162
163// Specify the default values for the VRM controlling the VDDNB plane.
164// If not specified, the values used for the core VRM will be applied
165//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
166//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
167//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
168//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
169//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
170//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
171
172#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
173
174#define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3
175#define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3
176
177#if CONFIG_GFXUMA
178#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
179#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
180//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
181#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
182#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
183#endif
184
185#define BLDCFG_IOMMU_SUPPORT FALSE
186
187#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
188//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
189//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
190//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
191
192/* Process the options...
193 * This file include MUST occur AFTER the user option selection settings
194 */
195#define AGESA_ENTRY_INIT_RESET TRUE
196#define AGESA_ENTRY_INIT_RECOVERY FALSE
197#define AGESA_ENTRY_INIT_EARLY TRUE
198#define AGESA_ENTRY_INIT_POST TRUE
199#define AGESA_ENTRY_INIT_ENV TRUE
200#define AGESA_ENTRY_INIT_MID TRUE
201#define AGESA_ENTRY_INIT_LATE TRUE
202#define AGESA_ENTRY_INIT_S3SAVE TRUE
203#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE
204#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
205#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
206/*
207 * Customized OEM build configurations for FCH component
208 */
209// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
210// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
211// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
212// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
213// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
214// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
215// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
216// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
217// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
218// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
219// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
220// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
221// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
222// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
223// #define BLDCFG_AZALIA_SSID 0x780D1022
224// #define BLDCFG_SMBUS_SSID 0x780B1022
225// #define BLDCFG_IDE_SSID 0x780C1022
226// #define BLDCFG_SATA_AHCI_SSID 0x78011022
227// #define BLDCFG_SATA_IDE_SSID 0x78001022
228// #define BLDCFG_SATA_RAID5_SSID 0x78031022
229// #define BLDCFG_SATA_RAID_SSID 0x78021022
230// #define BLDCFG_EHCI_SSID 0x78081022
231// #define BLDCFG_OHCI_SSID 0x78071022
232// #define BLDCFG_LPC_SSID 0x780E1022
233// #define BLDCFG_SD_SSID 0x78061022
234// #define BLDCFG_XHCI_SSID 0x78121022
235// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
236// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
237// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
238// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
239// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
240// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
241// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
242// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
243// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
244// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
245// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
246
247CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
248{
249 { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
250 { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
251 { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
252 { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
253 { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
254 { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
255 { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
256 { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
257 { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
258 { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
259 { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
260 { CPU_LIST_TERMINAL }
261};
262
263#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
264
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]265 // This is the delivery package title, "BrazosPI"
266 // This string MUST be exactly 8 characters long
267#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
268
269 // This is the release version number of the AGESA component
270 // This string MUST be exactly 12 characters long
271#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
272
273/* MEMORY_BUS_SPEED */
274#define DDR400_FREQUENCY 200 ///< DDR 400
275#define DDR533_FREQUENCY 266 ///< DDR 533
276#define DDR667_FREQUENCY 333 ///< DDR 667
277#define DDR800_FREQUENCY 400 ///< DDR 800
278#define DDR1066_FREQUENCY 533 ///< DDR 1066
279#define DDR1333_FREQUENCY 667 ///< DDR 1333
280#define DDR1600_FREQUENCY 800 ///< DDR 1600
281#define DDR1866_FREQUENCY 933 ///< DDR 1866
282#define DDR2100_FREQUENCY 1050 ///< DDR 2100
283#define DDR2133_FREQUENCY 1066 ///< DDR 2133
284#define DDR2400_FREQUENCY 1200 ///< DDR 2400
285#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
286
287/* QUANDRANK_TYPE*/
288#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
289#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
290
291/* USER_MEMORY_TIMING_MODE */
292#define TIMING_MODE_AUTO 0 ///< Use best rate possible
293#define TIMING_MODE_LIMITED 1 ///< Set user top limit
294#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
295
296/* POWER_DOWN_MODE */
297#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
298#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
299
300/*
301 * Agesa optional capabilities selection.
302 * Uncomment and mark FALSE those features you wish to include in the build.
303 * Comment out or mark TRUE those features you want to REMOVE from the build.
304 */
305
306#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
307#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
308#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
309#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
310#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
311#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
312#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
313#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
314#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
315#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
316#define DFLT_HPET_BASE_ADDRESS 0xFED00000
317#define DFLT_SMI_CMD_PORT 0xB0
318#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
319#define DFLT_GEC_BASE_ADDRESS 0xFED61000
320#define DFLT_AZALIA_SSID 0x780D1022
321#define DFLT_SMBUS_SSID 0x780B1022
322#define DFLT_IDE_SSID 0x780C1022
323#define DFLT_SATA_AHCI_SSID 0x78011022
324#define DFLT_SATA_IDE_SSID 0x78001022
325#define DFLT_SATA_RAID5_SSID 0x78031022
326#define DFLT_SATA_RAID_SSID 0x78021022
327#define DFLT_EHCI_SSID 0x78081022
328#define DFLT_OHCI_SSID 0x78071022
329#define DFLT_LPC_SSID 0x780E1022
330#define DFLT_SD_SSID 0x78061022
331#define DFLT_XHCI_SSID 0x78121022
332#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
333#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
334#define DFLT_FCH_GPP_LINK_CONFIG PortA4
335#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
336#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
337#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
338#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
339#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
340#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
341#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
342#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
343//#define BLDCFG_IR_PIN_CONTROL 0x33
344
Alexandru Gagniuc5405d3f2014-04-09 16:14:25 -0500[diff] [blame^]345/*
346 * The GPIO control is not well documented in AGESA, but is in the BKDG
347 *
348 * Eg. FANIN1/GPIO57 on datasheet means power-on default (Function0) is to route
349 * from this ball to hardware monitor as FAN1 tacho input. Selecting Function1
350 * routes this to the GPIO block instead. Seems ACPI GPIOs and related GEVENTs
351 * are mostly in Function1, sometimes Function2.
352 *
353 * Note that the GpioOut bit does not mean that the GPIO is an output. That bit
354 * actually controls the output value, so GpioOut means "default to set".
355 * PullUpB is an inverted logic, so setting this bit means we're actually
356 * disabling the internal pull-up. The PullDown bit is NOT inverted logic.
357 * The output driver can be disabled with the GpioOutEnB bit, which is again,
358 * inverted logic. To make the list more readable, we define a few local macros
359 * to state what we mean.
360 */
361#define OUTPUT_HIGH (GpioOut)
362#define OUTPUT_LOW (0)
363#define INPUT (GpioOutEnB)
364#define PULL_UP (0)
365#define PULL_DOWN (PullDown | PullUpB)
366#define PULL_NONE (PullUpB)
367
368GPIO_CONTROL pavilion_m6_1035dx_gpio[] = {
369 {57, Function1, OUTPUT_HIGH | PULL_NONE}, /* WLAN enable */
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]370 {-1}
371};
Alexandru Gagniuc5405d3f2014-04-09 16:14:25 -0500[diff] [blame^]372#define BLDCFG_FCH_GPIO_CONTROL_LIST (&pavilion_m6_1035dx_gpio[0])
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]373
374// The following definitions specify the default values for various parameters in which there are
375// no clearly defined defaults to be used in the common file. The values below are based on product
376// and BKDG content, please consult the AGESA Memory team for consultation.
377#define DFLT_SCRUB_DRAM_RATE (0)
378#define DFLT_SCRUB_L2_RATE (0)
379#define DFLT_SCRUB_L3_RATE (0)
380#define DFLT_SCRUB_IC_RATE (0)
381#define DFLT_SCRUB_DC_RATE (0)
382#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
383#define DFLT_VRM_SLEW_RATE (5000)
384
Alexandru Gagniuc1d87dac2014-03-28 14:48:13 -0500[diff] [blame]385/* AGESA nonsense: this header depends on the definitions above */
386#include <vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h>
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]387
388/*----------------------------------------------------------------------------------------
389 * CUSTOMER OVERIDES MEMORY TABLE
390 *----------------------------------------------------------------------------------------
391 */
392
393/*
Alexandru Gagniuc0b2fa342014-04-05 18:51:33 -0500[diff] [blame]394 * Platform Specific Overriding Table allows IBV/OEM to pass in platform
395 * information to AGESA
396 * (e.g. MemClk routing, the number of DIMM slots per channel,...).
397 * If PlatformSpecificTable is populated, AGESA will base its settings on the
398 * data from the table. Otherwise, it will use its default conservative settings
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]399 */
400CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
Alexandru Gagniuc0b2fa342014-04-05 18:51:33 -0500[diff] [blame]401
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]402 NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
403 NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
404 MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
405 CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A),
406 ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00),
407 CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
408
409 PSO_END
410};
411
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]412// Customer table
413UINT8 AGESA_MEM_TABLE_TN[][sizeof (MEM_TABLE_ALIAS)] =
414{
Alexandru Gagniucfccfee32014-03-26 18:51:08 -0500[diff] [blame]415 NBACCESS (MTEnd, 0, 0, 0, 0, 0), // End of Table
416};
417UINT8 SizeOfTableTN = sizeof (AGESA_MEM_TABLE_TN) / sizeof (AGESA_MEM_TABLE_TN[0]);