Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | chip soc/amd/cezanne |
Mathew King | c44cc19 | 2021-02-23 14:15:50 -0700 | [diff] [blame] | 3 | |
Karthikeyan Ramasubramanian | e71a6ee | 2021-04-23 09:51:41 -0600 | [diff] [blame] | 4 | register "common_config.acp_config" = "{ |
| 5 | .acp_pin_cfg = I2S_PINS_I2S_TDM, |
| 6 | .acp_i2s_wake_enable = 0, |
| 7 | .acp_pme_enable = 0, |
Karthikeyan Ramasubramanian | 6ce71e3 | 2021-05-27 16:34:29 -0600 | [diff] [blame] | 8 | .dmic_present = 1, |
Karthikeyan Ramasubramanian | e71a6ee | 2021-04-23 09:51:41 -0600 | [diff] [blame] | 9 | }" |
| 10 | |
Mathew King | c44cc19 | 2021-02-23 14:15:50 -0700 | [diff] [blame] | 11 | # eSPI Configuration |
| 12 | register "common_config.espi_config" = "{ |
| 13 | .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, |
| 14 | .generic_io_range[0] = { |
| 15 | .base = 0x62, |
| 16 | /* |
| 17 | * Only 0x62 and 0x66 are required. But, this is not supported by |
| 18 | * standard IO decodes and there are only 4 generic I/O windows |
| 19 | * available. Hence, open a window from 0x62-0x67. |
| 20 | */ |
| 21 | .size = 5, |
| 22 | }, |
| 23 | .generic_io_range[1] = { |
| 24 | .base = 0x800, /* EC_HOST_CMD_REGION0 */ |
| 25 | .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ |
| 26 | }, |
| 27 | .generic_io_range[2] = { |
| 28 | .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ |
| 29 | .size = 255, /* EC_MEMMAP_SIZE */ |
| 30 | }, |
| 31 | .generic_io_range[3] = { |
| 32 | .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ |
| 33 | .size = 8, /* 0x200 - 0x207 */ |
| 34 | }, |
| 35 | |
| 36 | .io_mode = ESPI_IO_MODE_QUAD, |
Rob Barnes | 20d689f | 2021-04-15 17:31:01 -0600 | [diff] [blame] | 37 | .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, |
Mathew King | c44cc19 | 2021-02-23 14:15:50 -0700 | [diff] [blame] | 38 | .crc_check_enable = 1, |
Rob Barnes | 888f303 | 2021-09-02 08:52:42 -0600 | [diff] [blame] | 39 | .alert_pin = ESPI_ALERT_PIN_OPEN_DRAIN, |
Mathew King | c44cc19 | 2021-02-23 14:15:50 -0700 | [diff] [blame] | 40 | .periph_ch_en = 1, |
| 41 | .vw_ch_en = 1, |
| 42 | .oob_ch_en = 0, |
| 43 | .flash_ch_en = 0, |
| 44 | |
Raul E Rangel | 5804aa3 | 2021-04-06 15:51:46 -0600 | [diff] [blame] | 45 | .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1), |
Mathew King | c44cc19 | 2021-02-23 14:15:50 -0700 | [diff] [blame] | 46 | }" |
| 47 | |
Karthikeyan Ramasubramanian | b6a4476 | 2021-04-22 17:03:56 -0600 | [diff] [blame] | 48 | # Enable S0i3 support |
| 49 | register "s0ix_enable" = "1" |
| 50 | |
Jason Glenesk | 87f2073 | 2021-06-11 12:09:20 -0700 | [diff] [blame] | 51 | # Enable STT support |
| 52 | register "stt_control" = "1" |
| 53 | register "stt_pcb_sensor_count" = "2" |
| 54 | register "stt_min_limit" = "0" |
| 55 | register "stt_m1" = "0x0319" |
| 56 | register "stt_m2" = "0x01A0" |
| 57 | register "stt_m3" = "0" |
| 58 | register "stt_m4" = "0" |
| 59 | register "stt_m5" = "0" |
| 60 | register "stt_m6" = "0" |
| 61 | register "stt_c_apu" = "0xE99F" |
| 62 | register "stt_c_gpu" = "0" |
| 63 | register "stt_c_hs2" = "0" |
| 64 | register "stt_alpha_apu" = "0xCCD" |
| 65 | register "stt_alpha_gpu" = "0" |
| 66 | register "stt_alpha_hs2" = "0" |
| 67 | register "stt_skin_temp_apu" = "0x2D00" |
| 68 | register "stt_skin_temp_gpu" = "0" |
| 69 | register "stt_skin_temp_hs2" = "0" |
| 70 | register "stt_error_coeff" = "0xD" |
| 71 | register "stt_error_rate_coefficient" = "0x8F6" |
| 72 | |
Martin Roth | e5b85c3 | 2021-04-26 16:04:51 -0600 | [diff] [blame] | 73 | register "system_configuration" = "2" |
| 74 | |
Karthikeyan Ramasubramanian | 699a709 | 2021-03-15 06:42:15 -0600 | [diff] [blame] | 75 | register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | |
| 76 | GPIO_I2C2_SCL | GPIO_I2C3_SCL" |
Karthikeyan Ramasubramanian | fec4db9 | 2021-06-02 16:14:39 -0600 | [diff] [blame] | 77 | # I2C Pad Control RX Select Configuration |
| 78 | register "i2c_pad_ctrl_rx_sel[0]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Trackpad |
| 79 | register "i2c_pad_ctrl_rx_sel[1]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Touchscreen |
| 80 | register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" # Audio/SAR |
| 81 | register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_1_8V" # GSC |
Karthikeyan Ramasubramanian | 699a709 | 2021-03-15 06:42:15 -0600 | [diff] [blame] | 82 | |
Patrick Huang | 25fc070 | 2021-08-10 17:52:01 +0800 | [diff] [blame] | 83 | # genral purpose PCIe clock output configuration |
| 84 | register "gpp_clk_config[0]" = "GPP_CLK_REQ" |
| 85 | register "gpp_clk_config[1]" = "GPP_CLK_REQ" |
| 86 | register "gpp_clk_config[2]" = "GPP_CLK_REQ" |
| 87 | register "gpp_clk_config[3]" = "GPP_CLK_REQ" |
| 88 | register "gpp_clk_config[4]" = "GPP_CLK_OFF" |
| 89 | register "gpp_clk_config[5]" = "GPP_CLK_OFF" |
| 90 | register "gpp_clk_config[6]" = "GPP_CLK_OFF" |
| 91 | |
Matt Papageorge | 5a2feed | 2021-07-20 15:09:46 -0500 | [diff] [blame] | 92 | register "pspp_policy" = "DXIO_PSPP_BALANCED" |
Felix Held | a7c410b | 2021-05-25 20:51:35 +0200 | [diff] [blame] | 93 | |
Julian Schroeder | cf2c99f | 2021-05-21 14:56:00 -0500 | [diff] [blame] | 94 | register "usb_phy_custom" = "1" |
| 95 | register "usb_phy" = "{ |
Rob Barnes | 058048c0 | 2021-07-28 11:33:22 -0600 | [diff] [blame] | 96 | /* Left USB C0 Port */ |
Julian Schroeder | cf2c99f | 2021-05-21 14:56:00 -0500 | [diff] [blame] | 97 | .Usb2PhyPort[0] = { |
| 98 | .compdstune = 3, |
| 99 | .sqrxtune = 3, |
| 100 | .txfslstune = 3, |
| 101 | .txpreempamptune = 1, |
| 102 | .txpreemppulsetune = 0, |
| 103 | .txrisetune = 1, |
| 104 | .txvreftune = 6, |
| 105 | .txhsxvtune = 3, |
| 106 | .txrestune = 1, |
| 107 | }, |
Rob Barnes | 058048c0 | 2021-07-28 11:33:22 -0600 | [diff] [blame] | 108 | /* Left USB A0 Port or WWAN */ |
Julian Schroeder | cf2c99f | 2021-05-21 14:56:00 -0500 | [diff] [blame] | 109 | .Usb2PhyPort[1] = { |
| 110 | .compdstune = 3, |
| 111 | .sqrxtune = 3, |
| 112 | .txfslstune = 3, |
| 113 | .txpreempamptune = 1, |
| 114 | .txpreemppulsetune = 0, |
| 115 | .txrisetune = 1, |
| 116 | .txvreftune = 6, |
| 117 | .txhsxvtune = 3, |
| 118 | .txrestune = 1, |
| 119 | }, |
Rob Barnes | 058048c0 | 2021-07-28 11:33:22 -0600 | [diff] [blame] | 120 | /* User facing camera */ |
Julian Schroeder | cf2c99f | 2021-05-21 14:56:00 -0500 | [diff] [blame] | 121 | .Usb2PhyPort[2] = { |
| 122 | .compdstune = 1, |
| 123 | .sqrxtune = 3, |
| 124 | .txfslstune = 3, |
| 125 | .txpreempamptune = 2, |
| 126 | .txpreemppulsetune = 0, |
| 127 | .txrisetune = 2, |
| 128 | .txvreftune = 3, |
| 129 | .txhsxvtune = 3, |
| 130 | .txrestune = 2, |
| 131 | }, |
Rob Barnes | 058048c0 | 2021-07-28 11:33:22 -0600 | [diff] [blame] | 132 | /* World facing camera */ |
Julian Schroeder | cf2c99f | 2021-05-21 14:56:00 -0500 | [diff] [blame] | 133 | .Usb2PhyPort[3] = { |
| 134 | .compdstune = 1, |
| 135 | .sqrxtune = 3, |
| 136 | .txfslstune = 3, |
| 137 | .txpreempamptune = 2, |
| 138 | .txpreemppulsetune = 0, |
| 139 | .txrisetune = 2, |
| 140 | .txvreftune = 3, |
| 141 | .txhsxvtune = 3, |
| 142 | .txrestune = 2, |
| 143 | }, |
Rob Barnes | 058048c0 | 2021-07-28 11:33:22 -0600 | [diff] [blame] | 144 | /* Right USB C1 Port */ |
Julian Schroeder | cf2c99f | 2021-05-21 14:56:00 -0500 | [diff] [blame] | 145 | .Usb2PhyPort[4] = { |
| 146 | .compdstune = 3, |
| 147 | .sqrxtune = 3, |
| 148 | .txfslstune = 3, |
| 149 | .txpreempamptune = 1, |
| 150 | .txpreemppulsetune = 0, |
| 151 | .txrisetune = 1, |
| 152 | .txvreftune = 6, |
| 153 | .txhsxvtune = 3, |
| 154 | .txrestune = 1, |
| 155 | }, |
Rob Barnes | 058048c0 | 2021-07-28 11:33:22 -0600 | [diff] [blame] | 156 | /* Right USB A1 Port */ |
Julian Schroeder | cf2c99f | 2021-05-21 14:56:00 -0500 | [diff] [blame] | 157 | .Usb2PhyPort[5] = { |
Ivy Jian | 13bf4dd | 2021-08-12 12:06:38 +0800 | [diff] [blame] | 158 | .compdstune = 5, |
Julian Schroeder | cf2c99f | 2021-05-21 14:56:00 -0500 | [diff] [blame] | 159 | .sqrxtune = 3, |
| 160 | .txfslstune = 3, |
| 161 | .txpreempamptune = 1, |
| 162 | .txpreemppulsetune = 0, |
| 163 | .txrisetune = 1, |
Ivy Jian | 13bf4dd | 2021-08-12 12:06:38 +0800 | [diff] [blame] | 164 | .txvreftune = 9, |
Julian Schroeder | cf2c99f | 2021-05-21 14:56:00 -0500 | [diff] [blame] | 165 | .txhsxvtune = 3, |
| 166 | .txrestune = 1, |
| 167 | }, |
Rob Barnes | 058048c0 | 2021-07-28 11:33:22 -0600 | [diff] [blame] | 168 | /* WiFi / Bluetooth */ |
Julian Schroeder | cf2c99f | 2021-05-21 14:56:00 -0500 | [diff] [blame] | 169 | .Usb2PhyPort[6] = { |
| 170 | .compdstune = 1, |
| 171 | .sqrxtune = 3, |
| 172 | .txfslstune = 3, |
| 173 | .txpreempamptune = 2, |
| 174 | .txpreemppulsetune = 0, |
| 175 | .txrisetune = 2, |
| 176 | .txvreftune = 3, |
| 177 | .txhsxvtune = 3, |
| 178 | .txrestune = 2, |
| 179 | }, |
Rob Barnes | 058048c0 | 2021-07-28 11:33:22 -0600 | [diff] [blame] | 180 | /* Smart Card */ |
Julian Schroeder | cf2c99f | 2021-05-21 14:56:00 -0500 | [diff] [blame] | 181 | .Usb2PhyPort[7] = { |
| 182 | .compdstune = 1, |
| 183 | .sqrxtune = 3, |
| 184 | .txfslstune = 3, |
| 185 | .txpreempamptune = 2, |
| 186 | .txpreemppulsetune = 0, |
| 187 | .txrisetune = 2, |
| 188 | .txvreftune = 3, |
| 189 | .txhsxvtune = 3, |
| 190 | .txrestune = 2, |
| 191 | }, |
Rob Barnes | 058048c0 | 2021-07-28 11:33:22 -0600 | [diff] [blame] | 192 | /* Left USB C0 Port */ |
Julian Schroeder | cf2c99f | 2021-05-21 14:56:00 -0500 | [diff] [blame] | 193 | .Usb3PhyPort[0] = { |
| 194 | .tx_term_ctrl=2, |
| 195 | .rx_term_ctrl=2, |
| 196 | .tx_vboost_lvl_en=1, |
| 197 | .tx_vboost_lvl=5, |
| 198 | }, |
Rob Barnes | 058048c0 | 2021-07-28 11:33:22 -0600 | [diff] [blame] | 199 | /* Left USB A0 Port or WWAN */ |
Julian Schroeder | cf2c99f | 2021-05-21 14:56:00 -0500 | [diff] [blame] | 200 | .Usb3PhyPort[1] = { |
| 201 | .tx_term_ctrl=2, |
| 202 | .rx_term_ctrl=2, |
| 203 | .tx_vboost_lvl_en=1, |
| 204 | .tx_vboost_lvl=5, |
| 205 | }, |
Rob Barnes | 058048c0 | 2021-07-28 11:33:22 -0600 | [diff] [blame] | 206 | /* Right USB C1 Port */ |
Julian Schroeder | cf2c99f | 2021-05-21 14:56:00 -0500 | [diff] [blame] | 207 | .Usb3PhyPort[2] = { |
| 208 | .tx_term_ctrl=2, |
| 209 | .rx_term_ctrl=2, |
| 210 | .tx_vboost_lvl_en=1, |
| 211 | .tx_vboost_lvl=5, |
| 212 | }, |
Rob Barnes | 058048c0 | 2021-07-28 11:33:22 -0600 | [diff] [blame] | 213 | /* Right USB A1 Port */ |
Julian Schroeder | cf2c99f | 2021-05-21 14:56:00 -0500 | [diff] [blame] | 214 | .Usb3PhyPort[3] = { |
| 215 | .tx_term_ctrl=2, |
| 216 | .rx_term_ctrl=2, |
| 217 | .tx_vboost_lvl_en=1, |
| 218 | .tx_vboost_lvl=5, |
| 219 | }, |
Julian Schroeder | cf2c99f | 2021-05-21 14:56:00 -0500 | [diff] [blame] | 220 | .ComboPhyStaticConfig[0] = 0, |
| 221 | .ComboPhyStaticConfig[1] = 0, |
Julian Schroeder | cf2c99f | 2021-05-21 14:56:00 -0500 | [diff] [blame] | 222 | .BatteryChargerEnable = 0, |
| 223 | .PhyP3CpmP4Support = 0, |
| 224 | }" |
| 225 | |
Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 226 | device domain 0 on |
Raul E Rangel | 3acc515 | 2021-06-09 13:36:10 -0600 | [diff] [blame] | 227 | device ref iommu on end |
| 228 | |
Karthikeyan Ramasubramanian | 24abd3e | 2021-05-04 16:19:32 -0600 | [diff] [blame] | 229 | device ref gpp_bridge_0 on |
| 230 | chip drivers/wifi/generic |
| 231 | register "wake" = "GEVENT_8" |
| 232 | device pci 00.0 on end |
| 233 | end |
| 234 | end # WLAN |
Mathew King | 095bdec | 2021-03-12 14:01:22 -0700 | [diff] [blame] | 235 | device ref gpp_bridge_1 on end # SD |
| 236 | device ref gpp_bridge_2 on end # WWAN |
Raul E Rangel | c54968d | 2021-05-26 17:04:14 -0600 | [diff] [blame] | 237 | device ref gpp_bridge_3 on |
| 238 | # Required so the NVMe gets placed into D3 when entering S0i3. |
| 239 | chip drivers/pcie/rtd3/device |
| 240 | register "name" = ""NVME"" |
| 241 | device pci 00.0 on end |
| 242 | end |
| 243 | end # NVMe |
Mathew King | 095bdec | 2021-03-12 14:01:22 -0700 | [diff] [blame] | 244 | |
Mathew King | abc6971 | 2021-03-03 16:36:46 -0700 | [diff] [blame] | 245 | device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A |
Raul Rangel | ca25ad5 | 2021-04-06 15:33:16 +0000 | [diff] [blame] | 246 | device ref gfx on end # Internal GPU (GFX) |
Karthikeyan Ramasubramanian | f6b2a1c | 2021-05-04 00:38:22 -0600 | [diff] [blame] | 247 | device ref gfx_hda on end # GFX HD Audio Controller |
Felix Held | 1028a41 | 2021-05-26 22:48:30 +0200 | [diff] [blame] | 248 | device ref crypto on end # Crypto Coprocessor |
Mathew King | 238242b | 2021-03-04 08:24:55 -0700 | [diff] [blame] | 249 | device ref xhci_0 on # USB 3.1 (USB0) |
| 250 | chip drivers/usb/acpi |
| 251 | device ref xhci_0_root_hub on |
| 252 | chip drivers/usb/acpi |
Rob Barnes | 9cdc72a | 2021-07-28 11:33:22 -0600 | [diff] [blame^] | 253 | register "desc" = ""Left Type-C Port"" |
Mathew King | 238242b | 2021-03-04 08:24:55 -0700 | [diff] [blame] | 254 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 255 | register "group" = "ACPI_PLD_GROUP(1, 1)" |
| 256 | device ref usb3_port0 on end |
| 257 | end |
| 258 | chip drivers/usb/acpi |
Rob Barnes | 9cdc72a | 2021-07-28 11:33:22 -0600 | [diff] [blame^] | 259 | register "desc" = ""Left Type-A Port"" |
Mathew King | 238242b | 2021-03-04 08:24:55 -0700 | [diff] [blame] | 260 | register "type" = "UPC_TYPE_USB3_A" |
| 261 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 262 | device ref usb3_port1 on end |
| 263 | end |
| 264 | chip drivers/usb/acpi |
Rob Barnes | 9cdc72a | 2021-07-28 11:33:22 -0600 | [diff] [blame^] | 265 | register "desc" = ""Left Type-C Port"" |
Mathew King | 238242b | 2021-03-04 08:24:55 -0700 | [diff] [blame] | 266 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 267 | register "group" = "ACPI_PLD_GROUP(1, 1)" |
| 268 | device ref usb2_port0 on end |
| 269 | end |
| 270 | chip drivers/usb/acpi |
Rob Barnes | 9cdc72a | 2021-07-28 11:33:22 -0600 | [diff] [blame^] | 271 | register "desc" = ""Left Type-A Port"" |
Mathew King | 238242b | 2021-03-04 08:24:55 -0700 | [diff] [blame] | 272 | register "type" = "UPC_TYPE_USB3_A" |
| 273 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 274 | device ref usb2_port1 on end |
| 275 | end |
| 276 | chip drivers/usb/acpi |
| 277 | register "desc" = ""User-Facing Camera"" |
| 278 | register "type" = "UPC_TYPE_INTERNAL" |
| 279 | device ref usb2_port2 on end |
| 280 | end |
| 281 | chip drivers/usb/acpi |
| 282 | register "desc" = ""World-Facing Camera"" |
| 283 | register "type" = "UPC_TYPE_INTERNAL" |
| 284 | device ref usb2_port3 on end |
| 285 | end |
| 286 | end |
| 287 | end |
| 288 | end |
| 289 | device ref xhci_1 on # USB 3.1 (USB1) |
| 290 | chip drivers/usb/acpi |
| 291 | device ref xhci_1_root_hub on |
| 292 | chip drivers/usb/acpi |
Rob Barnes | 9cdc72a | 2021-07-28 11:33:22 -0600 | [diff] [blame^] | 293 | register "desc" = ""Right Type-C Port"" |
Mathew King | 238242b | 2021-03-04 08:24:55 -0700 | [diff] [blame] | 294 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 295 | register "group" = "ACPI_PLD_GROUP(2, 2)" |
| 296 | device ref usb3_port4 on end |
| 297 | end |
| 298 | chip drivers/usb/acpi |
Rob Barnes | 9cdc72a | 2021-07-28 11:33:22 -0600 | [diff] [blame^] | 299 | register "desc" = ""Right Type-A Port"" |
Mathew King | 238242b | 2021-03-04 08:24:55 -0700 | [diff] [blame] | 300 | register "type" = "UPC_TYPE_USB3_A" |
| 301 | register "group" = "ACPI_PLD_GROUP(2, 1)" |
| 302 | device ref usb3_port5 on end |
| 303 | end |
| 304 | chip drivers/usb/acpi |
Rob Barnes | 9cdc72a | 2021-07-28 11:33:22 -0600 | [diff] [blame^] | 305 | register "desc" = ""Right Type-C Port"" |
Mathew King | 238242b | 2021-03-04 08:24:55 -0700 | [diff] [blame] | 306 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 307 | register "group" = "ACPI_PLD_GROUP(2, 2)" |
| 308 | device ref usb2_port4 on end |
| 309 | end |
| 310 | chip drivers/usb/acpi |
Rob Barnes | 9cdc72a | 2021-07-28 11:33:22 -0600 | [diff] [blame^] | 311 | register "desc" = ""Right Type-A Port"" |
Mathew King | 238242b | 2021-03-04 08:24:55 -0700 | [diff] [blame] | 312 | register "type" = "UPC_TYPE_USB3_A" |
| 313 | register "group" = "ACPI_PLD_GROUP(2, 1)" |
| 314 | device ref usb2_port5 on end |
| 315 | end |
| 316 | chip drivers/usb/acpi |
| 317 | register "desc" = ""Bluetooth"" |
| 318 | register "type" = "UPC_TYPE_INTERNAL" |
Karthikeyan Ramasubramanian | d84ce40 | 2021-03-30 16:27:59 -0600 | [diff] [blame] | 319 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_132)" |
Mathew King | 238242b | 2021-03-04 08:24:55 -0700 | [diff] [blame] | 320 | device ref usb2_port6 on end |
| 321 | end |
| 322 | end |
| 323 | end |
| 324 | end |
Karthikeyan Ramasubramanian | e71a6ee | 2021-04-23 09:51:41 -0600 | [diff] [blame] | 325 | device ref acp on |
| 326 | chip drivers/amd/i2s_machine_dev |
Yu-Hsuan Hsu | 45c46b6 | 2021-06-15 14:52:03 +0800 | [diff] [blame] | 327 | register "hid" = ""AMDI1019"" |
Karthikeyan Ramasubramanian | e71a6ee | 2021-04-23 09:51:41 -0600 | [diff] [blame] | 328 | device generic 0.0 on end |
| 329 | end |
| 330 | end # Audio |
Mathew King | abc6971 | 2021-03-03 16:36:46 -0700 | [diff] [blame] | 331 | end |
Mathew King | 78f0301 | 2021-03-05 09:04:44 -0700 | [diff] [blame] | 332 | |
| 333 | device ref lpc_bridge on |
| 334 | chip ec/google/chromeec |
Raul E Rangel | ba10223 | 2021-05-12 17:07:39 -0600 | [diff] [blame] | 335 | device pnp 0c09.0 alias chrome_ec on end |
Mathew King | 78f0301 | 2021-03-05 09:04:44 -0700 | [diff] [blame] | 336 | end |
| 337 | end |
Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 338 | end # domain |
Karthikeyan Ramasubramanian | 8f7fca5 | 2021-03-15 10:31:37 -0600 | [diff] [blame] | 339 | |
| 340 | device ref i2c_3 on |
| 341 | chip drivers/i2c/tpm |
| 342 | register "hid" = ""GOOG0005"" |
| 343 | register "desc" = ""Cr50 TPM"" |
| 344 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" |
| 345 | device i2c 50 on end |
| 346 | end |
| 347 | end |
Ivy Jian | a7696ad | 2021-04-13 14:04:12 +0800 | [diff] [blame] | 348 | |
| 349 | device ref uart_0 on end # UART0 |
| 350 | |
Raul E Rangel | ba10223 | 2021-05-12 17:07:39 -0600 | [diff] [blame] | 351 | # See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/baseboard/guybrush/baseboard.c;l=221 |
| 352 | # for the EC configuration. |
| 353 | # |
| 354 | # EC is configured to power off the system at 105C, so add a two degree |
| 355 | # buffer so the OS can gracefully shutdown. |
| 356 | # |
| 357 | # EC is configured to assert PROCHOT at 100C. That drastically lowers |
| 358 | # performance. Instead we will tell the OS to start throttling the CPUs |
| 359 | # at 95C in hopes that we don't hit the PROCHOT limit. |
| 360 | # |
| 361 | # We set use_acpi1_thermal_zone_scope because the Chrome ec.asl |
| 362 | # performs a `Notify` to the `_\TZ` scope. |
| 363 | chip drivers/acpi/thermal_zone |
| 364 | register "description" = ""SOC"" |
| 365 | use chrome_ec as temperature_controller |
| 366 | register "sensor_id" = "0" |
| 367 | register "polling_period" = "10" |
| 368 | register "critical_temperature" = "103" |
| 369 | register "passive_config.temperature" = "95" |
| 370 | register "use_acpi1_thermal_zone_scope" = "true" |
| 371 | |
| 372 | device generic 0 on end |
| 373 | end |
| 374 | chip drivers/acpi/thermal_zone |
| 375 | register "description" = ""Charger"" |
| 376 | use chrome_ec as temperature_controller |
| 377 | register "sensor_id" = "1" |
| 378 | register "polling_period" = "10" |
| 379 | register "critical_temperature" = "103" |
| 380 | register "passive_config.temperature" = "95" |
| 381 | register "use_acpi1_thermal_zone_scope" = "true" |
| 382 | |
| 383 | device generic 1 on end |
| 384 | end |
| 385 | chip drivers/acpi/thermal_zone |
| 386 | register "description" = ""Memory"" |
| 387 | use chrome_ec as temperature_controller |
| 388 | register "sensor_id" = "2" |
| 389 | register "polling_period" = "10" |
| 390 | register "critical_temperature" = "103" |
| 391 | register "passive_config.temperature" = "95" |
| 392 | register "use_acpi1_thermal_zone_scope" = "true" |
| 393 | |
| 394 | device generic 2 on end |
| 395 | end |
| 396 | chip drivers/acpi/thermal_zone |
| 397 | register "description" = ""CPU"" |
| 398 | use chrome_ec as temperature_controller |
| 399 | register "sensor_id" = "3" |
| 400 | register "polling_period" = "10" |
| 401 | register "critical_temperature" = "103" |
| 402 | register "passive_config.temperature" = "95" |
| 403 | register "use_acpi1_thermal_zone_scope" = "true" |
| 404 | |
| 405 | device generic 3 on end |
| 406 | end |
Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 407 | end # chip soc/amd/cezanne |