Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | chip soc/amd/cezanne |
Mathew King | c44cc19 | 2021-02-23 14:15:50 -0700 | [diff] [blame] | 3 | |
Karthikeyan Ramasubramanian | e71a6ee | 2021-04-23 09:51:41 -0600 | [diff] [blame] | 4 | register "common_config.acp_config" = "{ |
| 5 | .acp_pin_cfg = I2S_PINS_I2S_TDM, |
| 6 | .acp_i2s_wake_enable = 0, |
| 7 | .acp_pme_enable = 0, |
| 8 | }" |
| 9 | |
Mathew King | c44cc19 | 2021-02-23 14:15:50 -0700 | [diff] [blame] | 10 | # eSPI Configuration |
| 11 | register "common_config.espi_config" = "{ |
| 12 | .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X60_0X64_EN, |
| 13 | .generic_io_range[0] = { |
| 14 | .base = 0x62, |
| 15 | /* |
| 16 | * Only 0x62 and 0x66 are required. But, this is not supported by |
| 17 | * standard IO decodes and there are only 4 generic I/O windows |
| 18 | * available. Hence, open a window from 0x62-0x67. |
| 19 | */ |
| 20 | .size = 5, |
| 21 | }, |
| 22 | .generic_io_range[1] = { |
| 23 | .base = 0x800, /* EC_HOST_CMD_REGION0 */ |
| 24 | .size = 256, /* EC_HOST_CMD_REGION_SIZE * 2 */ |
| 25 | }, |
| 26 | .generic_io_range[2] = { |
| 27 | .base = 0x900, /* EC_LPC_ADDR_MEMMAP */ |
| 28 | .size = 255, /* EC_MEMMAP_SIZE */ |
| 29 | }, |
| 30 | .generic_io_range[3] = { |
| 31 | .base = 0x200, /* EC_LPC_ADDR_HOST_DATA */ |
| 32 | .size = 8, /* 0x200 - 0x207 */ |
| 33 | }, |
| 34 | |
| 35 | .io_mode = ESPI_IO_MODE_QUAD, |
Rob Barnes | 20d689f | 2021-04-15 17:31:01 -0600 | [diff] [blame] | 36 | .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, |
Mathew King | c44cc19 | 2021-02-23 14:15:50 -0700 | [diff] [blame] | 37 | .crc_check_enable = 1, |
Raul E Rangel | f33f857 | 2021-05-05 13:41:24 -0600 | [diff] [blame] | 38 | .alert_pin = ESPI_ALERT_PIN_IN_BAND, |
Mathew King | c44cc19 | 2021-02-23 14:15:50 -0700 | [diff] [blame] | 39 | .periph_ch_en = 1, |
| 40 | .vw_ch_en = 1, |
| 41 | .oob_ch_en = 0, |
| 42 | .flash_ch_en = 0, |
| 43 | |
Raul E Rangel | 5804aa3 | 2021-04-06 15:51:46 -0600 | [diff] [blame] | 44 | .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1), |
Mathew King | c44cc19 | 2021-02-23 14:15:50 -0700 | [diff] [blame] | 45 | }" |
| 46 | |
Karthikeyan Ramasubramanian | b6a4476 | 2021-04-22 17:03:56 -0600 | [diff] [blame] | 47 | # Enable S0i3 support |
| 48 | register "s0ix_enable" = "1" |
| 49 | |
Martin Roth | e5b85c3 | 2021-04-26 16:04:51 -0600 | [diff] [blame] | 50 | register "system_configuration" = "2" |
| 51 | |
Karthikeyan Ramasubramanian | 699a709 | 2021-03-15 06:42:15 -0600 | [diff] [blame] | 52 | register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | |
| 53 | GPIO_I2C2_SCL | GPIO_I2C3_SCL" |
| 54 | |
Felix Held | a7c410b | 2021-05-25 20:51:35 +0200 | [diff] [blame] | 55 | register "pspp_policy" = "DXIO_PSPP_POWERSAVE" |
| 56 | |
Julian Schroeder | cf2c99f | 2021-05-21 14:56:00 -0500 | [diff] [blame] | 57 | register "usb_phy_custom" = "1" |
| 58 | register "usb_phy" = "{ |
| 59 | .Usb2PhyPort[0] = { |
| 60 | .compdstune = 3, |
| 61 | .sqrxtune = 3, |
| 62 | .txfslstune = 3, |
| 63 | .txpreempamptune = 1, |
| 64 | .txpreemppulsetune = 0, |
| 65 | .txrisetune = 1, |
| 66 | .txvreftune = 6, |
| 67 | .txhsxvtune = 3, |
| 68 | .txrestune = 1, |
| 69 | }, |
| 70 | .Usb2PhyPort[1] = { |
| 71 | .compdstune = 3, |
| 72 | .sqrxtune = 3, |
| 73 | .txfslstune = 3, |
| 74 | .txpreempamptune = 1, |
| 75 | .txpreemppulsetune = 0, |
| 76 | .txrisetune = 1, |
| 77 | .txvreftune = 6, |
| 78 | .txhsxvtune = 3, |
| 79 | .txrestune = 1, |
| 80 | }, |
| 81 | .Usb2PhyPort[2] = { |
| 82 | .compdstune = 1, |
| 83 | .sqrxtune = 3, |
| 84 | .txfslstune = 3, |
| 85 | .txpreempamptune = 2, |
| 86 | .txpreemppulsetune = 0, |
| 87 | .txrisetune = 2, |
| 88 | .txvreftune = 3, |
| 89 | .txhsxvtune = 3, |
| 90 | .txrestune = 2, |
| 91 | }, |
| 92 | .Usb2PhyPort[3] = { |
| 93 | .compdstune = 1, |
| 94 | .sqrxtune = 3, |
| 95 | .txfslstune = 3, |
| 96 | .txpreempamptune = 2, |
| 97 | .txpreemppulsetune = 0, |
| 98 | .txrisetune = 2, |
| 99 | .txvreftune = 3, |
| 100 | .txhsxvtune = 3, |
| 101 | .txrestune = 2, |
| 102 | }, |
| 103 | .Usb2PhyPort[4] = { |
| 104 | .compdstune = 3, |
| 105 | .sqrxtune = 3, |
| 106 | .txfslstune = 3, |
| 107 | .txpreempamptune = 1, |
| 108 | .txpreemppulsetune = 0, |
| 109 | .txrisetune = 1, |
| 110 | .txvreftune = 6, |
| 111 | .txhsxvtune = 3, |
| 112 | .txrestune = 1, |
| 113 | }, |
| 114 | .Usb2PhyPort[5] = { |
| 115 | .compdstune = 3, |
| 116 | .sqrxtune = 3, |
| 117 | .txfslstune = 3, |
| 118 | .txpreempamptune = 1, |
| 119 | .txpreemppulsetune = 0, |
| 120 | .txrisetune = 1, |
| 121 | .txvreftune = 6, |
| 122 | .txhsxvtune = 3, |
| 123 | .txrestune = 1, |
| 124 | }, |
| 125 | .Usb2PhyPort[6] = { |
| 126 | .compdstune = 1, |
| 127 | .sqrxtune = 3, |
| 128 | .txfslstune = 3, |
| 129 | .txpreempamptune = 2, |
| 130 | .txpreemppulsetune = 0, |
| 131 | .txrisetune = 2, |
| 132 | .txvreftune = 3, |
| 133 | .txhsxvtune = 3, |
| 134 | .txrestune = 2, |
| 135 | }, |
| 136 | .Usb2PhyPort[7] = { |
| 137 | .compdstune = 1, |
| 138 | .sqrxtune = 3, |
| 139 | .txfslstune = 3, |
| 140 | .txpreempamptune = 2, |
| 141 | .txpreemppulsetune = 0, |
| 142 | .txrisetune = 2, |
| 143 | .txvreftune = 3, |
| 144 | .txhsxvtune = 3, |
| 145 | .txrestune = 2, |
| 146 | }, |
| 147 | |
| 148 | .Usb3PhyPort[0] = { |
| 149 | .tx_term_ctrl=2, |
| 150 | .rx_term_ctrl=2, |
| 151 | .tx_vboost_lvl_en=1, |
| 152 | .tx_vboost_lvl=5, |
| 153 | }, |
| 154 | .Usb3PhyPort[1] = { |
| 155 | .tx_term_ctrl=2, |
| 156 | .rx_term_ctrl=2, |
| 157 | .tx_vboost_lvl_en=1, |
| 158 | .tx_vboost_lvl=5, |
| 159 | }, |
| 160 | .Usb3PhyPort[2] = { |
| 161 | .tx_term_ctrl=2, |
| 162 | .rx_term_ctrl=2, |
| 163 | .tx_vboost_lvl_en=1, |
| 164 | .tx_vboost_lvl=5, |
| 165 | }, |
| 166 | .Usb3PhyPort[3] = { |
| 167 | .tx_term_ctrl=2, |
| 168 | .rx_term_ctrl=2, |
| 169 | .tx_vboost_lvl_en=1, |
| 170 | .tx_vboost_lvl=5, |
| 171 | }, |
| 172 | |
| 173 | .ComboPhyStaticConfig[0] = 0, |
| 174 | .ComboPhyStaticConfig[1] = 0, |
| 175 | .Version_Major = 0xd, |
| 176 | .Version_Minor = 0x4, |
| 177 | .TableLength = 100, |
| 178 | .BatteryChargerEnable = 0, |
| 179 | .PhyP3CpmP4Support = 0, |
| 180 | }" |
| 181 | |
Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 182 | device domain 0 on |
Karthikeyan Ramasubramanian | 24abd3e | 2021-05-04 16:19:32 -0600 | [diff] [blame] | 183 | device ref gpp_bridge_0 on |
| 184 | chip drivers/wifi/generic |
| 185 | register "wake" = "GEVENT_8" |
| 186 | device pci 00.0 on end |
| 187 | end |
| 188 | end # WLAN |
Mathew King | 095bdec | 2021-03-12 14:01:22 -0700 | [diff] [blame] | 189 | device ref gpp_bridge_1 on end # SD |
| 190 | device ref gpp_bridge_2 on end # WWAN |
| 191 | device ref gpp_bridge_3 on end # NVMe |
| 192 | |
Mathew King | abc6971 | 2021-03-03 16:36:46 -0700 | [diff] [blame] | 193 | device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A |
Raul Rangel | ca25ad5 | 2021-04-06 15:33:16 +0000 | [diff] [blame] | 194 | device ref gfx on end # Internal GPU (GFX) |
Karthikeyan Ramasubramanian | f6b2a1c | 2021-05-04 00:38:22 -0600 | [diff] [blame] | 195 | device ref gfx_hda on end # GFX HD Audio Controller |
Felix Held | 1028a41 | 2021-05-26 22:48:30 +0200 | [diff] [blame^] | 196 | device ref crypto on end # Crypto Coprocessor |
Mathew King | 238242b | 2021-03-04 08:24:55 -0700 | [diff] [blame] | 197 | device ref xhci_0 on # USB 3.1 (USB0) |
| 198 | chip drivers/usb/acpi |
| 199 | device ref xhci_0_root_hub on |
| 200 | chip drivers/usb/acpi |
| 201 | register "desc" = ""Right Type-C Port"" |
| 202 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 203 | register "group" = "ACPI_PLD_GROUP(1, 1)" |
| 204 | device ref usb3_port0 on end |
| 205 | end |
| 206 | chip drivers/usb/acpi |
| 207 | register "desc" = ""Right Type-A Port"" |
| 208 | register "type" = "UPC_TYPE_USB3_A" |
| 209 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 210 | device ref usb3_port1 on end |
| 211 | end |
| 212 | chip drivers/usb/acpi |
| 213 | register "desc" = ""Right Type-C Port"" |
| 214 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 215 | register "group" = "ACPI_PLD_GROUP(1, 1)" |
| 216 | device ref usb2_port0 on end |
| 217 | end |
| 218 | chip drivers/usb/acpi |
| 219 | register "desc" = ""Right Type-A Port"" |
| 220 | register "type" = "UPC_TYPE_USB3_A" |
| 221 | register "group" = "ACPI_PLD_GROUP(1, 2)" |
| 222 | device ref usb2_port1 on end |
| 223 | end |
| 224 | chip drivers/usb/acpi |
| 225 | register "desc" = ""User-Facing Camera"" |
| 226 | register "type" = "UPC_TYPE_INTERNAL" |
| 227 | device ref usb2_port2 on end |
| 228 | end |
| 229 | chip drivers/usb/acpi |
| 230 | register "desc" = ""World-Facing Camera"" |
| 231 | register "type" = "UPC_TYPE_INTERNAL" |
| 232 | device ref usb2_port3 on end |
| 233 | end |
| 234 | end |
| 235 | end |
| 236 | end |
| 237 | device ref xhci_1 on # USB 3.1 (USB1) |
| 238 | chip drivers/usb/acpi |
| 239 | device ref xhci_1_root_hub on |
| 240 | chip drivers/usb/acpi |
| 241 | register "desc" = ""Left Type-C Port"" |
| 242 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 243 | register "group" = "ACPI_PLD_GROUP(2, 2)" |
| 244 | device ref usb3_port4 on end |
| 245 | end |
| 246 | chip drivers/usb/acpi |
| 247 | register "desc" = ""Left Type-A Port"" |
| 248 | register "type" = "UPC_TYPE_USB3_A" |
| 249 | register "group" = "ACPI_PLD_GROUP(2, 1)" |
| 250 | device ref usb3_port5 on end |
| 251 | end |
| 252 | chip drivers/usb/acpi |
| 253 | register "desc" = ""Left Type-C Port"" |
| 254 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 255 | register "group" = "ACPI_PLD_GROUP(2, 2)" |
| 256 | device ref usb2_port4 on end |
| 257 | end |
| 258 | chip drivers/usb/acpi |
| 259 | register "desc" = ""Left Type-A Port"" |
| 260 | register "type" = "UPC_TYPE_USB3_A" |
| 261 | register "group" = "ACPI_PLD_GROUP(2, 1)" |
| 262 | device ref usb2_port5 on end |
| 263 | end |
| 264 | chip drivers/usb/acpi |
| 265 | register "desc" = ""Bluetooth"" |
| 266 | register "type" = "UPC_TYPE_INTERNAL" |
Karthikeyan Ramasubramanian | d84ce40 | 2021-03-30 16:27:59 -0600 | [diff] [blame] | 267 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_132)" |
Mathew King | 238242b | 2021-03-04 08:24:55 -0700 | [diff] [blame] | 268 | device ref usb2_port6 on end |
| 269 | end |
| 270 | end |
| 271 | end |
| 272 | end |
Karthikeyan Ramasubramanian | e71a6ee | 2021-04-23 09:51:41 -0600 | [diff] [blame] | 273 | device ref acp on |
| 274 | chip drivers/amd/i2s_machine_dev |
| 275 | register "hid" = ""AMDI5682"" |
| 276 | device generic 0.0 on end |
| 277 | end |
| 278 | end # Audio |
Mathew King | abc6971 | 2021-03-03 16:36:46 -0700 | [diff] [blame] | 279 | end |
Mathew King | 78f0301 | 2021-03-05 09:04:44 -0700 | [diff] [blame] | 280 | |
| 281 | device ref lpc_bridge on |
| 282 | chip ec/google/chromeec |
Raul E Rangel | ba10223 | 2021-05-12 17:07:39 -0600 | [diff] [blame] | 283 | device pnp 0c09.0 alias chrome_ec on end |
Mathew King | 78f0301 | 2021-03-05 09:04:44 -0700 | [diff] [blame] | 284 | end |
| 285 | end |
Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 286 | end # domain |
Karthikeyan Ramasubramanian | 8f7fca5 | 2021-03-15 10:31:37 -0600 | [diff] [blame] | 287 | |
| 288 | device ref i2c_3 on |
| 289 | chip drivers/i2c/tpm |
| 290 | register "hid" = ""GOOG0005"" |
| 291 | register "desc" = ""Cr50 TPM"" |
| 292 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_3)" |
| 293 | device i2c 50 on end |
| 294 | end |
| 295 | end |
Ivy Jian | a7696ad | 2021-04-13 14:04:12 +0800 | [diff] [blame] | 296 | |
| 297 | device ref uart_0 on end # UART0 |
| 298 | |
Raul E Rangel | ba10223 | 2021-05-12 17:07:39 -0600 | [diff] [blame] | 299 | # See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/baseboard/guybrush/baseboard.c;l=221 |
| 300 | # for the EC configuration. |
| 301 | # |
| 302 | # EC is configured to power off the system at 105C, so add a two degree |
| 303 | # buffer so the OS can gracefully shutdown. |
| 304 | # |
| 305 | # EC is configured to assert PROCHOT at 100C. That drastically lowers |
| 306 | # performance. Instead we will tell the OS to start throttling the CPUs |
| 307 | # at 95C in hopes that we don't hit the PROCHOT limit. |
| 308 | # |
| 309 | # We set use_acpi1_thermal_zone_scope because the Chrome ec.asl |
| 310 | # performs a `Notify` to the `_\TZ` scope. |
| 311 | chip drivers/acpi/thermal_zone |
| 312 | register "description" = ""SOC"" |
| 313 | use chrome_ec as temperature_controller |
| 314 | register "sensor_id" = "0" |
| 315 | register "polling_period" = "10" |
| 316 | register "critical_temperature" = "103" |
| 317 | register "passive_config.temperature" = "95" |
| 318 | register "use_acpi1_thermal_zone_scope" = "true" |
| 319 | |
| 320 | device generic 0 on end |
| 321 | end |
| 322 | chip drivers/acpi/thermal_zone |
| 323 | register "description" = ""Charger"" |
| 324 | use chrome_ec as temperature_controller |
| 325 | register "sensor_id" = "1" |
| 326 | register "polling_period" = "10" |
| 327 | register "critical_temperature" = "103" |
| 328 | register "passive_config.temperature" = "95" |
| 329 | register "use_acpi1_thermal_zone_scope" = "true" |
| 330 | |
| 331 | device generic 1 on end |
| 332 | end |
| 333 | chip drivers/acpi/thermal_zone |
| 334 | register "description" = ""Memory"" |
| 335 | use chrome_ec as temperature_controller |
| 336 | register "sensor_id" = "2" |
| 337 | register "polling_period" = "10" |
| 338 | register "critical_temperature" = "103" |
| 339 | register "passive_config.temperature" = "95" |
| 340 | register "use_acpi1_thermal_zone_scope" = "true" |
| 341 | |
| 342 | device generic 2 on end |
| 343 | end |
| 344 | chip drivers/acpi/thermal_zone |
| 345 | register "description" = ""CPU"" |
| 346 | use chrome_ec as temperature_controller |
| 347 | register "sensor_id" = "3" |
| 348 | register "polling_period" = "10" |
| 349 | register "critical_temperature" = "103" |
| 350 | register "passive_config.temperature" = "95" |
| 351 | register "use_acpi1_thermal_zone_scope" = "true" |
| 352 | |
| 353 | device generic 3 on end |
| 354 | end |
Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 355 | end # chip soc/amd/cezanne |