| commit | a7696adbeb1f3ad7408a02ba82930c02079b01ed | [log] [tgz] |
|---|---|---|
| author | Ivy Jian <ivy_jian@compal.corp-partner.google.com> | Tue Apr 13 14:04:12 2021 +0800 |
| committer | Patrick Georgi <pgeorgi@google.com> | Fri Apr 16 06:45:32 2021 +0000 |
| tree | 7ecd417ee3cb2a86e12d56fd2d3623b0b8360018 | |
| parent | a0d48096ad83813d959886ba354f7b7eb0aea179 [diff] [blame] |
soc/amd/cezanne: Add uart controllers to chipset.cb Add uart controller to chipset.cb and leave it off by default. Turn uart0 on for console for mainboards. BUG=none TEST=builds and boot into OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Iaeb7fea4b92bd89331c7ae7c1c000f8d9961fe9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 5e9037a..f044b8b 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb
@@ -142,4 +142,7 @@ device i2c 50 on end end end + + device ref uart_0 on end # UART0 + end # chip soc/amd/cezanne