Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | #include <types.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 4 | #include <console/console.h> |
Angel Pons | f4fa1e1 | 2020-08-03 14:12:13 +0200 | [diff] [blame] | 5 | #include <commonlib/helpers.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 6 | #include <acpi/acpi.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 7 | #include <device/device.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 9 | #include "haswell.h" |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 10 | #include <southbridge/intel/lynxpoint/pch.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 11 | |
| 12 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 13 | { |
Angel Pons | 32770f8 | 2021-01-20 15:03:30 +0100 | [diff] [blame] | 14 | current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, |
| 15 | CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 16 | |
| 17 | return current; |
| 18 | } |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 19 | |
| 20 | static unsigned long acpi_fill_dmar(unsigned long current) |
| 21 | { |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 22 | struct device *const igfx_dev = pcidev_on_root(2, 0); |
Angel Pons | 2e397ae | 2021-03-26 12:35:57 +0100 | [diff] [blame] | 23 | const u32 gfxvtbar = mchbar_read32(GFXVTBAR) & ~0xfff; |
| 24 | const u32 vtvc0bar = mchbar_read32(VTVC0BAR) & ~0xfff; |
| 25 | const bool gfxvten = mchbar_read32(GFXVTBAR) & 0x1; |
| 26 | const bool vtvc0en = mchbar_read32(VTVC0BAR) & 0x1; |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 27 | |
| 28 | /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ |
Angel Pons | 849104f | 2020-10-29 21:39:52 +0100 | [diff] [blame] | 29 | const bool emit_igd = |
| 30 | igfx_dev && igfx_dev->enabled && |
| 31 | gfxvtbar && gfxvten && |
Angel Pons | 2e397ae | 2021-03-26 12:35:57 +0100 | [diff] [blame] | 32 | !mchbar_read32(GFXVTBAR + 4); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 33 | |
Angel Pons | 849104f | 2020-10-29 21:39:52 +0100 | [diff] [blame] | 34 | /* First, add DRHD entries */ |
| 35 | if (emit_igd) { |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 36 | const unsigned long tmp = current; |
| 37 | |
| 38 | current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); |
Matt DeVillier | 7866d49 | 2018-03-29 14:59:57 +0200 | [diff] [blame] | 39 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 40 | |
| 41 | acpi_dmar_drhd_fixup(tmp, current); |
| 42 | } |
| 43 | |
| 44 | /* VTVC0BAR has to be set, enabled, and in 32-bit space */ |
Angel Pons | 2e397ae | 2021-03-26 12:35:57 +0100 | [diff] [blame] | 45 | if (vtvc0bar && vtvc0en && !mchbar_read32(VTVC0BAR + 4)) { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 46 | |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 47 | const unsigned long tmp = current; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 48 | current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); |
| 49 | current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, |
| 50 | PCH_IOAPIC_PCI_SLOT, 0); |
| 51 | |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 52 | size_t i; |
| 53 | for (i = 0; i < 8; ++i) |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 54 | current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, |
| 55 | PCH_HPET_PCI_SLOT, i); |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 56 | acpi_dmar_drhd_fixup(tmp, current); |
| 57 | } |
| 58 | |
Angel Pons | 849104f | 2020-10-29 21:39:52 +0100 | [diff] [blame] | 59 | /* Then, add RMRR entries after all DRHD entries */ |
| 60 | if (emit_igd) { |
| 61 | const unsigned long tmp = current; |
| 62 | |
| 63 | const struct device *sa_dev = pcidev_on_root(0, 0); |
| 64 | |
| 65 | /* Bit 0 is lock bit, not part of address */ |
| 66 | const u32 tolud = pci_read_config32(sa_dev, TOLUD) & ~1; |
| 67 | const u32 bgsm = pci_read_config32(sa_dev, BGSM) & ~1; |
| 68 | |
| 69 | current += acpi_create_dmar_rmrr(current, 0, bgsm, tolud - 1); |
| 70 | current += acpi_create_dmar_ds_pci(current, 0, 2, 0); |
| 71 | acpi_dmar_rmrr_fixup(tmp, current); |
| 72 | } |
| 73 | |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 74 | return current; |
| 75 | } |
| 76 | |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 77 | unsigned long northbridge_write_acpi_tables(const struct device *const dev, |
| 78 | unsigned long current, |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 79 | struct acpi_rsdp *const rsdp) |
| 80 | { |
| 81 | /* Create DMAR table only if we have VT-d capability. */ |
| 82 | const u32 capid0_a = pci_read_config32(dev, CAPID0_A); |
| 83 | if (capid0_a & VTD_DISABLE) |
| 84 | return current; |
| 85 | |
| 86 | acpi_dmar_t *const dmar = (acpi_dmar_t *)current; |
| 87 | printk(BIOS_DEBUG, "ACPI: * DMAR\n"); |
| 88 | acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar); |
| 89 | current += dmar->header.length; |
| 90 | current = acpi_align_current(current); |
| 91 | acpi_add_table(rsdp, dmar); |
| 92 | |
| 93 | return current; |
| 94 | } |