Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # GPE configuration |
| 4 | # Note that GPE events called out in ASL code rely on this |
| 5 | # route. i.e. If this route changes then the affected GPE |
| 6 | # offset bits also need to be changed. |
| 7 | register "gpe0_dw0" = "GPP_B" |
| 8 | register "gpe0_dw1" = "GPP_D" |
| 9 | register "gpe0_dw2" = "GPP_E" |
| 10 | |
| 11 | register "gen1_dec" = "0x007c0a01" # Super IO SWC |
| 12 | register "gen2_dec" = "0x000c0ca1" # IPMI KCS |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 13 | |
Michael Niewöhner | 6238563 | 2019-09-23 14:38:41 +0200 | [diff] [blame] | 14 | # FIXME: find out why FSP crashes without this |
| 15 | register "PchHdaVcType" = "Vc1" |
| 16 | |
Felix Singer | 9a1b47e | 2023-10-23 17:37:21 +0200 | [diff] [blame^] | 17 | register "usb2_ports" = "{ |
| 18 | [0] = USB2_PORT_MID(OC0), /* USB 2 */ |
| 19 | [1] = USB2_PORT_MID(OC0), /* USB 3 */ |
| 20 | [2] = USB2_PORT_MID(OC1), /* USB 4 */ |
| 21 | [3] = USB2_PORT_MID(OC1), /* USB 5 */ |
| 22 | [4] = USB2_PORT_MID(OC2), /* USB 0 */ |
| 23 | [5] = USB2_PORT_MID(OC2), /* USB 1 */ |
| 24 | [8] = USB2_PORT_MID(OC3), /* USB 9 (3.0) */ |
| 25 | [9] = USB2_PORT_MID(OC5), /* USB 8 (3.0) */ |
| 26 | [10] = USB2_PORT_MID(OC4), /* USB 6 (3.0) */ |
| 27 | [11] = USB2_PORT_MID(OC4), /* USB 7 (3.0) */ |
| 28 | [12] = USB2_PORT_MID(OC3), /* USB 10 (3.0) */ |
| 29 | [13] = USB2_PORT_MID(OC_SKIP), /* IPMI USB hub */ |
| 30 | [14] = USB2_PORT_MID(OC0), /* Unknown */ |
| 31 | [15] = USB2_PORT_MID(OC0), /* Unknown */ |
| 32 | }" |
Michael Niewöhner | 33533c0 | 2019-10-19 21:15:15 +0200 | [diff] [blame] | 33 | |
Felix Singer | 9a1b47e | 2023-10-23 17:37:21 +0200 | [diff] [blame^] | 34 | register "usb3_ports" = "{ |
| 35 | [0] = USB3_PORT_DEFAULT(OC5), /* USB 8 */ |
| 36 | [1] = USB3_PORT_DEFAULT(OC4), /* USB 6 */ |
| 37 | [2] = USB3_PORT_DEFAULT(OC4), /* USB 7 */ |
| 38 | [3] = USB3_PORT_DEFAULT(OC3), /* USB 9 */ |
| 39 | [4] = USB3_PORT_DEFAULT(OC3), /* USB 10 */ |
| 40 | }" |
Michael Niewöhner | 33533c0 | 2019-10-19 21:15:15 +0200 | [diff] [blame] | 41 | |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 42 | device domain 0 on |
| 43 | device pci 01.0 on end # unused |
| 44 | device pci 01.1 on # PCIE Slot (JPCIE1) |
Michael Niewöhner | ddd44f4 | 2020-11-24 01:23:28 +0100 | [diff] [blame] | 45 | register "PcieRpEnable[0]" = "1" |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 46 | smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" |
| 47 | end |
| 48 | device pci 1c.0 on # PCI Express Port 1 (Slot JPCIE1) |
Michael Niewöhner | ddd44f4 | 2020-11-24 01:23:28 +0100 | [diff] [blame] | 49 | register "PcieRpEnable[2]" = "1" |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 50 | smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" |
| 51 | end |
| 52 | device pci 1c.2 on # PCI Express Port 3 |
| 53 | device pci 00.0 on # Aspeed PCI Bridge |
| 54 | device pci 00.0 on end # Aspeed 2400 VGA |
| 55 | end |
| 56 | end |
| 57 | device pci 1c.4 on # PCI Express Port 5 |
Michael Niewöhner | ddd44f4 | 2020-11-24 01:23:28 +0100 | [diff] [blame] | 58 | register "PcieRpEnable[4]" = "1" |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 59 | device pci 00.0 on end # 10GbE |
| 60 | device pci 00.1 on end # 10GbE |
| 61 | end |
| 62 | device pci 1d.0 on # PCI Express Port 9 |
Michael Niewöhner | ddd44f4 | 2020-11-24 01:23:28 +0100 | [diff] [blame] | 63 | register "PcieRpEnable[8]" = "1" |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 64 | smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" |
| 65 | end |
| 66 | device pci 1f.0 on # LPC Interface |
| 67 | chip drivers/ipmi |
Michael Niewöhner | 6c3ba50 | 2020-11-08 19:32:13 +0100 | [diff] [blame] | 68 | use pch_gpio as gpio_dev |
| 69 | register "post_complete_gpio" = "GPP_B20" |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 70 | # On cold boot it takes a while for the BMC to start the IPMI service |
| 71 | register "wait_for_bmc" = "1" |
| 72 | register "bmc_boot_timeout" = "60" |
| 73 | device pnp ca2.0 on end # IPMI KCS |
| 74 | end |
| 75 | chip superio/common |
| 76 | device pnp 2e.0 on |
| 77 | chip superio/aspeed/ast2400 |
| 78 | device pnp 2e.2 on # SUART1 |
| 79 | io 0x60 = 0x3f8 |
| 80 | irq 0x70 = 4 |
Michael Niewöhner | 1c8e464 | 2020-02-23 22:51:05 +0100 | [diff] [blame] | 81 | drq 0xf0 = 0x00 |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 82 | end |
| 83 | device pnp 2e.3 on # SUART2 |
| 84 | io 0x60 = 0x2f8 |
| 85 | irq 0x70 = 3 |
Michael Niewöhner | 1c8e464 | 2020-02-23 22:51:05 +0100 | [diff] [blame] | 86 | drq 0xf0 = 0x00 |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 87 | end |
| 88 | device pnp 2e.4 on # SWC |
| 89 | io 0x60 = 0xa00 |
| 90 | io 0x62 = 0xa10 |
| 91 | io 0x64 = 0xa20 |
| 92 | io 0x66 = 0xa30 |
Michael Niewöhner | 2a28c81 | 2020-07-25 23:47:44 +0200 | [diff] [blame] | 93 | irq 0x70 = 0x00 |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 94 | end |
Patrick Rudolph | baa8c78 | 2019-10-15 14:52:29 +0200 | [diff] [blame] | 95 | device pnp 2e.5 off end # KBC |
Michael Niewöhner | 2a28c81 | 2020-07-25 23:47:44 +0200 | [diff] [blame] | 96 | device pnp 2e.7 on # GPIO |
| 97 | irq 0x70 = 0x00 |
| 98 | end |
Michael Niewöhner | b1f1ee3 | 2020-02-10 20:58:50 +0100 | [diff] [blame] | 99 | device pnp 2e.b off end # SUART3 |
| 100 | device pnp 2e.c off end # SUART4 |
Michael Niewöhner | 2a28c81 | 2020-07-25 23:47:44 +0200 | [diff] [blame] | 101 | device pnp 2e.d on # iLPC2AHB |
| 102 | irq 0x70 = 0x00 |
| 103 | end |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 104 | device pnp 2e.e on # Mailbox |
| 105 | io 0x60 = 0xa40 |
| 106 | irq 0x70 = 0x00 |
| 107 | end |
| 108 | end |
| 109 | end |
| 110 | end |
| 111 | end |
| 112 | end |
| 113 | end |