Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 1 | chip soc/intel/skylake |
| 2 | |
| 3 | # GPE configuration |
| 4 | # Note that GPE events called out in ASL code rely on this |
| 5 | # route. i.e. If this route changes then the affected GPE |
| 6 | # offset bits also need to be changed. |
| 7 | register "gpe0_dw0" = "GPP_B" |
| 8 | register "gpe0_dw1" = "GPP_D" |
| 9 | register "gpe0_dw2" = "GPP_E" |
| 10 | |
| 11 | register "gen1_dec" = "0x007c0a01" # Super IO SWC |
| 12 | register "gen2_dec" = "0x000c0ca1" # IPMI KCS |
| 13 | register "gen3_dec" = "0x000c03e1" # UART3 |
| 14 | register "gen4_dec" = "0x000c02e1" # UART4 |
| 15 | |
| 16 | # PCIe configuration |
| 17 | # Enable JPCIE1 |
| 18 | register "PcieRpEnable[0]" = "1" |
| 19 | register "PcieRpClkReqSupport[0]" = "0" |
| 20 | |
| 21 | # Enable ASpeed PCI bridge |
| 22 | register "PcieRpEnable[2]" = "1" |
| 23 | register "PcieRpClkReqSupport[2]" = "0" |
| 24 | |
| 25 | # Enable X550T (10GbE) |
| 26 | register "PcieRpEnable[4]" = "1" |
| 27 | register "PcieRpClkReqSupport[4]" = "0" |
| 28 | |
| 29 | # Enable M.2 |
| 30 | register "PcieRpEnable[8]" = "1" |
| 31 | register "PcieRpClkReqSupport[8]" = "0" |
| 32 | |
Michael Niewöhner | 6238563 | 2019-09-23 14:38:41 +0200 | [diff] [blame] | 33 | # FIXME: find out why FSP crashes without this |
| 34 | register "PchHdaVcType" = "Vc1" |
| 35 | |
Michael Niewöhner | 33533c0 | 2019-10-19 21:15:15 +0200 | [diff] [blame] | 36 | # USB configuration |
| 37 | # USB2/3 |
| 38 | register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" |
| 39 | register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" |
| 40 | |
| 41 | # ? |
| 42 | register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" |
| 43 | register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" |
| 44 | |
| 45 | # USB4/5 |
| 46 | register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" |
| 47 | register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" |
| 48 | |
| 49 | # USB0/1 |
| 50 | register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" |
| 51 | register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" |
| 52 | |
| 53 | # USB9/10 (USB3.0) |
| 54 | register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" |
| 55 | register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" |
| 56 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" |
| 57 | register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" |
| 58 | |
| 59 | # USB6/7 (USB3.0) |
| 60 | register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" |
| 61 | register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" |
| 62 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" |
| 63 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" |
| 64 | |
| 65 | # USB8 (USB3.0) |
| 66 | register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" |
| 67 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" |
| 68 | |
| 69 | # IPMI USB HUB |
| 70 | register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" |
| 71 | |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 72 | device domain 0 on |
| 73 | device pci 01.0 on end # unused |
| 74 | device pci 01.1 on # PCIE Slot (JPCIE1) |
| 75 | smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" |
| 76 | end |
| 77 | device pci 1c.0 on # PCI Express Port 1 (Slot JPCIE1) |
| 78 | smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" |
| 79 | end |
| 80 | device pci 1c.2 on # PCI Express Port 3 |
| 81 | device pci 00.0 on # Aspeed PCI Bridge |
| 82 | device pci 00.0 on end # Aspeed 2400 VGA |
| 83 | end |
| 84 | end |
| 85 | device pci 1c.4 on # PCI Express Port 5 |
| 86 | device pci 00.0 on end # 10GbE |
| 87 | device pci 00.1 on end # 10GbE |
| 88 | end |
| 89 | device pci 1d.0 on # PCI Express Port 9 |
| 90 | smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" |
| 91 | end |
| 92 | device pci 1f.0 on # LPC Interface |
| 93 | chip drivers/ipmi |
| 94 | # On cold boot it takes a while for the BMC to start the IPMI service |
| 95 | register "wait_for_bmc" = "1" |
| 96 | register "bmc_boot_timeout" = "60" |
| 97 | device pnp ca2.0 on end # IPMI KCS |
| 98 | end |
| 99 | chip superio/common |
| 100 | device pnp 2e.0 on |
| 101 | chip superio/aspeed/ast2400 |
| 102 | device pnp 2e.2 on # SUART1 |
| 103 | io 0x60 = 0x3f8 |
| 104 | irq 0x70 = 4 |
| 105 | end |
| 106 | device pnp 2e.3 on # SUART2 |
| 107 | io 0x60 = 0x2f8 |
| 108 | irq 0x70 = 3 |
| 109 | end |
| 110 | device pnp 2e.4 on # SWC |
| 111 | io 0x60 = 0xa00 |
| 112 | io 0x62 = 0xa10 |
| 113 | io 0x64 = 0xa20 |
| 114 | io 0x66 = 0xa30 |
| 115 | irq 0x70 = 0xb |
| 116 | end |
Patrick Rudolph | baa8c78 | 2019-10-15 14:52:29 +0200 | [diff] [blame^] | 117 | device pnp 2e.5 off end # KBC |
Michael Niewöhner | 0a6c62f | 2019-09-18 16:31:50 +0200 | [diff] [blame] | 118 | device pnp 2e.7 on end # GPIO |
| 119 | device pnp 2e.b on # SUART3 |
| 120 | io 0x60 = 0x3e8 |
| 121 | irq 0x70 = 4 |
| 122 | end |
| 123 | device pnp 2e.c on # SUART4 |
| 124 | io 0x60 = 0x2e8 |
| 125 | irq 0x70 = 3 |
| 126 | end |
| 127 | device pnp 2e.d on end # iLPC2AHB |
| 128 | device pnp 2e.e on # Mailbox |
| 129 | io 0x60 = 0xa40 |
| 130 | irq 0x70 = 0x00 |
| 131 | end |
| 132 | end |
| 133 | end |
| 134 | end |
| 135 | end |
| 136 | end |
| 137 | end |