src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb

chip soc/intel/skylake

	# GPE configuration
	# Note that GPE events called out in ASL code rely on this
	# route. i.e. If this route changes then the affected GPE
	# offset bits also need to be changed.
	register "gpe0_dw0" = "GPP_B"
	register "gpe0_dw1" = "GPP_D"
	register "gpe0_dw2" = "GPP_E"

	register "gen1_dec" = "0x007c0a01"	# Super IO SWC
	register "gen2_dec" = "0x000c0ca1"	# IPMI KCS
	register "gen3_dec" = "0x000c03e1"	# UART3
	register "gen4_dec" = "0x000c02e1"	# UART4

	# PCIe configuration
	# Enable JPCIE1
	register "PcieRpEnable[0]" = "1"
	register "PcieRpClkReqSupport[0]" = "0"

	# Enable ASpeed PCI bridge
	register "PcieRpEnable[2]" = "1"
	register "PcieRpClkReqSupport[2]" = "0"

	# Enable X550T (10GbE)
	register "PcieRpEnable[4]" = "1"
	register "PcieRpClkReqSupport[4]" = "0"

	# Enable M.2
	register "PcieRpEnable[8]" = "1"
	register "PcieRpClkReqSupport[8]" = "0"

	# FIXME: find out why FSP crashes without this
	register "PchHdaVcType" = "Vc1"

	device domain 0 on
		device pci 01.0 on end	# unused
		device pci 01.1 on	# PCIE Slot (JPCIE1)
			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X"
		end
		device pci 1c.0 on	# PCI Express Port 1 (Slot JPCIE1)
			smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X"
		end
		device pci 1c.2 on	# PCI Express Port 3
			device pci 00.0 on	# Aspeed PCI Bridge
				device pci 00.0 on end	# Aspeed 2400 VGA
			end
		end
		device pci 1c.4 on	# PCI Express Port 5
			device pci 00.0 on end	# 10GbE
			device pci 00.1 on end	# 10GbE
		end
		device pci 1d.0 on	# PCI Express Port 9
			smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
		end
		device pci 1f.0 on	# LPC Interface
			chip drivers/ipmi
				# On cold boot it takes a while for the BMC to start the IPMI service
				register "wait_for_bmc" = "1"
				register "bmc_boot_timeout" = "60"
				device pnp ca2.0 on end	# IPMI KCS
			end
			chip superio/common
				device pnp 2e.0 on
					chip superio/aspeed/ast2400
						device pnp 2e.2 on	# SUART1
							io 0x60 = 0x3f8
							irq 0x70 = 4
						end
						device pnp 2e.3 on	# SUART2
							io 0x60 = 0x2f8
							irq 0x70 = 3
						end
						device pnp 2e.4 on	# SWC
							io 0x60 = 0xa00
							io 0x62 = 0xa10
							io 0x64 = 0xa20
							io 0x66 = 0xa30
							irq 0x70 = 0xb
						end
						device pnp 2e.5 on	# Keyboard
							io 0x60 = 0x60
							io 0x62 = 0x64
							irq 0x70 = 1
							irq 0x72 = 0xc
						end
						device pnp 2e.7 on end	# GPIO
						device pnp 2e.b on	# SUART3
							io 0x60 = 0x3e8
							irq 0x70 = 4
						end
						device pnp 2e.c on	# SUART4
							io 0x60 = 0x2e8
							irq 0x70 = 3
						end
						device pnp 2e.d on end	# iLPC2AHB
						device pnp 2e.e on	# Mailbox
							io 0x60 = 0xa40
							irq 0x70 = 0x00
						end
					end
				end
			end
		end
	end
end