| commit | 6238563b2b65edac8e6dba4f8f20eb020c172317 | [log] [tgz] |
|---|---|---|
| author | Michael Niewöhner <foss@mniewoehner.de> | Mon Sep 23 14:38:41 2019 +0200 |
| committer | Patrick Georgi <pgeorgi@google.com> | Wed Oct 02 11:15:00 2019 +0000 |
| tree | 8293ac5ef0441b978b3c447a19f8262627d25843 | |
| parent | 5387144a939b4ad3d334f2b4abebb987611b0274 [diff] [blame] |
soc/intel/skylake: devicetree: introduce PchHdaVcType fsp parameter Make the the FSP Parameter PchHdaVcType a devicetree setting and make use of it in the devicetrees of all boards that currently set it. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ibafc3b6bd2495658f2bd634218042ec413a89f5e Reviewed-on: https://review.coreboot.org/c/coreboot/+/35542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 1039f7a..09aa8b5 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb
@@ -30,6 +30,9 @@ register "PcieRpEnable[8]" = "1" register "PcieRpClkReqSupport[8]" = "0" + # FIXME: find out why FSP crashes without this + register "PchHdaVcType" = "Vc1" + device domain 0 on device pci 01.0 on end # unused device pci 01.1 on # PCIE Slot (JPCIE1)