Angel Pons | f94ac9a | 2020-04-05 15:46:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 2 | |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 3 | #include <assert.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 4 | #include <cbfs.h> |
| 5 | #include <cbmem.h> |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 6 | #include <cf9_reset.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 7 | #include <console/console.h> |
| 8 | #include <device/pci_def.h> |
Matt DeVillier | 9aaf59a | 2018-05-27 21:51:49 -0500 | [diff] [blame] | 9 | #include <memory_info.h> |
Aaron Durbin | decd062 | 2017-12-15 12:26:40 -0700 | [diff] [blame] | 10 | #include <mrc_cache.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 11 | #include <string.h> |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 12 | #if CONFIG(EC_GOOGLE_CHROMEEC) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 13 | #include <ec/google/chromeec/ec.h> |
| 14 | #include <ec/google/chromeec/ec_commands.h> |
| 15 | #endif |
| 16 | #include <vendorcode/google/chromeos/chromeos.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 17 | #include <soc/iomap.h> |
| 18 | #include <soc/pei_data.h> |
| 19 | #include <soc/pei_wrapper.h> |
| 20 | #include <soc/pm.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 21 | #include <soc/romstage.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 22 | #include <soc/systemagent.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 23 | |
| 24 | /* |
Angel Pons | 239c966 | 2020-10-13 21:34:53 +0200 | [diff] [blame] | 25 | * Dump in the log memory controller configuration as read from the memory |
| 26 | * controller registers. |
| 27 | */ |
| 28 | static void report_memory_config(void) |
| 29 | { |
Angel Pons | 430f1c5 | 2020-10-13 23:01:48 +0200 | [diff] [blame] | 30 | u32 addr_decode_ch[2]; |
Angel Pons | 239c966 | 2020-10-13 21:34:53 +0200 | [diff] [blame] | 31 | int i; |
| 32 | |
Angel Pons | 430f1c5 | 2020-10-13 23:01:48 +0200 | [diff] [blame] | 33 | const u32 addr_decoder_common = MCHBAR32(MAD_CHNL); |
| 34 | addr_decode_ch[0] = MCHBAR32(MAD_DIMM(0)); |
| 35 | addr_decode_ch[1] = MCHBAR32(MAD_DIMM(1)); |
Angel Pons | 239c966 | 2020-10-13 21:34:53 +0200 | [diff] [blame] | 36 | |
| 37 | printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", |
Angel Pons | 430f1c5 | 2020-10-13 23:01:48 +0200 | [diff] [blame] | 38 | (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); |
| 39 | |
Angel Pons | 239c966 | 2020-10-13 21:34:53 +0200 | [diff] [blame] | 40 | printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", |
Angel Pons | 430f1c5 | 2020-10-13 23:01:48 +0200 | [diff] [blame] | 41 | (addr_decoder_common >> 0) & 3, |
Angel Pons | 239c966 | 2020-10-13 21:34:53 +0200 | [diff] [blame] | 42 | (addr_decoder_common >> 2) & 3, |
| 43 | (addr_decoder_common >> 4) & 3); |
| 44 | |
| 45 | for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { |
| 46 | u32 ch_conf = addr_decode_ch[i]; |
Angel Pons | 430f1c5 | 2020-10-13 23:01:48 +0200 | [diff] [blame] | 47 | |
| 48 | printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); |
| 49 | |
Angel Pons | 239c966 | 2020-10-13 21:34:53 +0200 | [diff] [blame] | 50 | printk(BIOS_DEBUG, " enhanced interleave mode %s\n", |
| 51 | ((ch_conf >> 22) & 1) ? "on" : "off"); |
Angel Pons | 430f1c5 | 2020-10-13 23:01:48 +0200 | [diff] [blame] | 52 | |
Angel Pons | 239c966 | 2020-10-13 21:34:53 +0200 | [diff] [blame] | 53 | printk(BIOS_DEBUG, " rank interleave %s\n", |
| 54 | ((ch_conf >> 21) & 1) ? "on" : "off"); |
Angel Pons | 430f1c5 | 2020-10-13 23:01:48 +0200 | [diff] [blame] | 55 | |
Angel Pons | 239c966 | 2020-10-13 21:34:53 +0200 | [diff] [blame] | 56 | printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", |
| 57 | ((ch_conf >> 0) & 0xff) * 256, |
| 58 | ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", |
| 59 | ((ch_conf >> 17) & 1) ? "dual" : "single", |
| 60 | ((ch_conf >> 16) & 1) ? "" : ", selected"); |
Angel Pons | 430f1c5 | 2020-10-13 23:01:48 +0200 | [diff] [blame] | 61 | |
Angel Pons | 239c966 | 2020-10-13 21:34:53 +0200 | [diff] [blame] | 62 | printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", |
| 63 | ((ch_conf >> 8) & 0xff) * 256, |
Angel Pons | 973c9d4 | 2020-10-13 23:28:23 +0200 | [diff] [blame^] | 64 | ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32", |
Angel Pons | 239c966 | 2020-10-13 21:34:53 +0200 | [diff] [blame] | 65 | ((ch_conf >> 18) & 1) ? "dual" : "single", |
| 66 | ((ch_conf >> 16) & 1) ? ", selected" : ""); |
| 67 | } |
| 68 | } |
| 69 | |
| 70 | /* |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 71 | * Find PEI executable in coreboot filesystem and execute it. |
| 72 | */ |
| 73 | void raminit(struct pei_data *pei_data) |
| 74 | { |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 75 | size_t mrc_size; |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 76 | struct memory_info *mem_info; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 77 | pei_wrapper_entry_t entry; |
| 78 | int ret; |
Arthur Heymans | 4d56a06 | 2018-12-22 16:11:52 +0100 | [diff] [blame] | 79 | struct cbfsf f; |
| 80 | uint32_t type = CBFS_TYPE_MRC; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 81 | |
| 82 | broadwell_fill_pei_data(pei_data); |
| 83 | |
Julius Werner | 29fbfcc | 2020-03-02 15:54:43 -0800 | [diff] [blame] | 84 | if (CONFIG(BROADWELL_VBOOT_IN_BOOTBLOCK) && |
| 85 | vboot_recovery_mode_enabled()) { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 86 | /* Recovery mode does not use MRC cache */ |
| 87 | printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 88 | } else { |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 89 | /* Assume boot device is memory mapped. */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 90 | assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 91 | |
| 92 | pei_data->saved_data = |
| 93 | mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, 0, |
| 94 | &mrc_size); |
| 95 | if (pei_data->saved_data) { |
| 96 | /* MRC cache found */ |
| 97 | pei_data->saved_data_size = mrc_size; |
| 98 | } else if (pei_data->boot_mode == ACPI_S3) { |
| 99 | /* Waking from S3 and no cache. */ |
| 100 | printk(BIOS_DEBUG, |
| 101 | "No MRC cache found in S3 resume path.\n"); |
| 102 | post_code(POST_RESUME_FAILURE); |
| 103 | system_reset(); |
| 104 | } else { |
| 105 | printk(BIOS_DEBUG, "No MRC cache found.\n"); |
| 106 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 107 | } |
| 108 | |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 109 | /* |
| 110 | * Do not use saved pei data. Can be set by mainboard romstage |
| 111 | * to force a full train of memory on every boot. |
| 112 | */ |
| 113 | if (pei_data->disable_saved_data) { |
| 114 | printk(BIOS_DEBUG, "Disabling PEI saved data by request\n"); |
| 115 | pei_data->saved_data = NULL; |
| 116 | pei_data->saved_data_size = 0; |
| 117 | } |
| 118 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 119 | /* Determine if mrc.bin is in the cbfs. */ |
Arthur Heymans | 4d56a06 | 2018-12-22 16:11:52 +0100 | [diff] [blame] | 120 | if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) |
| 121 | die("mrc.bin not found!"); |
| 122 | /* We don't care about leaking the mapping */ |
| 123 | entry = (pei_wrapper_entry_t)rdev_mmap_full(&f.data); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 124 | if (entry == NULL) { |
| 125 | printk(BIOS_DEBUG, "Couldn't find mrc.bin\n"); |
| 126 | return; |
| 127 | } |
| 128 | |
| 129 | printk(BIOS_DEBUG, "Starting Memory Reference Code\n"); |
| 130 | |
| 131 | ret = entry(pei_data); |
| 132 | if (ret < 0) |
| 133 | die("pei_data version mismatch\n"); |
| 134 | |
| 135 | /* Print the MRC version after executing the UEFI PEI stage. */ |
Angel Pons | 430f1c5 | 2020-10-13 23:01:48 +0200 | [diff] [blame] | 136 | u32 version = MCHBAR32(MRC_REVISION); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 137 | printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n", |
Angel Pons | 430f1c5 | 2020-10-13 23:01:48 +0200 | [diff] [blame] | 138 | (version >> 24) & 0xff, (version >> 16) & 0xff, |
| 139 | (version >> 8) & 0xff, (version >> 0) & 0xff); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 140 | |
| 141 | report_memory_config(); |
| 142 | |
Aaron Durbin | 9e6d143 | 2016-07-13 23:21:41 -0500 | [diff] [blame] | 143 | if (pei_data->boot_mode != ACPI_S3) { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 144 | cbmem_initialize_empty(); |
Aaron Durbin | 42e6856 | 2015-06-09 13:55:51 -0500 | [diff] [blame] | 145 | } else if (cbmem_initialize()) { |
Aaron Durbin | 42e6856 | 2015-06-09 13:55:51 -0500 | [diff] [blame] | 146 | printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); |
| 147 | /* Failed S3 resume, reset to come up cleanly */ |
Patrick Rudolph | 45022ae | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 148 | system_reset(); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 149 | } |
| 150 | |
| 151 | printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save, |
| 152 | pei_data->data_to_save_size); |
| 153 | |
| 154 | if (pei_data->data_to_save != NULL && pei_data->data_to_save_size > 0) |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 155 | mrc_cache_stash_data(MRC_TRAINING_DATA, 0, |
| 156 | pei_data->data_to_save, |
| 157 | pei_data->data_to_save_size); |
Kane Chen | ebbb0d4 | 2014-07-28 10:54:40 -0700 | [diff] [blame] | 158 | |
| 159 | printk(BIOS_DEBUG, "create cbmem for dimm information\n"); |
| 160 | mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); |
John Zhao | 317cbd6 | 2019-05-31 10:44:46 -0700 | [diff] [blame] | 161 | |
| 162 | if (!mem_info) { |
| 163 | printk(BIOS_ERR, "Error! Failed to add mem_info to cbmem\n"); |
| 164 | return; |
| 165 | } |
| 166 | |
Matt DeVillier | 9aaf59a | 2018-05-27 21:51:49 -0500 | [diff] [blame] | 167 | memset(mem_info, 0, sizeof(*mem_info)); |
| 168 | /* Translate pei_memory_info struct data into memory_info struct */ |
| 169 | mem_info->dimm_cnt = pei_data->meminfo.dimm_cnt; |
| 170 | for (int i = 0; i < MIN(DIMM_INFO_TOTAL, PEI_DIMM_INFO_TOTAL); i++) { |
| 171 | struct dimm_info *dimm = &mem_info->dimm[i]; |
| 172 | const struct pei_dimm_info *pei_dimm = |
| 173 | &pei_data->meminfo.dimm[i]; |
| 174 | dimm->dimm_size = pei_dimm->dimm_size; |
| 175 | dimm->ddr_type = pei_dimm->ddr_type; |
| 176 | dimm->ddr_frequency = pei_dimm->ddr_frequency; |
| 177 | dimm->rank_per_dimm = pei_dimm->rank_per_dimm; |
| 178 | dimm->channel_num = pei_dimm->channel_num; |
| 179 | dimm->dimm_num = pei_dimm->dimm_num; |
| 180 | dimm->bank_locator = pei_dimm->bank_locator; |
| 181 | memcpy(&dimm->serial, &pei_dimm->serial, |
| 182 | MIN(sizeof(dimm->serial), sizeof(pei_dimm->serial))); |
| 183 | memcpy(&dimm->module_part_number, |
| 184 | &pei_dimm->module_part_number, |
| 185 | MIN(sizeof(dimm->module_part_number), |
| 186 | sizeof(pei_dimm->module_part_number))); |
| 187 | dimm->module_part_number[DIMM_INFO_PART_NUMBER_SIZE - 1] = '\0'; |
| 188 | dimm->mod_id = pei_dimm->mod_id; |
| 189 | dimm->mod_type = pei_dimm->mod_type; |
| 190 | dimm->bus_width = pei_dimm->bus_width; |
| 191 | } |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 192 | } |