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Julius Werner7a757c92014-09-10 19:37:15 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2014 Rockchip Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Julius Werner7a757c92014-09-10 19:37:15 -070014 */
15
16#include <assert.h>
David Hendricks3c4951e2015-01-12 14:08:10 -080017#include <bcd.h>
Julius Werner7a757c92014-09-10 19:37:15 -070018#include <console/console.h>
Julius Werner7a453eb2014-10-20 13:14:55 -070019#include <delay.h>
Julius Werner7a757c92014-09-10 19:37:15 -070020#include <device/i2c.h>
David Hendricks3c4951e2015-01-12 14:08:10 -080021#include <rtc.h>
Julius Werner7a453eb2014-10-20 13:14:55 -070022#include <soc/rk808.h>
Julius Werner7a757c92014-09-10 19:37:15 -070023#include <stdint.h>
24#include <stdlib.h>
Julius Werner7a757c92014-09-10 19:37:15 -070025
David Hendricks4d244212015-01-12 13:13:30 -080026#if CONFIG_PMIC_BUS < 0
27#error "PMIC_BUS must be set in mainboard's Kconfig."
28#endif
Julius Werner7a757c92014-09-10 19:37:15 -070029
David Hendricks4d244212015-01-12 13:13:30 -080030#define RK808_ADDR 0x1b
Julius Werner7a757c92014-09-10 19:37:15 -070031
David Hendricks4d244212015-01-12 13:13:30 -080032#define DCDC_EN 0x23
33#define LDO_EN 0x24
34#define BUCK1SEL 0x2f
35#define BUCK4SEL 0x38
36#define LDO_ONSEL(i) (0x39 + 2 * i)
37#define LDO_SLPSEL(i) (0x3a + 2 * i)
38
David Hendricks3c4951e2015-01-12 14:08:10 -080039#define RTC_SECOND 0x00
40#define RTC_MINUTE 0x01
41#define RTC_HOUR 0x02
42#define RTC_DAY 0x03
43#define RTC_MONTH 0x04
44#define RTC_YEAR 0x05
45#define RTC_WEEKS 0x06
46#define RTC_CTRL 0x10
47#define RTC_STATUS 0x11
48
49#define RTC_CTRL_STOP_RTC (1 << 0)
50#define RTC_CTRL_GET_TIME (1 << 6)
51#define RTC_CTRL_RTC_READSEL (1 << 7)
52
huang lin3704e692015-02-27 19:35:04 -080053#define DCDC_UV_ACT 0x28
huang lin75f431a2015-01-23 14:48:42 +080054#define DCDC_ILMAX 0x90
55
David Hendricks4d244212015-01-12 13:13:30 -080056static int rk808_read(uint8_t reg, uint8_t *value)
57{
58 return i2c_readb(CONFIG_PMIC_BUS, RK808_ADDR, reg, value);
59}
60
61static int rk808_write(uint8_t reg, uint8_t value)
62{
63 return i2c_writeb(CONFIG_PMIC_BUS, RK808_ADDR, reg, value);
64}
65
66static void rk808_clrsetbits(uint8_t reg, uint8_t clr, uint8_t set)
Julius Werner7a757c92014-09-10 19:37:15 -070067{
68 uint8_t value;
69
David Hendricks4d244212015-01-12 13:13:30 -080070 if (rk808_read(reg, &value) || rk808_write(reg, (value & ~clr) | set))
Julius Werner7a757c92014-09-10 19:37:15 -070071 printk(BIOS_ERR, "ERROR: Cannot set Rk808[%#x]!\n", reg);
72}
73
David Hendricks4d244212015-01-12 13:13:30 -080074void rk808_configure_switch(int sw, int enabled)
Julius Werner8f3883d2014-09-26 21:01:08 -070075{
76 assert(sw == 1 || sw == 2);
David Hendricks4d244212015-01-12 13:13:30 -080077 rk808_clrsetbits(DCDC_EN, 1 << (sw + 4), !!enabled << (sw + 4));
Julius Werner8f3883d2014-09-26 21:01:08 -070078}
79
David Hendricks4d244212015-01-12 13:13:30 -080080void rk808_configure_ldo(int ldo, int millivolts)
Julius Werner7a757c92014-09-10 19:37:15 -070081{
82 uint8_t vsel;
83
Julius Wernerdbfa9d52014-12-05 17:29:42 -080084 if (!millivolts) {
David Hendricks4d244212015-01-12 13:13:30 -080085 rk808_clrsetbits(LDO_EN, 1 << (ldo - 1), 0);
Julius Wernerdbfa9d52014-12-05 17:29:42 -080086 return;
87 }
88
Julius Werner7a757c92014-09-10 19:37:15 -070089 switch (ldo) {
90 case 1:
91 case 2:
92 case 4:
93 case 5:
94 case 8:
huang lin08884e32014-10-10 20:28:47 -070095 vsel = div_round_up(millivolts, 100) - 18;
Julius Werneref639b22014-11-06 14:33:12 -080096 assert(vsel <= 0x10);
Julius Werner7a757c92014-09-10 19:37:15 -070097 break;
98 case 3:
99 case 6:
100 case 7:
huang lin08884e32014-10-10 20:28:47 -0700101 vsel = div_round_up(millivolts, 100) - 8;
Julius Werneref639b22014-11-06 14:33:12 -0800102 assert(vsel <= 0x11);
Julius Werner7a757c92014-09-10 19:37:15 -0700103 break;
104 default:
105 die("Unknown LDO index!");
106 }
Julius Werner7a757c92014-09-10 19:37:15 -0700107
David Hendricks4d244212015-01-12 13:13:30 -0800108 rk808_clrsetbits(LDO_ONSEL(ldo), 0x1f, vsel);
109 rk808_clrsetbits(LDO_EN, 0, 1 << (ldo - 1));
Julius Werner7a757c92014-09-10 19:37:15 -0700110}
huang lin08884e32014-10-10 20:28:47 -0700111
David Hendricks4d244212015-01-12 13:13:30 -0800112void rk808_configure_buck(int buck, int millivolts)
huang lin08884e32014-10-10 20:28:47 -0700113{
114 uint8_t vsel;
115 uint8_t buck_reg;
116
117 switch (buck) {
118 case 1:
119 case 2:
huang lin75f431a2015-01-23 14:48:42 +0800120 /* 25mV steps. base = 29 * 25mV = 725 */
huang lin08884e32014-10-10 20:28:47 -0700121 vsel = (div_round_up(millivolts, 25) - 29) * 2 + 1;
122 assert(vsel <= 0x3f);
123 buck_reg = BUCK1SEL + 4 * (buck - 1);
124 break;
125 case 4:
126 vsel = div_round_up(millivolts, 100) - 18;
127 assert(vsel <= 0xf);
128 buck_reg = BUCK4SEL;
129 break;
130 default:
huang lin75f431a2015-01-23 14:48:42 +0800131 die("Unknown buck index!");
huang lin08884e32014-10-10 20:28:47 -0700132 }
huang lin75f431a2015-01-23 14:48:42 +0800133 rk808_clrsetbits(DCDC_ILMAX, 0, 3 << ((buck - 1) * 2));
huang lin3704e692015-02-27 19:35:04 -0800134
135 /* undervoltage detection may be wrong, disable it */
136 rk808_clrsetbits(DCDC_UV_ACT, 1 << (buck - 1), 0);
137
David Hendricks4d244212015-01-12 13:13:30 -0800138 rk808_clrsetbits(buck_reg, 0x3f, vsel);
139 rk808_clrsetbits(DCDC_EN, 0, 1 << (buck - 1));
huang lin08884e32014-10-10 20:28:47 -0700140}
David Hendricks3c4951e2015-01-12 14:08:10 -0800141
142static void rk808rtc_stop(void)
143{
144 rk808_clrsetbits(RTC_CTRL, RTC_CTRL_STOP_RTC, 0);
145}
146
147static void rk808rtc_start(void)
148{
149 rk808_clrsetbits(RTC_CTRL, 0, RTC_CTRL_STOP_RTC);
150}
151
152int rtc_set(const struct rtc_time *time)
153{
154 int ret = 0;
155
156 /* RTC time can only be set when RTC is frozen */
157 rk808rtc_stop();
158
159 ret |= rk808_write(RTC_SECOND, bin2bcd(time->sec));
160 ret |= rk808_write(RTC_MINUTE, bin2bcd(time->min));
161 ret |= rk808_write(RTC_HOUR, bin2bcd(time->hour));
162 ret |= rk808_write(RTC_DAY, bin2bcd(time->mday));
163 ret |= rk808_write(RTC_MONTH, bin2bcd(time->mon));
164 ret |= rk808_write(RTC_YEAR, bin2bcd(time->year));
165
166 rk808rtc_start();
167 return ret;
168}
169
170int rtc_get(struct rtc_time *time)
171{
172 uint8_t value;
173 int ret = 0;
174
175 /*
176 * Set RTC_READSEL to cause reads to access shadow registers and
177 * transition GET_TIME from 0 to 1 to cause dynamic register content
178 * to be copied into shadow registers. This ensures a coherent reading
179 * of time values as we access each register using slow I2C transfers.
180 */
181 rk808_clrsetbits(RTC_CTRL, RTC_CTRL_GET_TIME, 0);
182 rk808_clrsetbits(RTC_CTRL, 0, RTC_CTRL_GET_TIME | RTC_CTRL_RTC_READSEL);
183
184 ret |= rk808_read(RTC_SECOND, &value);
185 time->sec = bcd2bin(value & 0x7f);
186
187 ret |= rk808_read(RTC_MINUTE, &value);
188 time->min = bcd2bin(value & 0x7f);
189
190 ret |= rk808_read(RTC_HOUR, &value);
191 time->hour = bcd2bin(value & 0x3f);
192
193 ret |= rk808_read(RTC_DAY, &value);
194 time->mday = bcd2bin(value & 0x3f);
195
196 ret |= rk808_read(RTC_MONTH, &value);
197 time->mon = bcd2bin(value & 0x1f);
198
199 ret |= rk808_read(RTC_YEAR, &value);
200 time->year = bcd2bin(value);
201
202 return ret;
203}