Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 5 | * Copyright (C) 2015 Intel Corporation. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
Aaron Durbin | 5a96b37 | 2015-08-18 10:11:35 -0500 | [diff] [blame] | 17 | #include <arch/acpi.h> |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 18 | #include <chip.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 19 | #include <console/console.h> |
| 20 | #include <device/device.h> |
| 21 | #include <device/pci.h> |
Aaron Durbin | 789f2b6 | 2015-09-09 17:05:06 -0500 | [diff] [blame] | 22 | #include <fsp/util.h> |
Subrata Banik | d0def39 | 2015-07-22 12:19:28 +0530 | [diff] [blame] | 23 | #include <soc/interrupt.h> |
| 24 | #include <soc/irq.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 25 | #include <soc/pci_devs.h> |
| 26 | #include <soc/ramstage.h> |
Duncan Laurie | 3745c65 | 2015-08-28 17:21:07 -0700 | [diff] [blame] | 27 | #include <string.h> |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 28 | |
Subrata Banik | d0def39 | 2015-07-22 12:19:28 +0530 | [diff] [blame] | 29 | static const SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = { |
| 30 | /* |
| 31 | * cAVS(Audio, Voice, Speach), INTA is default, programmed in |
| 32 | * PciCfgSpace 3Dh |
| 33 | */ |
| 34 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, |
| 35 | PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ), |
| 36 | /* |
| 37 | * SMBus Controller, no default value, programmed in |
| 38 | * PciCfgSpace 3Dh |
| 39 | */ |
| 40 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, |
| 41 | PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ), |
| 42 | /* GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh */ |
| 43 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, |
| 44 | PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ), |
| 45 | /* TraceHub, INTA is default, RO register */ |
| 46 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC, |
| 47 | PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A, TRACE_HUB_INTA_IRQ), |
| 48 | /* |
| 49 | * SerialIo: UART #0, INTA is default, |
| 50 | * programmed in PCR[SERIALIO] + PCICFGCTRL[7] |
| 51 | */ |
| 52 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, |
| 53 | PCI_FUNC(PCH_DEVFN_UART0), int_A, LPSS_UART0_IRQ), |
| 54 | /* |
| 55 | * SerialIo: UART #1, INTA is default, |
| 56 | * programmed in PCR[SERIALIO] + PCICFGCTRL[8] |
| 57 | */ |
| 58 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, |
| 59 | PCI_FUNC(PCH_DEVFN_UART1), int_B, LPSS_UART1_IRQ), |
| 60 | /* |
| 61 | * SerialIo: SPI #0, INTA is default, |
| 62 | * programmed in PCR[SERIALIO] + PCICFGCTRL[10] |
| 63 | */ |
| 64 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, |
| 65 | PCI_FUNC(PCH_DEVFN_GSPI0), int_C, LPSS_SPI0_IRQ), |
| 66 | /* |
| 67 | * SerialIo: SPI #1, INTA is default, |
| 68 | * programmed in PCR[SERIALIO] + PCICFGCTRL[11] |
| 69 | */ |
| 70 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, |
| 71 | PCI_FUNC(PCH_DEVFN_GSPI1), int_D, LPSS_SPI1_IRQ), |
| 72 | /* SCS: eMMC (SKL PCH-LP Only) */ |
| 73 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, |
| 74 | PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ), |
| 75 | /* SCS: SDIO (SKL PCH-LP Only) */ |
| 76 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, |
| 77 | PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ), |
| 78 | /* SCS: SDCard (SKL PCH-LP Only) */ |
| 79 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE, |
| 80 | PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ), |
| 81 | /* PCI Express Port 9, INT is default, programmed in PciCfgSpace + FCh */ |
| 82 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, |
| 83 | PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ), |
| 84 | /* PCI Express Port 10, INT is default, programmed in PciCfgSpace + FCh */ |
| 85 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, |
| 86 | PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ), |
| 87 | /* PCI Express Port 11, INT is default, programmed in PciCfgSpace + FCh */ |
| 88 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, |
| 89 | PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ), |
| 90 | /* PCI Express Port 12, INT is default, programmed in PciCfgSpace + FCh */ |
| 91 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1, |
| 92 | PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ), |
| 93 | /* |
| 94 | * PCI Express Port 1, INT is default, |
| 95 | * programmed in PciCfgSpace + FCh |
| 96 | */ |
| 97 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, |
| 98 | PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ), |
| 99 | /* |
| 100 | * PCI Express Port 2, INT is default, |
| 101 | * programmed in PciCfgSpace + FCh |
| 102 | */ |
| 103 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, |
| 104 | PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ), |
| 105 | /* |
| 106 | * PCI Express Port 3, INT is default, |
| 107 | * programmed in PciCfgSpace + FCh |
| 108 | */ |
| 109 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, |
| 110 | PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ), |
| 111 | /* |
| 112 | * PCI Express Port 4, INT is default, |
| 113 | * programmed in PciCfgSpace + FCh |
| 114 | */ |
| 115 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, |
| 116 | PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ), |
| 117 | /* |
| 118 | * PCI Express Port 5, INT is default, |
| 119 | * programmed in PciCfgSpace + FCh |
| 120 | */ |
| 121 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, |
| 122 | PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ), |
| 123 | /* |
| 124 | * PCI Express Port 6, INT is default, |
| 125 | * programmed in PciCfgSpace + FCh |
| 126 | */ |
| 127 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, |
| 128 | PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ), |
| 129 | /* |
| 130 | * PCI Express Port 7, INT is default, |
| 131 | * programmed in PciCfgSpace + FCh |
| 132 | */ |
| 133 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, |
| 134 | PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ), |
| 135 | /* |
| 136 | * PCI Express Port 8, INT is default, |
| 137 | * programmed in PciCfgSpace + FCh |
| 138 | */ |
| 139 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE, |
| 140 | PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ), |
| 141 | /* |
| 142 | * SerialIo UART Controller #2, INTA is default, |
| 143 | * programmed in PCR[SERIALIO] + PCICFGCTRL[9] |
| 144 | */ |
| 145 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, |
| 146 | PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ), |
| 147 | /* |
| 148 | * SerialIo UART Controller #5, INTA is default, |
| 149 | * programmed in PCR[SERIALIO] + PCICFGCTRL[6] |
| 150 | */ |
| 151 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, |
| 152 | PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ), |
| 153 | /* |
| 154 | * SerialIo UART Controller #4, INTA is default, |
| 155 | * programmed in PCR[SERIALIO] + PCICFGCTRL[5] |
| 156 | */ |
| 157 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2, |
| 158 | PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ), |
| 159 | /* |
| 160 | * SATA Controller, INTA is default, |
| 161 | * programmed in PciCfgSpace + 3Dh |
| 162 | */ |
| 163 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA, |
| 164 | PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ), |
| 165 | /* CSME: HECI #1 */ |
| 166 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, |
| 167 | PCI_FUNC(PCH_DEVFN_ME), int_A, HECI_1_IRQ), |
| 168 | /* CSME: HECI #2 */ |
| 169 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, |
| 170 | PCI_FUNC(PCH_DEVFN_ME_2), int_B, HECI_2_IRQ), |
| 171 | /* CSME: IDE-Redirection (IDE-R) */ |
| 172 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, |
| 173 | PCI_FUNC(PCH_DEVFN_ME_IDER), int_C, IDER_IRQ), |
| 174 | /* CSME: Keyboard and Text (KT) Redirection */ |
| 175 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, |
| 176 | PCI_FUNC(PCH_DEVFN_ME_KT), int_D, KT_IRQ), |
| 177 | /* CSME: HECI #3 */ |
| 178 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, |
| 179 | PCI_FUNC(PCH_DEVFN_ME_3), int_A, HECI_3_IRQ), |
| 180 | /* |
| 181 | * SerialIo I2C Controller #0, INTA is default, |
| 182 | * programmed in PCR[SERIALIO] + PCICFGCTRL[1] |
| 183 | */ |
| 184 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, |
| 185 | PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ), |
| 186 | /* |
| 187 | * SerialIo I2C Controller #1, INTA is default, |
| 188 | * programmed in PCR[SERIALIO] + PCICFGCTRL[2] |
| 189 | */ |
| 190 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, |
| 191 | PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ), |
| 192 | /* |
| 193 | * SerialIo I2C Controller #2, INTA is default, |
| 194 | * programmed in PCR[SERIALIO] + PCICFGCTRL[3] |
| 195 | */ |
| 196 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, |
| 197 | PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ), |
| 198 | /* |
| 199 | * SerialIo I2C Controller #3, INTA is default, |
| 200 | * programmed in PCR[SERIALIO] + PCICFGCTRL[4] |
| 201 | */ |
| 202 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1, |
| 203 | PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ), |
| 204 | /* |
| 205 | * USB 3.0 xHCI Controller, no default value, |
| 206 | * programmed in PciCfgSpace 3Dh |
| 207 | */ |
| 208 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, |
| 209 | PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ), |
| 210 | /* USB Device Controller (OTG) */ |
| 211 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, |
| 212 | PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ), |
| 213 | /* Thermal Subsystem */ |
| 214 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, |
| 215 | PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THRMAL_IRQ), |
| 216 | /* Camera IO Host Controller */ |
| 217 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI, |
| 218 | PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ), |
| 219 | /* Integrated Sensor Hub */ |
| 220 | DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, |
| 221 | PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ) |
| 222 | }; |
| 223 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 224 | static void pci_domain_set_resources(device_t dev) |
| 225 | { |
| 226 | assign_resources(dev->link_list); |
| 227 | } |
| 228 | |
| 229 | static struct device_operations pci_domain_ops = { |
| 230 | .read_resources = &pci_domain_read_resources, |
| 231 | .set_resources = &pci_domain_set_resources, |
| 232 | .scan_bus = &pci_domain_scan_bus, |
| 233 | .ops_pci_bus = &pci_bus_default_ops, |
| 234 | }; |
| 235 | |
| 236 | static struct device_operations cpu_bus_ops = { |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 237 | .init = &soc_init_cpus, |
Aaron Durbin | 5a96b37 | 2015-08-18 10:11:35 -0500 | [diff] [blame] | 238 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 239 | }; |
| 240 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 241 | static void soc_enable(device_t dev) |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 242 | { |
| 243 | /* Set the operations if it is a special bus type */ |
| 244 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 245 | dev->ops = &pci_domain_ops; |
| 246 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 247 | dev->ops = &cpu_bus_ops; |
| 248 | } else if (dev->path.type == DEVICE_PATH_PCI) { |
| 249 | /* Handle PCH device enable */ |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 250 | if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_IGD && |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 251 | (dev->ops == NULL || dev->ops->enable == NULL)) { |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 252 | pch_enable_dev(dev); |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 253 | } |
| 254 | } |
| 255 | } |
| 256 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 257 | struct chip_operations soc_intel_skylake_ops = { |
| 258 | CHIP_NAME("Intel Skylake") |
| 259 | .enable_dev = &soc_enable, |
| 260 | .init = &soc_init_pre_device, |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 261 | }; |
| 262 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 263 | /* UPD parameters to be initialized before SiliconInit */ |
| 264 | void soc_silicon_init_params(SILICON_INIT_UPD *params) |
| 265 | { |
Duncan Laurie | 3745c65 | 2015-08-28 17:21:07 -0700 | [diff] [blame] | 266 | const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); |
| 267 | const struct soc_intel_skylake_config *config = dev->chip_info; |
Subrata Banik | d0def39 | 2015-07-22 12:19:28 +0530 | [diff] [blame] | 268 | u8 irq_config[PCH_MAX_IRQ_CONFIG]; |
| 269 | int i; |
| 270 | int intdeventry; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 271 | |
Duncan Laurie | 3745c65 | 2015-08-28 17:21:07 -0700 | [diff] [blame] | 272 | memcpy(params->SerialIoDevMode, config->SerialIoDevMode, |
| 273 | sizeof(params->SerialIoDevMode)); |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 274 | |
Duncan Laurie | fe86666 | 2015-10-16 13:58:11 -0700 | [diff] [blame] | 275 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| 276 | params->PortUsb20Enable[i] = |
| 277 | config->usb2_ports[i].enable; |
| 278 | params->Usb2AfePetxiset[i] = |
| 279 | config->usb2_ports[i].pre_emp_bias; |
| 280 | params->Usb2AfeTxiset[i] = |
| 281 | config->usb2_ports[i].tx_bias; |
| 282 | params->Usb2AfePredeemp[i] = |
| 283 | config->usb2_ports[i].tx_emp_enable; |
| 284 | params->Usb2AfePehalfbit[i] = |
| 285 | config->usb2_ports[i].pre_emp_bit; |
| 286 | } |
Rizwan Qureshi | 952cb03 | 2015-10-05 19:11:39 +0530 | [diff] [blame] | 287 | |
Duncan Laurie | fe86666 | 2015-10-16 13:58:11 -0700 | [diff] [blame] | 288 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| 289 | params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
| 290 | if (config->usb3_ports[i].tx_de_emp) { |
| 291 | params->Usb3HsioTxDeEmphEnable[i] = 1; |
| 292 | params->Usb3HsioTxDeEmph[i] = |
| 293 | config->usb3_ports[i].tx_de_emp; |
| 294 | } |
| 295 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 296 | params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 297 | params->Usb3HsioTxDownscaleAmp[i] = |
| 298 | config->usb3_ports[i].tx_downscale_amp; |
| 299 | } |
| 300 | } |
Rizwan Qureshi | 952cb03 | 2015-10-05 19:11:39 +0530 | [diff] [blame] | 301 | |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 302 | params->SataSalpSupport = config->SataSalpSupport; |
| 303 | params->SataPortsEnable[0] = config->SataPortsEnable[0]; |
| 304 | params->SsicPortEnable = config->SsicPortEnable; |
| 305 | params->SmbusEnable = config->SmbusEnable; |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 306 | params->ScsEmmcEnabled = config->ScsEmmcEnabled; |
| 307 | params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; |
| 308 | params->ScsSdCardEnabled = config->ScsSdCardEnabled; |
| 309 | params->IshEnable = 0; |
| 310 | params->EnableAzalia = config->EnableAzalia; |
| 311 | params->IoBufferOwnership = config->IoBufferOwnership; |
| 312 | params->DspEnable = config->DspEnable; |
| 313 | params->XdciEnable = config->XdciEnable; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 314 | params->Device4Enable = config->Device4Enable; |
Barnali Sarkar | b090a26 | 2015-09-08 16:00:46 +0530 | [diff] [blame] | 315 | params->RtcLock = config->RtcLock; |
Rizwan Qureshi | 952cb03 | 2015-10-05 19:11:39 +0530 | [diff] [blame] | 316 | params->EnableSata = config->EnableSata; |
| 317 | params->SataMode = config->SataMode; |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 318 | |
| 319 | /* Show SPI controller if enabled in devicetree.cb */ |
| 320 | dev = dev_find_slot(0, PCH_DEVFN_SPI); |
| 321 | params->ShowSpiController = dev->enabled; |
Subrata Banik | d0def39 | 2015-07-22 12:19:28 +0530 | [diff] [blame] | 322 | |
| 323 | /* Get Device Int Count */ |
| 324 | intdeventry = ARRAY_SIZE(devintconfig); |
| 325 | /*update irq table*/ |
| 326 | memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *)(params->DevIntConfigPtr), devintconfig, |
| 327 | intdeventry * sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG)); |
| 328 | |
| 329 | params->NumOfDevIntConfig = intdeventry; |
| 330 | /* PxRC to IRQ programing */ |
| 331 | for (i = 0; i < PCH_MAX_IRQ_CONFIG; i++) { |
| 332 | switch(i) { |
| 333 | case PCH_PARC: |
| 334 | case PCH_PCRC: |
| 335 | case PCH_PDRC: |
| 336 | case PCH_PERC: |
| 337 | case PCH_PFRC: |
| 338 | case PCH_PGRC: |
| 339 | case PCH_PHRC: |
| 340 | irq_config[i] = PCH_IRQ11; |
| 341 | break; |
| 342 | case PCH_PBRC: |
| 343 | irq_config[PCH_PBRC] = PCH_IRQ10; |
| 344 | break; |
| 345 | } |
| 346 | } |
| 347 | memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG); |
| 348 | /* GPIO IRQ Route The valid values is 14 or 15*/ |
| 349 | if(config->GpioIrqSelect == 0) |
| 350 | params->GpioIrqRoute = GPIO_IRQ14; |
| 351 | else |
| 352 | params->GpioIrqRoute = config->GpioIrqSelect; |
| 353 | /* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23*/ |
| 354 | if(config->SciIrqSelect == 0) |
| 355 | params->SciIrqSelect = SCI_IRQ9; |
| 356 | else |
| 357 | params->SciIrqSelect = config->SciIrqSelect; |
| 358 | /* TCO IRQ Select The valid values is 9, 10, 11, 20 21, 22, 23*/ |
| 359 | if(config->TcoIrqSelect == 0) |
| 360 | params->TcoIrqSelect = TCO_IRQ9; |
| 361 | else |
| 362 | params->TcoIrqSelect = config->TcoIrqSelect; |
| 363 | /* TCO Irq enable/disable */ |
| 364 | params->TcoIrqEnable = config->TcoIrqEnable; |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 365 | } |
| 366 | |
| 367 | void soc_display_silicon_init_params(const SILICON_INIT_UPD *original, |
| 368 | SILICON_INIT_UPD *params) |
| 369 | { |
| 370 | /* Display the parameters for SiliconInit */ |
| 371 | printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 372 | fsp_display_upd_value("LogoPtr", 4, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 373 | (uint32_t)original->LogoPtr, |
| 374 | (uint32_t)params->LogoPtr); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 375 | fsp_display_upd_value("LogoSize", 4, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 376 | (uint32_t)original->LogoSize, |
| 377 | (uint32_t)params->LogoSize); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 378 | fsp_display_upd_value("GraphicsConfigPtr", 4, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 379 | (uint32_t)original->GraphicsConfigPtr, |
| 380 | (uint32_t)params->GraphicsConfigPtr); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 381 | fsp_display_upd_value("MicrocodeRegionBase", 4, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 382 | (uint32_t)original->MicrocodeRegionBase, |
| 383 | (uint32_t)params->MicrocodeRegionBase); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 384 | fsp_display_upd_value("MicrocodeRegionSize", 4, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 385 | (uint32_t)original->MicrocodeRegionSize, |
| 386 | (uint32_t)params->MicrocodeRegionSize); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 387 | fsp_display_upd_value("TurboMode", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 388 | (uint32_t)original->TurboMode, |
| 389 | (uint32_t)params->TurboMode); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 390 | fsp_display_upd_value("Device4Enable", 1, |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 391 | original->Device4Enable, |
| 392 | params->Device4Enable); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 393 | fsp_display_upd_value("SataSalpSupport", 1, original->SataSalpSupport, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 394 | params->SataSalpSupport); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 395 | fsp_display_upd_value("SataPortsEnable[0]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 396 | original->SataPortsEnable[0], params->SataPortsEnable[0]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 397 | fsp_display_upd_value("SataPortsEnable[1]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 398 | original->SataPortsEnable[1], params->SataPortsEnable[1]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 399 | fsp_display_upd_value("SataPortsEnable[2]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 400 | original->SataPortsEnable[2], params->SataPortsEnable[2]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 401 | fsp_display_upd_value("SataPortsEnable[3]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 402 | original->SataPortsEnable[3], params->SataPortsEnable[3]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 403 | fsp_display_upd_value("SataPortsEnable[4]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 404 | original->SataPortsEnable[4], params->SataPortsEnable[4]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 405 | fsp_display_upd_value("SataPortsEnable[5]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 406 | original->SataPortsEnable[5], params->SataPortsEnable[5]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 407 | fsp_display_upd_value("SataPortsEnable[6]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 408 | original->SataPortsEnable[6], params->SataPortsEnable[6]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 409 | fsp_display_upd_value("SataPortsEnable[7]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 410 | original->SataPortsEnable[7], params->SataPortsEnable[7]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 411 | fsp_display_upd_value("SataPortsDevSlp[0]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 412 | original->SataPortsDevSlp[0], params->SataPortsDevSlp[0]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 413 | fsp_display_upd_value("SataPortsDevSlp[1]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 414 | original->SataPortsDevSlp[1], params->SataPortsDevSlp[1]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 415 | fsp_display_upd_value("SataPortsDevSlp[2]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 416 | original->SataPortsDevSlp[2], params->SataPortsDevSlp[2]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 417 | fsp_display_upd_value("SataPortsDevSlp[3]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 418 | original->SataPortsDevSlp[3], params->SataPortsDevSlp[3]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 419 | fsp_display_upd_value("SataPortsDevSlp[4]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 420 | original->SataPortsDevSlp[4], params->SataPortsDevSlp[4]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 421 | fsp_display_upd_value("SataPortsDevSlp[5]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 422 | original->SataPortsDevSlp[5], params->SataPortsDevSlp[5]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 423 | fsp_display_upd_value("SataPortsDevSlp[6]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 424 | original->SataPortsDevSlp[6], params->SataPortsDevSlp[6]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 425 | fsp_display_upd_value("SataPortsDevSlp[7]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 426 | original->SataPortsDevSlp[7], params->SataPortsDevSlp[7]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 427 | fsp_display_upd_value("EnableAzalia", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 428 | original->EnableAzalia, params->EnableAzalia); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 429 | fsp_display_upd_value("DspEnable", 1, original->DspEnable, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 430 | params->DspEnable); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 431 | fsp_display_upd_value("IoBufferOwnership", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 432 | original->IoBufferOwnership, params->IoBufferOwnership); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 433 | fsp_display_upd_value("PortUsb20Enable[0]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 434 | original->PortUsb20Enable[0], params->PortUsb20Enable[0]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 435 | fsp_display_upd_value("PortUsb20Enable[1]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 436 | original->PortUsb20Enable[1], params->PortUsb20Enable[1]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 437 | fsp_display_upd_value("PortUsb20Enable[2]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 438 | original->PortUsb20Enable[2], params->PortUsb20Enable[2]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 439 | fsp_display_upd_value("PortUsb20Enable[3]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 440 | original->PortUsb20Enable[3], params->PortUsb20Enable[3]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 441 | fsp_display_upd_value("PortUsb20Enable[4]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 442 | original->PortUsb20Enable[4], params->PortUsb20Enable[4]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 443 | fsp_display_upd_value("PortUsb20Enable[5]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 444 | original->PortUsb20Enable[5], params->PortUsb20Enable[5]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 445 | fsp_display_upd_value("PortUsb20Enable[6]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 446 | original->PortUsb20Enable[6], params->PortUsb20Enable[6]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 447 | fsp_display_upd_value("PortUsb20Enable[7]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 448 | original->PortUsb20Enable[7], params->PortUsb20Enable[7]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 449 | fsp_display_upd_value("PortUsb20Enable[8]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 450 | original->PortUsb20Enable[8], params->PortUsb20Enable[8]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 451 | fsp_display_upd_value("PortUsb20Enable[9]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 452 | original->PortUsb20Enable[9], params->PortUsb20Enable[9]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 453 | fsp_display_upd_value("PortUsb20Enable[10]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 454 | original->PortUsb20Enable[10], params->PortUsb20Enable[10]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 455 | fsp_display_upd_value("PortUsb20Enable[11]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 456 | original->PortUsb20Enable[11], params->PortUsb20Enable[11]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 457 | fsp_display_upd_value("PortUsb20Enable[12]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 458 | original->PortUsb20Enable[12], params->PortUsb20Enable[12]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 459 | fsp_display_upd_value("PortUsb20Enable[13]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 460 | original->PortUsb20Enable[13], params->PortUsb20Enable[13]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 461 | fsp_display_upd_value("PortUsb20Enable[14]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 462 | original->PortUsb20Enable[14], params->PortUsb20Enable[14]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 463 | fsp_display_upd_value("PortUsb20Enable[15]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 464 | original->PortUsb20Enable[15], params->PortUsb20Enable[15]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 465 | fsp_display_upd_value("PortUsb30Enable[0]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 466 | original->PortUsb30Enable[0], params->PortUsb30Enable[0]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 467 | fsp_display_upd_value("PortUsb30Enable[1]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 468 | original->PortUsb30Enable[1], params->PortUsb30Enable[1]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 469 | fsp_display_upd_value("PortUsb30Enable[2]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 470 | original->PortUsb30Enable[2], params->PortUsb30Enable[2]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 471 | fsp_display_upd_value("PortUsb30Enable[3]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 472 | original->PortUsb30Enable[3], params->PortUsb30Enable[3]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 473 | fsp_display_upd_value("PortUsb30Enable[4]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 474 | original->PortUsb30Enable[4], params->PortUsb30Enable[4]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 475 | fsp_display_upd_value("PortUsb30Enable[5]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 476 | original->PortUsb30Enable[5], params->PortUsb30Enable[5]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 477 | fsp_display_upd_value("PortUsb30Enable[6]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 478 | original->PortUsb30Enable[6], params->PortUsb30Enable[6]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 479 | fsp_display_upd_value("PortUsb30Enable[7]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 480 | original->PortUsb30Enable[7], params->PortUsb30Enable[7]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 481 | fsp_display_upd_value("PortUsb30Enable[8]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 482 | original->PortUsb30Enable[8], params->PortUsb30Enable[8]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 483 | fsp_display_upd_value("PortUsb30Enable[9]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 484 | original->PortUsb30Enable[9], params->PortUsb30Enable[9]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 485 | fsp_display_upd_value("XdciEnable", 1, original->XdciEnable, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 486 | params->XdciEnable); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 487 | fsp_display_upd_value("SsicPortEnable", 1, original->SsicPortEnable, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 488 | params->SsicPortEnable); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 489 | fsp_display_upd_value("SmbusEnable", 1, original->SmbusEnable, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 490 | params->SmbusEnable); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 491 | fsp_display_upd_value("SerialIoDevMode[0]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 492 | original->SerialIoDevMode[0], params->SerialIoDevMode[0]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 493 | fsp_display_upd_value("SerialIoDevMode[1]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 494 | original->SerialIoDevMode[1], params->SerialIoDevMode[1]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 495 | fsp_display_upd_value("SerialIoDevMode[2]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 496 | original->SerialIoDevMode[2], params->SerialIoDevMode[2]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 497 | fsp_display_upd_value("SerialIoDevMode[3]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 498 | original->SerialIoDevMode[3], params->SerialIoDevMode[3]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 499 | fsp_display_upd_value("SerialIoDevMode[4]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 500 | original->SerialIoDevMode[4], params->SerialIoDevMode[4]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 501 | fsp_display_upd_value("SerialIoDevMode[5]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 502 | original->SerialIoDevMode[5], params->SerialIoDevMode[5]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 503 | fsp_display_upd_value("SerialIoDevMode[6]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 504 | original->SerialIoDevMode[6], params->SerialIoDevMode[6]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 505 | fsp_display_upd_value("SerialIoDevMode[7]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 506 | original->SerialIoDevMode[7], params->SerialIoDevMode[7]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 507 | fsp_display_upd_value("SerialIoDevMode[8]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 508 | original->SerialIoDevMode[8], params->SerialIoDevMode[8]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 509 | fsp_display_upd_value("SerialIoDevMode[9]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 510 | original->SerialIoDevMode[9], params->SerialIoDevMode[9]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 511 | fsp_display_upd_value("SerialIoDevMode[10]", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 512 | original->SerialIoDevMode[10], params->SerialIoDevMode[10]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 513 | fsp_display_upd_value("ScsEmmcEnabled", 1, original->ScsEmmcEnabled, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 514 | params->ScsEmmcEnabled); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 515 | fsp_display_upd_value("ScsEmmcHs400Enabled", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 516 | original->ScsEmmcHs400Enabled, params->ScsEmmcHs400Enabled); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 517 | fsp_display_upd_value("ScsSdCardEnabled", 1, original->ScsSdCardEnabled, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 518 | params->ScsSdCardEnabled); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 519 | fsp_display_upd_value("IshEnable", 1, original->IshEnable, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 520 | params->IshEnable); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 521 | fsp_display_upd_value("ShowSpiController", 1, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 522 | original->ShowSpiController, params->ShowSpiController); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 523 | fsp_display_upd_value("HsioMessaging", 1, original->HsioMessaging, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 524 | params->HsioMessaging); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 525 | fsp_display_upd_value("Heci3Enabled", 1, original->Heci3Enabled, |
Rizwan Qureshi | 5c1c3d6 | 2015-07-21 20:21:50 +0530 | [diff] [blame] | 526 | params->Heci3Enabled); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 527 | fsp_display_upd_value("RtcLock", 1, original->RtcLock, |
Barnali Sarkar | b090a26 | 2015-09-08 16:00:46 +0530 | [diff] [blame] | 528 | params->RtcLock); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 529 | fsp_display_upd_value("EnableSata", 1, original->EnableSata, |
Rizwan Qureshi | 952cb03 | 2015-10-05 19:11:39 +0530 | [diff] [blame] | 530 | params->EnableSata); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 531 | fsp_display_upd_value("SataMode", 1, original->SataMode, |
Rizwan Qureshi | 952cb03 | 2015-10-05 19:11:39 +0530 | [diff] [blame] | 532 | params->SataMode); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 533 | fsp_display_upd_value("NumOfDevIntConfig", 1, |
Subrata Banik | d0def39 | 2015-07-22 12:19:28 +0530 | [diff] [blame] | 534 | original->NumOfDevIntConfig, |
| 535 | params->NumOfDevIntConfig); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 536 | fsp_display_upd_value("PxRcConfig[PARC]", 1, |
Subrata Banik | d0def39 | 2015-07-22 12:19:28 +0530 | [diff] [blame] | 537 | original->PxRcConfig[PCH_PARC], |
| 538 | params->PxRcConfig[PCH_PARC]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 539 | fsp_display_upd_value("PxRcConfig[PBRC]", 1, |
Subrata Banik | d0def39 | 2015-07-22 12:19:28 +0530 | [diff] [blame] | 540 | original->PxRcConfig[PCH_PBRC], |
| 541 | params->PxRcConfig[PCH_PBRC]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 542 | fsp_display_upd_value("PxRcConfig[PCRC]", 1, |
Subrata Banik | d0def39 | 2015-07-22 12:19:28 +0530 | [diff] [blame] | 543 | original->PxRcConfig[PCH_PCRC], |
| 544 | params->PxRcConfig[PCH_PCRC]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 545 | fsp_display_upd_value("PxRcConfig[PDRC]", 1, |
Subrata Banik | d0def39 | 2015-07-22 12:19:28 +0530 | [diff] [blame] | 546 | original->PxRcConfig[PCH_PDRC], |
| 547 | params->PxRcConfig[PCH_PDRC]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 548 | fsp_display_upd_value("PxRcConfig[PERC]", 1, |
Subrata Banik | d0def39 | 2015-07-22 12:19:28 +0530 | [diff] [blame] | 549 | original->PxRcConfig[PCH_PERC], |
| 550 | params->PxRcConfig[PCH_PERC]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 551 | fsp_display_upd_value("PxRcConfig[PFRC]", 1, |
Subrata Banik | d0def39 | 2015-07-22 12:19:28 +0530 | [diff] [blame] | 552 | original->PxRcConfig[PCH_PFRC], |
| 553 | params->PxRcConfig[PCH_PFRC]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 554 | fsp_display_upd_value("PxRcConfig[PGRC]", 1, |
Subrata Banik | d0def39 | 2015-07-22 12:19:28 +0530 | [diff] [blame] | 555 | original->PxRcConfig[PCH_PGRC], |
| 556 | params->PxRcConfig[PCH_PGRC]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 557 | fsp_display_upd_value("PxRcConfig[PHRC]", 1, |
Subrata Banik | d0def39 | 2015-07-22 12:19:28 +0530 | [diff] [blame] | 558 | original->PxRcConfig[PCH_PHRC], |
| 559 | params->PxRcConfig[PCH_PHRC]); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 560 | fsp_display_upd_value("GpioIrqRoute", 1, |
Subrata Banik | d0def39 | 2015-07-22 12:19:28 +0530 | [diff] [blame] | 561 | original->GpioIrqRoute, |
| 562 | params->GpioIrqRoute); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 563 | fsp_display_upd_value("SciIrqSelect", 1, |
Subrata Banik | d0def39 | 2015-07-22 12:19:28 +0530 | [diff] [blame] | 564 | original->SciIrqSelect, |
| 565 | params->SciIrqSelect); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 566 | fsp_display_upd_value("TcoIrqSelect", 1, |
Subrata Banik | d0def39 | 2015-07-22 12:19:28 +0530 | [diff] [blame] | 567 | original->TcoIrqSelect, |
| 568 | params->TcoIrqSelect); |
Lee Leahy | 66208bd | 2015-10-15 16:17:58 -0700 | [diff] [blame] | 569 | fsp_display_upd_value("TcoIrqEnable", 1, |
Subrata Banik | d0def39 | 2015-07-22 12:19:28 +0530 | [diff] [blame] | 570 | original->TcoIrqEnable, |
| 571 | params->TcoIrqEnable); |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 572 | } |
| 573 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 574 | static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 575 | { |
| 576 | if (!vendor || !device) |
| 577 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 578 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 579 | else |
| 580 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 581 | (device << 16) | vendor); |
| 582 | } |
| 583 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 584 | struct pci_operations soc_pci_ops = { |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 585 | .set_subsystem = &pci_set_subsystem |
| 586 | }; |