Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <string.h> |
| 19 | #include <lib.h> |
| 20 | #include <timestamp.h> |
| 21 | #include <arch/io.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 22 | #include <device/pci_def.h> |
| 23 | #include <device/pnp_def.h> |
| 24 | #include <cpu/x86/lapic.h> |
| 25 | #include <pc80/mc146818rtc.h> |
Kyösti Mälkki | 6722f8d | 2014-06-16 09:14:49 +0300 | [diff] [blame] | 26 | #include <arch/acpi.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 27 | #include <cbmem.h> |
| 28 | #include <console/console.h> |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 29 | #include <bootmode.h> |
Edward O'Callaghan | 1b3acb1 | 2014-06-01 18:04:05 +1000 | [diff] [blame] | 30 | #include <superio/ite/common/ite.h> |
| 31 | #include <superio/ite/it8772f/it8772f.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 32 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 33 | #include <northbridge/intel/sandybridge/raminit.h> |
| 34 | #include <southbridge/intel/bd82x6x/pch.h> |
| 35 | #include <southbridge/intel/bd82x6x/gpio.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 36 | #include <arch/cpu.h> |
| 37 | #include <cpu/x86/bist.h> |
| 38 | #include <cpu/x86/msr.h> |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 39 | #include <halt.h> |
Vladimir Serbinenko | 0e90dae | 2015-05-18 10:29:06 +0200 | [diff] [blame] | 40 | #include <tpm.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 41 | #include "gpio.h" |
Kyösti Mälkki | afa7b13 | 2014-02-13 17:16:22 +0200 | [diff] [blame] | 42 | #if CONFIG_DRIVERS_UART_8250IO |
Edward O'Callaghan | 74834e0 | 2015-01-04 04:17:35 +1100 | [diff] [blame] | 43 | #include <superio/smsc/lpc47n207/lpc47n207.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 44 | #endif |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 45 | |
| 46 | /* Stumpy USB Reset Disable defined in cmos.layout */ |
| 47 | #if CONFIG_USE_OPTION_TABLE |
| 48 | #include "option_table.h" |
| 49 | #define CMOS_USB_RESET_DISABLE (CMOS_VSTART_stumpy_usb_reset_disable >> 3) |
| 50 | #else |
| 51 | #define CMOS_USB_RESET_DISABLE (400 >> 3) |
| 52 | #endif |
| 53 | #define USB_RESET_DISABLE_MAGIC (0xdd) /* Disable if set to this */ |
| 54 | |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 55 | #define DUMMY_DEV PNP_DEV(0x2e, 0) |
Edward O'Callaghan | 1b3acb1 | 2014-06-01 18:04:05 +1000 | [diff] [blame] | 56 | #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) |
| 57 | #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) |
| 58 | |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 59 | static void pch_enable_lpc(void) |
| 60 | { |
| 61 | /* Set COM1/COM2 decode range */ |
| 62 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); |
| 63 | |
Kyösti Mälkki | afa7b13 | 2014-02-13 17:16:22 +0200 | [diff] [blame] | 64 | #if CONFIG_DRIVERS_UART_8250IO |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 65 | /* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/ |
| 66 | pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\ |
| 67 | CNF2_LPC_EN | COMA_LPC_EN); |
| 68 | |
| 69 | /* map full 256 bytes at 0x1600 to the LPC bus */ |
| 70 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601); |
| 71 | |
| 72 | try_enabling_LPC47N207_uart(); |
| 73 | #else |
| 74 | /* Enable SuperIO + PS/2 Keyboard/Mouse */ |
| 75 | pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN); |
| 76 | #endif |
| 77 | } |
| 78 | |
| 79 | static void rcba_config(void) |
| 80 | { |
| 81 | u32 reg32; |
| 82 | |
Kyösti Mälkki | 6f49906 | 2015-06-06 11:52:24 +0300 | [diff] [blame] | 83 | /* |
| 84 | * GFX INTA -> PIRQA (MSI) |
| 85 | * D28IP_P1IP WLAN INTA -> PIRQB |
| 86 | * D28IP_P4IP ETH0 INTB -> PIRQC |
| 87 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 88 | * D26IP_E2P EHCI2 INTA -> PIRQE |
| 89 | * D31IP_SIP SATA INTA -> PIRQF (MSI) |
| 90 | * D31IP_SMIP SMBUS INTB -> PIRQG |
| 91 | * D31IP_TTIP THRT INTC -> PIRQH |
| 92 | * D27IP_ZIP HDA INTA -> PIRQG (MSI) |
| 93 | */ |
| 94 | |
| 95 | /* Device interrupt pin register (board specific) */ |
| 96 | RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 97 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 98 | RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| 99 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 100 | RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | |
| 101 | (INTB << D28IP_P4IP); |
| 102 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 103 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 104 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 105 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 106 | |
| 107 | /* Device interrupt route registers */ |
| 108 | DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA); |
| 109 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 110 | DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); |
| 111 | DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); |
| 112 | DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); |
| 113 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 114 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 115 | |
| 116 | /* Enable IOAPIC (generic) */ |
| 117 | RCBA16(OIC) = 0x0100; |
| 118 | /* PCH BWG says to read back the IOAPIC enable register */ |
| 119 | (void) RCBA16(OIC); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 120 | |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 121 | /* Disable unused devices (board specific) */ |
| 122 | reg32 = RCBA32(FD); |
| 123 | reg32 |= PCH_DISABLE_ALWAYS; |
| 124 | RCBA32(FD) = reg32; |
| 125 | } |
| 126 | |
| 127 | static void early_pch_init(void) |
| 128 | { |
| 129 | u8 reg8; |
| 130 | |
| 131 | // reset rtc power status |
| 132 | reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); |
| 133 | reg8 &= ~(1 << 2); |
| 134 | pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); |
| 135 | } |
| 136 | |
| 137 | static void setup_sio_gpios(void) |
| 138 | { |
| 139 | /* |
| 140 | * GPIO10 as USBPWRON12# |
| 141 | * GPIO12 as USBPWRON13# |
| 142 | */ |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 143 | it8772f_gpio_setup(DUMMY_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 144 | |
| 145 | /* |
| 146 | * GPIO22 as wake SCI# |
| 147 | */ |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 148 | it8772f_gpio_setup(DUMMY_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 149 | |
| 150 | /* |
| 151 | * GPIO32 as EXTSMI# |
| 152 | */ |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 153 | it8772f_gpio_setup(DUMMY_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 154 | |
| 155 | /* |
| 156 | * GPIO45 as LED_POWER# |
| 157 | */ |
david | 80ef7b7 | 2015-01-19 17:11:36 +0800 | [diff] [blame] | 158 | it8772f_gpio_led(DUMMY_DEV, 4 /* set */, (0x1<<5) /* select */, |
| 159 | 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, |
| 160 | (0x1<<5) /* output */, (0x1<<5) /* 1=Simple IO function */, |
| 161 | SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 162 | |
| 163 | /* |
| 164 | * GPIO51 as USBPWRON8# |
| 165 | * GPIO52 as USBPWRON1# |
| 166 | */ |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 167 | it8772f_gpio_setup(DUMMY_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06); |
| 168 | it8772f_gpio_setup(DUMMY_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 169 | } |
| 170 | |
Aaron Durbin | a0a3727 | 2014-08-14 08:35:11 -0500 | [diff] [blame] | 171 | #include <cpu/intel/romstage.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 172 | void main(unsigned long bist) |
| 173 | { |
| 174 | int boot_mode = 0; |
| 175 | int cbmem_was_initted; |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 176 | |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 177 | struct pei_data pei_data = { |
Edward O'Callaghan | b27d360 | 2014-05-24 02:40:31 +1000 | [diff] [blame] | 178 | .pei_version = PEI_VERSION, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 179 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 180 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
Edward O'Callaghan | b27d360 | 2014-05-24 02:40:31 +1000 | [diff] [blame] | 181 | .epbar = DEFAULT_EPBAR, |
| 182 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 183 | .smbusbar = SMBUS_IO_BASE, |
| 184 | .wdbbar = 0x4000000, |
| 185 | .wdbsize = 0x1000, |
| 186 | .hpet_address = CONFIG_HPET_ADDRESS, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 187 | .rcba = (uintptr_t)DEFAULT_RCBABASE, |
Edward O'Callaghan | b27d360 | 2014-05-24 02:40:31 +1000 | [diff] [blame] | 188 | .pmbase = DEFAULT_PMBASE, |
| 189 | .gpiobase = DEFAULT_GPIOBASE, |
| 190 | .thermalbase = 0xfed08000, |
| 191 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 192 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 193 | .spd_addresses = { 0xa0, 0x00,0xa4,0x00 }, |
| 194 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 195 | .ec_present = 0, |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 196 | // 0 = leave channel enabled |
| 197 | // 1 = disable dimm 0 on channel |
| 198 | // 2 = disable dimm 1 on channel |
| 199 | // 3 = disable dimm 0+1 on channel |
Edward O'Callaghan | b27d360 | 2014-05-24 02:40:31 +1000 | [diff] [blame] | 200 | .dimm_channel0_disabled = 2, |
| 201 | .dimm_channel1_disabled = 2, |
| 202 | .max_ddr3_freq = 1333, |
| 203 | .usb_port_config = { |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 204 | { 1, 0, 0x0080 }, /* P0: Front port (OC0) */ |
| 205 | { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ |
| 206 | { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ |
| 207 | { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ |
| 208 | { 1, 2, 0x0080 }, /* P4: Front port (OC2) */ |
| 209 | { 0, 0, 0x0000 }, /* P5: Empty */ |
| 210 | { 0, 0, 0x0000 }, /* P6: Empty */ |
| 211 | { 0, 0, 0x0000 }, /* P7: Empty */ |
| 212 | { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ |
| 213 | { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ |
| 214 | { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ |
| 215 | { 0, 4, 0x0000 }, /* P11: Empty */ |
| 216 | { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ |
| 217 | { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ |
| 218 | }, |
| 219 | }; |
| 220 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 221 | timestamp_init(get_initial_timestamp()); |
| 222 | timestamp_add_now(TS_START_ROMSTAGE); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 223 | |
| 224 | if (bist == 0) |
| 225 | enable_lapic(); |
| 226 | |
| 227 | pch_enable_lpc(); |
| 228 | |
| 229 | /* Enable GPIOs */ |
| 230 | pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); |
| 231 | pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); |
| 232 | setup_pch_gpios(&stumpy_gpio_map); |
| 233 | setup_sio_gpios(); |
| 234 | |
| 235 | /* Early SuperIO setup */ |
Edward O'Callaghan | 1f9653a | 2014-07-14 16:31:25 +1000 | [diff] [blame] | 236 | it8772f_ac_resume_southbridge(DUMMY_DEV); |
Edward O'Callaghan | 1b3acb1 | 2014-06-01 18:04:05 +1000 | [diff] [blame] | 237 | ite_kill_watchdog(GPIO_DEV); |
| 238 | ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 239 | console_init(); |
| 240 | |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 241 | init_bootmode_straps(); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 242 | |
| 243 | /* Halt if there was a built in self test failure */ |
| 244 | report_bist_failure(bist); |
| 245 | |
| 246 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 247 | printk(BIOS_DEBUG, "soft reset detected\n"); |
| 248 | boot_mode = 1; |
| 249 | |
| 250 | /* System is not happy after keyboard reset... */ |
| 251 | printk(BIOS_DEBUG, "Issuing CF9 warm reset\n"); |
| 252 | outb(0x6, 0xcf9); |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 253 | halt(); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 254 | } |
| 255 | |
| 256 | /* Perform some early chipset initialization required |
| 257 | * before RAM initialization can work |
| 258 | */ |
| 259 | sandybridge_early_initialization(SANDYBRIDGE_MOBILE); |
| 260 | printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); |
| 261 | |
Vladimir Serbinenko | 332f14b | 2014-09-05 16:29:41 +0200 | [diff] [blame] | 262 | boot_mode = southbridge_detect_s3_resume() ? 2 : 0; |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 263 | |
| 264 | post_code(0x38); |
| 265 | /* Enable SPD ROMs and DDR-III DRAM */ |
| 266 | enable_smbus(); |
| 267 | |
| 268 | /* Prepare USB controller early in S3 resume */ |
| 269 | if (boot_mode == 2) { |
| 270 | /* |
| 271 | * For Stumpy the back USB ports are reset on resume |
| 272 | * so default to resetting the controller to make the |
| 273 | * kernel happy. There is a CMOS flag to disable the |
| 274 | * controller reset in case the kernel can tolerate |
| 275 | * the device power loss better in the future. |
| 276 | */ |
| 277 | u8 magic = cmos_read(CMOS_USB_RESET_DISABLE); |
| 278 | |
| 279 | if (magic == USB_RESET_DISABLE_MAGIC) { |
| 280 | printk(BIOS_DEBUG, "USB Controller Reset Disabled\n"); |
| 281 | enable_usb_bar(); |
| 282 | } else { |
| 283 | printk(BIOS_DEBUG, "USB Controller Reset Enabled\n"); |
| 284 | } |
| 285 | } else { |
| 286 | /* Ensure USB reset on resume is enabled at boot */ |
| 287 | cmos_write(0, CMOS_USB_RESET_DISABLE); |
| 288 | } |
| 289 | |
| 290 | post_code(0x39); |
| 291 | pei_data.boot_mode = boot_mode; |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 292 | timestamp_add_now(TS_BEFORE_INITRAM); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 293 | sdram_initialize(&pei_data); |
| 294 | |
Kyösti Mälkki | 3d45c40 | 2013-09-07 20:26:36 +0300 | [diff] [blame] | 295 | timestamp_add_now(TS_AFTER_INITRAM); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 296 | post_code(0x3a); |
| 297 | /* Perform some initialization that must run before stage2 */ |
| 298 | early_pch_init(); |
| 299 | post_code(0x3b); |
| 300 | |
| 301 | rcba_config(); |
| 302 | post_code(0x3c); |
| 303 | |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 304 | quick_ram_check(); |
Stefan Reinauer | afcaac2 | 2012-06-18 15:43:50 -0700 | [diff] [blame] | 305 | post_code(0x3e); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 306 | |
Kyösti Mälkki | 2d8520b | 2014-01-06 17:20:31 +0200 | [diff] [blame] | 307 | cbmem_was_initted = !cbmem_recovery(boot_mode==2); |
Kyösti Mälkki | 7893848 | 2014-01-04 11:02:45 +0200 | [diff] [blame] | 308 | if (boot_mode!=2) |
| 309 | save_mrc_data(&pei_data); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 310 | |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 311 | if (boot_mode==2 && !cbmem_was_initted) { |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 312 | /* Failed S3 resume, reset to come up cleanly */ |
| 313 | outb(0x6, 0xcf9); |
Patrick Georgi | bd79c5e | 2014-11-28 22:35:36 +0100 | [diff] [blame] | 314 | halt(); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 315 | } |
Vladimir Serbinenko | c845b43 | 2014-09-05 03:37:44 +0200 | [diff] [blame] | 316 | northbridge_romstage_finalize(boot_mode==2); |
| 317 | |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 318 | post_code(0x3f); |
Vladimir Serbinenko | 0e90dae | 2015-05-18 10:29:06 +0200 | [diff] [blame] | 319 | if (CONFIG_LPC_TPM) { |
| 320 | init_tpm(boot_mode == 2); |
| 321 | } |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 322 | } |