Angel Pons | f94ac9a | 2020-04-05 15:46:48 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 2 | |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
| 6 | #include <device/pci_ids.h> |
| 7 | #include <device/pci_ops.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 9 | #include <soc/adsp.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 10 | #include <soc/pch.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 11 | #include <soc/rcba.h> |
Angel Pons | 3cc2c38 | 2020-10-23 20:38:23 +0200 | [diff] [blame] | 12 | #include <soc/intel/broadwell/pch/chip.h> |
Angel Pons | c423ce2 | 2021-04-19 16:13:31 +0200 | [diff] [blame] | 13 | #include <southbridge/intel/lynxpoint/iobp.h> |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 14 | |
| 15 | static void adsp_init(struct device *dev) |
| 16 | { |
Angel Pons | 3cc2c38 | 2020-10-23 20:38:23 +0200 | [diff] [blame] | 17 | const struct soc_intel_broadwell_pch_config *config = config_of(dev); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 18 | struct resource *bar0, *bar1; |
| 19 | u32 tmp32; |
| 20 | |
| 21 | /* Ensure memory and bus master are enabled */ |
Elyes HAOUAS | b887adf | 2020-04-29 10:42:34 +0200 | [diff] [blame] | 22 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 23 | |
| 24 | /* Find BAR0 and BAR1 */ |
| 25 | bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 26 | if (!bar0) |
| 27 | return; |
| 28 | bar1 = find_resource(dev, PCI_BASE_ADDRESS_1); |
| 29 | if (!bar1) |
| 30 | return; |
| 31 | |
| 32 | /* |
| 33 | * Set LTR value in DSP shim LTR control register to 3ms |
| 34 | * SNOOP_REQ[13]=1b SNOOP_SCALE[12:10]=100b (1ms) SNOOP_VAL[9:0]=3h |
| 35 | */ |
| 36 | tmp32 = pch_is_wpt() ? ADSP_SHIM_BASE_WPT : ADSP_SHIM_BASE_LPT; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 37 | write32(res2mmio(bar0, tmp32 + ADSP_SHIM_LTRC, 0), |
| 38 | ADSP_SHIM_LTRC_VALUE); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 39 | |
| 40 | /* Program VDRTCTL2 D19:F0:A8[31:0] = 0x00000fff */ |
| 41 | pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE); |
| 42 | |
| 43 | /* Program ADSP IOBP VDLDAT1 to 0x040100 */ |
| 44 | pch_iobp_write(ADSP_IOBP_VDLDAT1, ADSP_VDLDAT1_VALUE); |
| 45 | |
| 46 | /* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */ |
| 47 | tmp32 = pci_read_config32(dev, ADSP_PCI_VDRTCTL0); |
Duncan Laurie | d9f9507 | 2014-10-01 13:47:20 -0700 | [diff] [blame] | 48 | if (pch_is_wpt()) { |
| 49 | if (config->adsp_d3_pg_enable) { |
| 50 | tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT; |
| 51 | if (config->adsp_sram_pg_enable) |
| 52 | tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT; |
| 53 | else |
| 54 | tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_WPT; |
Duncan Laurie | 3ed4d39 | 2014-07-31 10:41:56 -0700 | [diff] [blame] | 55 | } else { |
Duncan Laurie | d9f9507 | 2014-10-01 13:47:20 -0700 | [diff] [blame] | 56 | tmp32 |= ADSP_VDRTCTL0_D3PGD_WPT; |
Duncan Laurie | 3ed4d39 | 2014-07-31 10:41:56 -0700 | [diff] [blame] | 57 | } |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 58 | } else { |
Duncan Laurie | d9f9507 | 2014-10-01 13:47:20 -0700 | [diff] [blame] | 59 | if (config->adsp_d3_pg_enable) { |
Duncan Laurie | 3ed4d39 | 2014-07-31 10:41:56 -0700 | [diff] [blame] | 60 | tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT; |
Duncan Laurie | d9f9507 | 2014-10-01 13:47:20 -0700 | [diff] [blame] | 61 | if (config->adsp_sram_pg_enable) |
| 62 | tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT; |
| 63 | else |
| 64 | tmp32 |= ADSP_VDRTCTL0_D3SRAMPGD_LPT; |
| 65 | } else { |
| 66 | tmp32 |= ADSP_VDRTCTL0_D3PGD_LPT; |
Duncan Laurie | 3ed4d39 | 2014-07-31 10:41:56 -0700 | [diff] [blame] | 67 | } |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 68 | } |
| 69 | pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32); |
| 70 | |
| 71 | /* Set PSF Snoop to SA, RCBA+0x3350[10]=1b */ |
| 72 | RCBA32_OR(0x3350, (1 << 10)); |
| 73 | |
| 74 | /* Set DSP IOBP PMCTL 0x1e0=0x3f */ |
| 75 | pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE); |
| 76 | |
| 77 | if (config->sio_acpi_mode) { |
Kyösti Mälkki | 4abc731 | 2021-01-12 17:46:30 +0200 | [diff] [blame] | 78 | /* Configure for ACPI mode */ |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 79 | printk(BIOS_INFO, "ADSP: Enable ACPI Mode IRQ3\n"); |
| 80 | |
Angel Pons | 34bd6ba | 2021-04-19 22:38:55 +0200 | [diff] [blame] | 81 | /* Save BAR0 and BAR1 */ |
| 82 | struct pch_acpi_device_state *state = get_acpi_device_state(PCH_ACPI_ADSP); |
| 83 | state->enable = 1; |
| 84 | state->bar0 = (u32)bar0->base; |
| 85 | state->bar1 = (u32)bar1->base; |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 86 | |
| 87 | /* Set PCI Config Disable Bit */ |
| 88 | pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~0, ADSP_PCICFGCTL_PCICD); |
| 89 | |
| 90 | /* Set interrupt de-assert/assert opcode override to IRQ3 */ |
| 91 | pch_iobp_write(ADSP_IOBP_VDLDAT2, ADSP_IOBP_ACPI_IRQ3); |
| 92 | |
| 93 | /* Enable IRQ3 in RCBA */ |
| 94 | RCBA32_OR(ACPIIRQEN, ADSP_ACPI_IRQEN); |
| 95 | |
| 96 | /* Set ACPI Interrupt Enable Bit */ |
| 97 | pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~ADSP_PCICFGCTL_SPCBAD, |
| 98 | ADSP_PCICFGCTL_ACPIIE); |
| 99 | |
| 100 | /* Put ADSP in D3hot */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 101 | tmp32 = read32(res2mmio(bar1, PCH_PCS, 0)); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 102 | tmp32 |= PCH_PCS_PS_D3HOT; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 103 | write32(res2mmio(bar1, PCH_PCS, 0), tmp32); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 104 | } else { |
| 105 | printk(BIOS_INFO, "ADSP: Enable PCI Mode IRQ23\n"); |
| 106 | |
| 107 | /* Configure for PCI mode */ |
Elyes HAOUAS | fac2893 | 2020-05-03 08:30:09 +0200 | [diff] [blame] | 108 | pci_write_config8(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ); |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 109 | |
| 110 | /* Clear ACPI Interrupt Enable Bit */ |
| 111 | pch_iobp_update(ADSP_IOBP_PCICFGCTL, |
| 112 | ~(ADSP_PCICFGCTL_SPCBAD | ADSP_PCICFGCTL_ACPIIE), 0); |
| 113 | } |
| 114 | } |
| 115 | |
| 116 | static struct device_operations adsp_ops = { |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 117 | .read_resources = pci_dev_read_resources, |
| 118 | .set_resources = pci_dev_set_resources, |
| 119 | .enable_resources = pci_dev_enable_resources, |
| 120 | .init = adsp_init, |
Angel Pons | cb2080f | 2020-10-23 15:45:44 +0200 | [diff] [blame] | 121 | .ops_pci = &pci_dev_ops_pci, |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 122 | }; |
| 123 | |
| 124 | static const unsigned short pci_device_ids[] = { |
| 125 | 0x9c36, /* LynxPoint */ |
| 126 | 0x9cb6, /* WildcatPoint */ |
| 127 | 0 |
| 128 | }; |
| 129 | |
| 130 | static const struct pci_driver pch_adsp __pci_driver = { |
| 131 | .ops = &adsp_ops, |
| 132 | .vendor = PCI_VENDOR_ID_INTEL, |
| 133 | .devices = pci_device_ids, |
| 134 | }; |