Angel Pons | 381c4eb | 2020-04-03 01:22:06 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 2 | |
Alexandru Gagniuc | c4e7db5 | 2014-04-05 13:40:33 -0500 | [diff] [blame] | 3 | #include "mainboard.h" |
| 4 | |
Alexandru Gagniuc | 1d87dac | 2014-03-28 14:48:13 -0500 | [diff] [blame] | 5 | #include <vendorcode/amd/agesa/f15tn/AGESA.h> |
| 6 | |
Angel Pons | 66ee42d | 2020-05-20 23:34:54 +0200 | [diff] [blame] | 7 | /* Include the files that instantiate the configuration definitions. */ |
Alexandru Gagniuc | 1d87dac | 2014-03-28 14:48:13 -0500 | [diff] [blame] | 8 | #include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> |
Alexandru Gagniuc | 1d87dac | 2014-03-28 14:48:13 -0500 | [diff] [blame] | 9 | #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> |
| 10 | #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> |
| 11 | #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> |
Angel Pons | db2e118 | 2020-05-22 21:34:10 +0200 | [diff] [blame] | 12 | /* AGESA nonsense: the next two headers depend on heapManager.h */ |
Alexandru Gagniuc | 1d87dac | 2014-03-28 14:48:13 -0500 | [diff] [blame] | 13 | #include <vendorcode/amd/agesa/f15tn/Proc/Common/CreateStruct.h> |
| 14 | #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEarlyInit.h> |
| 15 | /* These tables are optional and may be used to adjust memory timing settings */ |
| 16 | #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mm.h> |
| 17 | #include <vendorcode/amd/agesa/f15tn/Proc/Mem/mn.h> |
| 18 | |
Angel Pons | db2e118 | 2020-05-22 21:34:10 +0200 | [diff] [blame] | 19 | /* Select the CPU family */ |
| 20 | #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 21 | |
Angel Pons | db2e118 | 2020-05-22 21:34:10 +0200 | [diff] [blame] | 22 | /* Select the CPU socket type */ |
| 23 | #define INSTALL_FS1_SOCKET_SUPPORT TRUE |
| 24 | #define INSTALL_FP2_SOCKET_SUPPORT TRUE |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 25 | |
Angel Pons | db2e118 | 2020-05-22 21:34:10 +0200 | [diff] [blame] | 26 | //#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE |
| 27 | //#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE |
| 28 | #define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE |
| 29 | //#define BLDOPT_REMOVE_ECC_SUPPORT TRUE |
| 30 | #define BLDOPT_REMOVE_SRAT FALSE |
| 31 | #define BLDOPT_REMOVE_WHEA FALSE |
Paul Menzel | d354c08 | 2020-10-17 13:10:32 +0200 | [diff] [blame] | 32 | #define BLDOPT_REMOVE_CRAT TRUE |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 33 | |
Angel Pons | db2e118 | 2020-05-22 21:34:10 +0200 | [diff] [blame] | 34 | /* Build configuration values here. */ |
| 35 | #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 36 | |
Angel Pons | db2e118 | 2020-05-22 21:34:10 +0200 | [diff] [blame] | 37 | #define BLDCFG_MEMORY_RDIMM_CAPABLE FALSE |
| 38 | #define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE |
| 39 | #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE |
| 40 | #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE |
| 41 | #define BLDCFG_ENABLE_ECC_FEATURE TRUE |
| 42 | #define BLDCFG_ECC_SYNC_FLOOD FALSE |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 43 | |
Angel Pons | db2e118 | 2020-05-22 21:34:10 +0200 | [diff] [blame] | 44 | #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED |
| 45 | #define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* (0x2000 << 16) = 512M */ |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 46 | |
Angel Pons | db2e118 | 2020-05-22 21:34:10 +0200 | [diff] [blame] | 47 | #define BLDCFG_IOMMU_SUPPORT TRUE |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 48 | |
Angel Pons | db2e118 | 2020-05-22 21:34:10 +0200 | [diff] [blame] | 49 | #define BLDCFG_CFG_GNB_HD_AUDIO TRUE |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 50 | |
Alexandru Gagniuc | 5405d3f | 2014-04-09 16:14:25 -0500 | [diff] [blame] | 51 | /* |
| 52 | * The GPIO control is not well documented in AGESA, but is in the BKDG |
| 53 | * |
| 54 | * Eg. FANIN1/GPIO57 on datasheet means power-on default (Function0) is to route |
| 55 | * from this ball to hardware monitor as FAN1 tacho input. Selecting Function1 |
| 56 | * routes this to the GPIO block instead. Seems ACPI GPIOs and related GEVENTs |
| 57 | * are mostly in Function1, sometimes Function2. |
| 58 | * |
| 59 | * Note that the GpioOut bit does not mean that the GPIO is an output. That bit |
| 60 | * actually controls the output value, so GpioOut means "default to set". |
| 61 | * PullUpB is an inverted logic, so setting this bit means we're actually |
| 62 | * disabling the internal pull-up. The PullDown bit is NOT inverted logic. |
| 63 | * The output driver can be disabled with the GpioOutEnB bit, which is again, |
| 64 | * inverted logic. To make the list more readable, we define a few local macros |
| 65 | * to state what we mean. |
| 66 | */ |
| 67 | #define OUTPUT_HIGH (GpioOut) |
| 68 | #define OUTPUT_LOW (0) |
| 69 | #define INPUT (GpioOutEnB) |
| 70 | #define PULL_UP (0) |
| 71 | #define PULL_DOWN (PullDown | PullUpB) |
| 72 | #define PULL_NONE (PullUpB) |
| 73 | |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 74 | CONST GPIO_CONTROL pavilion_m6_1035dx_gpio[] = { |
Alexandru Gagniuc | 5405d3f | 2014-04-09 16:14:25 -0500 | [diff] [blame] | 75 | {57, Function1, OUTPUT_HIGH | PULL_NONE}, /* WLAN enable */ |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 76 | {-1} |
| 77 | }; |
Angel Pons | db2e118 | 2020-05-22 21:34:10 +0200 | [diff] [blame] | 78 | #define BLDCFG_FCH_GPIO_CONTROL_LIST (pavilion_m6_1035dx_gpio) |
Alexandru Gagniuc | fccfee3 | 2014-03-26 18:51:08 -0500 | [diff] [blame] | 79 | |
Angel Pons | db2e118 | 2020-05-22 21:34:10 +0200 | [diff] [blame] | 80 | /* |
| 81 | * These definitions could be moved to a common Hudson header, should we decide |
Alexandru Gagniuc | 7efd5fd | 2014-04-19 13:36:49 -0500 | [diff] [blame] | 82 | * to provide our own, saner SCI mapping function |
| 83 | */ |
Alexandru Gagniuc | c4e7db5 | 2014-04-05 13:40:33 -0500 | [diff] [blame] | 84 | #define GEVENT_PIN(gpe) ((gpe) + 0x40) |
Alexandru Gagniuc | 7efd5fd | 2014-04-19 13:36:49 -0500 | [diff] [blame] | 85 | #define SCI_MAP_OHCI_12_0 0x58 |
| 86 | #define SCI_MAP_OHCI_13_0 0x59 |
| 87 | #define SCI_MAP_XHCI_10_0 0x78 |
| 88 | #define SCI_MAP_PWRBTN 0x73 |
Alexandru Gagniuc | c4e7db5 | 2014-04-05 13:40:33 -0500 | [diff] [blame] | 89 | |
Arthur Heymans | 8d3640d | 2022-05-16 12:27:36 +0200 | [diff] [blame^] | 90 | CONST SCI_MAP_CONTROL m6_1035dx_sci_map[] = { |
Elyes HAOUAS | a342f39 | 2018-10-17 10:56:26 +0200 | [diff] [blame] | 91 | {GEVENT_PIN(EC_SCI_GEVENT), EC_SCI_GPE}, |
| 92 | {GEVENT_PIN(EC_LID_GEVENT), EC_LID_GPE}, |
| 93 | {GEVENT_PIN(PCIE_GEVENT), PCIE_GPE}, |
Alexandru Gagniuc | 7efd5fd | 2014-04-19 13:36:49 -0500 | [diff] [blame] | 94 | {SCI_MAP_OHCI_12_0, PME_GPE}, |
| 95 | {SCI_MAP_OHCI_13_0, PME_GPE}, |
| 96 | {SCI_MAP_XHCI_10_0, PME_GPE}, |
| 97 | {SCI_MAP_PWRBTN, PME_GPE}, |
Alexandru Gagniuc | c4e7db5 | 2014-04-05 13:40:33 -0500 | [diff] [blame] | 98 | }; |
Angel Pons | db2e118 | 2020-05-22 21:34:10 +0200 | [diff] [blame] | 99 | #define BLDCFG_FCH_SCI_MAP_LIST (m6_1035dx_sci_map) |
Alexandru Gagniuc | c4e7db5 | 2014-04-05 13:40:33 -0500 | [diff] [blame] | 100 | |
Angel Pons | db2e118 | 2020-05-22 21:34:10 +0200 | [diff] [blame] | 101 | /* |
| 102 | * Process the options... |
| 103 | * This file include MUST occur AFTER the user option selection settings. |
| 104 | * AGESA nonsense: Moving this include up will break AGESA. |
| 105 | */ |
Kyösti Mälkki | c8e4742 | 2017-08-31 08:52:12 +0300 | [diff] [blame] | 106 | #include <PlatformInstall.h> |