Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 4 | * Copyright (C) 2015 Intel Corp. |
| 5 | * |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #define __SIMPLE_DEVICE__ |
| 17 | |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 18 | #include <assert.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 19 | #include <stdint.h> |
| 20 | #include <arch/io.h> |
Marshall Dawson | 94ee937 | 2017-06-15 12:18:23 -0600 | [diff] [blame] | 21 | #include <cpu/x86/msr.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 22 | #include <cpu/amd/msr.h> |
Marshall Dawson | 94ee937 | 2017-06-15 12:18:23 -0600 | [diff] [blame] | 23 | #include <cpu/amd/mtrr.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 24 | #include <cbmem.h> |
Marshall Dawson | f3c57a7c | 2018-01-29 18:08:16 -0700 | [diff] [blame] | 25 | #include <stage_cache.h> |
Marshall Dawson | 4b0f6fa | 2018-09-04 13:08:25 -0600 | [diff] [blame] | 26 | #include <arch/bert_storage.h> |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 27 | #include <soc/northbridge.h> |
Marshall Dawson | 22f54c5 | 2017-11-29 09:30:23 -0700 | [diff] [blame] | 28 | #include <soc/southbridge.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 29 | |
| 30 | void backup_top_of_low_cacheable(uintptr_t ramtop) |
| 31 | { |
Marshall Dawson | 22f54c5 | 2017-11-29 09:30:23 -0700 | [diff] [blame] | 32 | biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 33 | } |
| 34 | |
| 35 | uintptr_t restore_top_of_low_cacheable(void) |
| 36 | { |
Marshall Dawson | 22f54c5 | 2017-11-29 09:30:23 -0700 | [diff] [blame] | 37 | return biosram_read32(BIOSRAM_CBMEM_TOP); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 38 | } |
Marshall Dawson | 94ee937 | 2017-06-15 12:18:23 -0600 | [diff] [blame] | 39 | |
Marshall Dawson | 4b0f6fa | 2018-09-04 13:08:25 -0600 | [diff] [blame] | 40 | #if IS_ENABLED(CONFIG_ACPI_BERT) |
Marshall Dawson | f0de242 | 2018-09-10 13:28:49 -0600 | [diff] [blame] | 41 | #if CONFIG_SMM_TSEG_SIZE == 0x0 |
| 42 | #define BERT_REGION_MAX_SIZE 0x100000 |
| 43 | #else |
| 44 | /* SMM_TSEG_SIZE must stay on a boundary appropriate for its granularity */ |
| 45 | #define BERT_REGION_MAX_SIZE CONFIG_SMM_TSEG_SIZE |
| 46 | #endif |
Marshall Dawson | 4b0f6fa | 2018-09-04 13:08:25 -0600 | [diff] [blame] | 47 | #else |
Marshall Dawson | f0de242 | 2018-09-10 13:28:49 -0600 | [diff] [blame] | 48 | #define BERT_REGION_MAX_SIZE 0 |
Marshall Dawson | 4b0f6fa | 2018-09-04 13:08:25 -0600 | [diff] [blame] | 49 | #endif |
| 50 | |
| 51 | void bert_reserved_region(void **start, size_t *size) |
| 52 | { |
| 53 | if (IS_ENABLED(CONFIG_ACPI_BERT)) |
| 54 | *start = cbmem_top(); |
| 55 | else |
| 56 | start = NULL; |
| 57 | *size = BERT_REGION_MAX_SIZE; |
| 58 | } |
| 59 | |
Marshall Dawson | 94ee937 | 2017-06-15 12:18:23 -0600 | [diff] [blame] | 60 | void *cbmem_top(void) |
| 61 | { |
| 62 | msr_t tom = rdmsr(TOP_MEM); |
| 63 | |
| 64 | if (!tom.lo) |
| 65 | return 0; |
Richard Spiegel | 8c614f2 | 2018-10-23 14:53:23 -0700 | [diff] [blame^] | 66 | |
| 67 | /* 8MB alignment to keep MTRR usage low */ |
| 68 | return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() |
| 69 | - CONFIG_SMM_TSEG_SIZE |
| 70 | - BERT_REGION_MAX_SIZE, 8*MiB); |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 71 | } |
| 72 | |
| 73 | static uintptr_t smm_region_start(void) |
| 74 | { |
Marshall Dawson | 4b0f6fa | 2018-09-04 13:08:25 -0600 | [diff] [blame] | 75 | return (uintptr_t)cbmem_top() + BERT_REGION_MAX_SIZE; |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 76 | } |
| 77 | |
| 78 | static size_t smm_region_size(void) |
| 79 | { |
| 80 | return CONFIG_SMM_TSEG_SIZE; |
| 81 | } |
| 82 | |
Marshall Dawson | f3c57a7c | 2018-01-29 18:08:16 -0700 | [diff] [blame] | 83 | void stage_cache_external_region(void **base, size_t *size) |
| 84 | { |
| 85 | if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { |
| 86 | printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); |
| 87 | *base = NULL; |
| 88 | *size = 0; |
| 89 | } |
| 90 | } |
| 91 | |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 92 | void smm_region_info(void **start, size_t *size) |
| 93 | { |
| 94 | *start = (void *)smm_region_start(); |
| 95 | *size = smm_region_size(); |
| 96 | } |
| 97 | |
Marshall Dawson | f3c57a7c | 2018-01-29 18:08:16 -0700 | [diff] [blame] | 98 | /* |
| 99 | * For data stored in TSEG, ensure TValid is clear so R/W access can reach |
| 100 | * the DRAM when not in SMM. |
| 101 | */ |
| 102 | static void clear_tvalid(void) |
| 103 | { |
| 104 | msr_t hwcr = rdmsr(HWCR_MSR); |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 105 | msr_t mask = rdmsr(SMM_MASK_MSR); |
Marshall Dawson | f3c57a7c | 2018-01-29 18:08:16 -0700 | [diff] [blame] | 106 | int tvalid = !!(mask.lo & SMM_TSEG_VALID); |
| 107 | |
| 108 | if (hwcr.lo & SMM_LOCK) { |
| 109 | if (!tvalid) /* not valid but locked means still accessible */ |
| 110 | return; |
| 111 | |
| 112 | printk(BIOS_ERR, "Error: can't clear TValid, already locked\n"); |
| 113 | return; |
| 114 | } |
| 115 | |
| 116 | mask.lo &= ~SMM_TSEG_VALID; |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 117 | wrmsr(SMM_MASK_MSR, mask); |
Marshall Dawson | f3c57a7c | 2018-01-29 18:08:16 -0700 | [diff] [blame] | 118 | } |
| 119 | |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 120 | int smm_subregion(int sub, void **start, size_t *size) |
| 121 | { |
| 122 | uintptr_t sub_base; |
| 123 | size_t sub_size; |
| 124 | const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; |
| 125 | |
| 126 | sub_base = smm_region_start(); |
| 127 | sub_size = smm_region_size(); |
| 128 | |
| 129 | assert(sub_size > CONFIG_SMM_RESERVED_SIZE); |
| 130 | |
| 131 | switch (sub) { |
| 132 | case SMM_SUBREGION_HANDLER: |
| 133 | /* Handler starts at the base of TSEG. */ |
| 134 | sub_size -= cache_size; |
| 135 | break; |
| 136 | case SMM_SUBREGION_CACHE: |
| 137 | /* External cache is in the middle of TSEG. */ |
| 138 | sub_base += sub_size - cache_size; |
| 139 | sub_size = cache_size; |
Marshall Dawson | f3c57a7c | 2018-01-29 18:08:16 -0700 | [diff] [blame] | 140 | clear_tvalid(); |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 141 | break; |
| 142 | default: |
| 143 | return -1; |
| 144 | } |
| 145 | |
| 146 | *start = (void *)sub_base; |
| 147 | *size = sub_size; |
| 148 | |
| 149 | return 0; |
Marshall Dawson | 94ee937 | 2017-06-15 12:18:23 -0600 | [diff] [blame] | 150 | } |