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Marc Jones1587dc82017-05-15 18:55:11 -06001/*
2 * This file is part of the coreboot project.
3 *
Marshall Dawsonb6172112017-09-13 17:47:31 -06004 * Copyright (C) 2015 Intel Corp.
5 *
Marc Jones1587dc82017-05-15 18:55:11 -06006 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#define __SIMPLE_DEVICE__
17
Marshall Dawsonb6172112017-09-13 17:47:31 -060018#include <assert.h>
Marc Jones1587dc82017-05-15 18:55:11 -060019#include <stdint.h>
20#include <arch/io.h>
Marshall Dawson94ee9372017-06-15 12:18:23 -060021#include <cpu/x86/msr.h>
22#include <cpu/amd/mtrr.h>
Marc Jones1587dc82017-05-15 18:55:11 -060023#include <cbmem.h>
Marshall Dawsonb6172112017-09-13 17:47:31 -060024#include <soc/northbridge.h>
Marshall Dawson22f54c52017-11-29 09:30:23 -070025#include <soc/southbridge.h>
Marc Jones1587dc82017-05-15 18:55:11 -060026
27void backup_top_of_low_cacheable(uintptr_t ramtop)
28{
Marshall Dawson22f54c52017-11-29 09:30:23 -070029 biosram_write32(BIOSRAM_CBMEM_TOP, ramtop);
Marc Jones1587dc82017-05-15 18:55:11 -060030}
31
32uintptr_t restore_top_of_low_cacheable(void)
33{
Marshall Dawson22f54c52017-11-29 09:30:23 -070034 return biosram_read32(BIOSRAM_CBMEM_TOP);
Marc Jones1587dc82017-05-15 18:55:11 -060035}
Marshall Dawson94ee9372017-06-15 12:18:23 -060036
37void *cbmem_top(void)
38{
39 msr_t tom = rdmsr(TOP_MEM);
40
41 if (!tom.lo)
42 return 0;
43 else
Marshall Dawsonb6172112017-09-13 17:47:31 -060044 /* 8MB alignment to keep MTRR usage low */
Marshall Dawson0801b332017-08-25 15:29:45 -060045 return (void *)ALIGN_DOWN(restore_top_of_low_cacheable()
Marshall Dawsonb6172112017-09-13 17:47:31 -060046 - CONFIG_SMM_TSEG_SIZE, 8*MiB);
47}
48
49static uintptr_t smm_region_start(void)
50{
51 return (uintptr_t)cbmem_top();
52}
53
54static size_t smm_region_size(void)
55{
56 return CONFIG_SMM_TSEG_SIZE;
57}
58
59void smm_region_info(void **start, size_t *size)
60{
61 *start = (void *)smm_region_start();
62 *size = smm_region_size();
63}
64
65int smm_subregion(int sub, void **start, size_t *size)
66{
67 uintptr_t sub_base;
68 size_t sub_size;
69 const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;
70
71 sub_base = smm_region_start();
72 sub_size = smm_region_size();
73
74 assert(sub_size > CONFIG_SMM_RESERVED_SIZE);
75
76 switch (sub) {
77 case SMM_SUBREGION_HANDLER:
78 /* Handler starts at the base of TSEG. */
79 sub_size -= cache_size;
80 break;
81 case SMM_SUBREGION_CACHE:
82 /* External cache is in the middle of TSEG. */
83 sub_base += sub_size - cache_size;
84 sub_size = cache_size;
85 break;
86 default:
87 return -1;
88 }
89
90 *start = (void *)sub_base;
91 *size = sub_size;
92
93 return 0;
Marshall Dawson94ee9372017-06-15 12:18:23 -060094}