Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 4 | * Copyright (C) 2015 Intel Corp. |
| 5 | * |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #define __SIMPLE_DEVICE__ |
| 17 | |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 18 | #include <assert.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 19 | #include <stdint.h> |
| 20 | #include <arch/io.h> |
Marshall Dawson | 94ee937 | 2017-06-15 12:18:23 -0600 | [diff] [blame] | 21 | #include <cpu/x86/msr.h> |
| 22 | #include <cpu/amd/mtrr.h> |
Marshall Dawson | f3c57a7c | 2018-01-29 18:08:16 -0700 | [diff] [blame^] | 23 | #include <cpu/amd/amdfam15.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 24 | #include <cbmem.h> |
Marshall Dawson | f3c57a7c | 2018-01-29 18:08:16 -0700 | [diff] [blame^] | 25 | #include <stage_cache.h> |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 26 | #include <soc/northbridge.h> |
Marshall Dawson | 22f54c5 | 2017-11-29 09:30:23 -0700 | [diff] [blame] | 27 | #include <soc/southbridge.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 28 | |
| 29 | void backup_top_of_low_cacheable(uintptr_t ramtop) |
| 30 | { |
Marshall Dawson | 22f54c5 | 2017-11-29 09:30:23 -0700 | [diff] [blame] | 31 | biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 32 | } |
| 33 | |
| 34 | uintptr_t restore_top_of_low_cacheable(void) |
| 35 | { |
Marshall Dawson | 22f54c5 | 2017-11-29 09:30:23 -0700 | [diff] [blame] | 36 | return biosram_read32(BIOSRAM_CBMEM_TOP); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 37 | } |
Marshall Dawson | 94ee937 | 2017-06-15 12:18:23 -0600 | [diff] [blame] | 38 | |
| 39 | void *cbmem_top(void) |
| 40 | { |
| 41 | msr_t tom = rdmsr(TOP_MEM); |
| 42 | |
| 43 | if (!tom.lo) |
| 44 | return 0; |
| 45 | else |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 46 | /* 8MB alignment to keep MTRR usage low */ |
Marshall Dawson | 0801b33 | 2017-08-25 15:29:45 -0600 | [diff] [blame] | 47 | return (void *)ALIGN_DOWN(restore_top_of_low_cacheable() |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 48 | - CONFIG_SMM_TSEG_SIZE, 8*MiB); |
| 49 | } |
| 50 | |
| 51 | static uintptr_t smm_region_start(void) |
| 52 | { |
| 53 | return (uintptr_t)cbmem_top(); |
| 54 | } |
| 55 | |
| 56 | static size_t smm_region_size(void) |
| 57 | { |
| 58 | return CONFIG_SMM_TSEG_SIZE; |
| 59 | } |
| 60 | |
Marshall Dawson | f3c57a7c | 2018-01-29 18:08:16 -0700 | [diff] [blame^] | 61 | void stage_cache_external_region(void **base, size_t *size) |
| 62 | { |
| 63 | if (smm_subregion(SMM_SUBREGION_CACHE, base, size)) { |
| 64 | printk(BIOS_ERR, "ERROR: No cache SMM subregion.\n"); |
| 65 | *base = NULL; |
| 66 | *size = 0; |
| 67 | } |
| 68 | } |
| 69 | |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 70 | void smm_region_info(void **start, size_t *size) |
| 71 | { |
| 72 | *start = (void *)smm_region_start(); |
| 73 | *size = smm_region_size(); |
| 74 | } |
| 75 | |
Marshall Dawson | f3c57a7c | 2018-01-29 18:08:16 -0700 | [diff] [blame^] | 76 | /* |
| 77 | * For data stored in TSEG, ensure TValid is clear so R/W access can reach |
| 78 | * the DRAM when not in SMM. |
| 79 | */ |
| 80 | static void clear_tvalid(void) |
| 81 | { |
| 82 | msr_t hwcr = rdmsr(HWCR_MSR); |
| 83 | msr_t mask = rdmsr(MSR_SMM_MASK); |
| 84 | int tvalid = !!(mask.lo & SMM_TSEG_VALID); |
| 85 | |
| 86 | if (hwcr.lo & SMM_LOCK) { |
| 87 | if (!tvalid) /* not valid but locked means still accessible */ |
| 88 | return; |
| 89 | |
| 90 | printk(BIOS_ERR, "Error: can't clear TValid, already locked\n"); |
| 91 | return; |
| 92 | } |
| 93 | |
| 94 | mask.lo &= ~SMM_TSEG_VALID; |
| 95 | wrmsr(MSR_SMM_MASK, mask); |
| 96 | } |
| 97 | |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 98 | int smm_subregion(int sub, void **start, size_t *size) |
| 99 | { |
| 100 | uintptr_t sub_base; |
| 101 | size_t sub_size; |
| 102 | const size_t cache_size = CONFIG_SMM_RESERVED_SIZE; |
| 103 | |
| 104 | sub_base = smm_region_start(); |
| 105 | sub_size = smm_region_size(); |
| 106 | |
| 107 | assert(sub_size > CONFIG_SMM_RESERVED_SIZE); |
| 108 | |
| 109 | switch (sub) { |
| 110 | case SMM_SUBREGION_HANDLER: |
| 111 | /* Handler starts at the base of TSEG. */ |
| 112 | sub_size -= cache_size; |
| 113 | break; |
| 114 | case SMM_SUBREGION_CACHE: |
| 115 | /* External cache is in the middle of TSEG. */ |
| 116 | sub_base += sub_size - cache_size; |
| 117 | sub_size = cache_size; |
Marshall Dawson | f3c57a7c | 2018-01-29 18:08:16 -0700 | [diff] [blame^] | 118 | clear_tvalid(); |
Marshall Dawson | b617211 | 2017-09-13 17:47:31 -0600 | [diff] [blame] | 119 | break; |
| 120 | default: |
| 121 | return -1; |
| 122 | } |
| 123 | |
| 124 | *start = (void *)sub_base; |
| 125 | *size = sub_size; |
| 126 | |
| 127 | return 0; |
Marshall Dawson | 94ee937 | 2017-06-15 12:18:23 -0600 | [diff] [blame] | 128 | } |