Angel Pons | 89ab250 | 2020-04-03 01:22:28 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 3 | |
| 4 | #include <stdint.h> |
| 5 | #include <string.h> |
| 6 | #include <cbfs.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 7 | #include <device/pci_ops.h> |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 8 | #include <console/console.h> |
Elyes HAOUAS | 4ad1446 | 2018-06-16 18:29:33 +0200 | [diff] [blame] | 9 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 10 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 11 | #include <southbridge/intel/bd82x6x/pch.h> |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 12 | #include <southbridge/intel/common/gpio.h> |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 13 | #include "ec.h" |
| 14 | |
| 15 | #define SPD_LEN 256 |
| 16 | |
Arthur Heymans | 2b28a16 | 2019-11-12 17:21:08 +0100 | [diff] [blame] | 17 | void mainboard_pch_lpc_setup(void) |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 18 | { |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 19 | /* Memory map KB9012 EC registers */ |
| 20 | pci_write_config32( |
Peter Lemenkov | 9b7ae2f | 2018-10-09 13:09:07 +0200 | [diff] [blame] | 21 | PCH_LPC_DEV, LGMR, |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 22 | CONFIG_EC_BASE_ADDRESS | 1); |
Peter Lemenkov | 9b7ae2f | 2018-10-09 13:09:07 +0200 | [diff] [blame] | 23 | pci_write_config16(PCH_LPC_DEV, BIOS_DEC_EN1, 0xffc0); |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 24 | |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 25 | /* Enable external USB port power. */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 26 | if (CONFIG(USBDEBUG)) |
Martin Roth | 5ef5c00 | 2017-03-24 11:08:32 -0600 | [diff] [blame] | 27 | ec_mm_set_bit(0x3b, 4); |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 28 | } |
| 29 | |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 30 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 31 | { 1, 1, 0 }, |
| 32 | { 1, 0, 0 }, |
| 33 | { 1, 1, 1 }, |
| 34 | { 1, 0, 1 }, |
| 35 | { 1, 1, 2 }, |
| 36 | { 1, 0, 2 }, |
| 37 | { 0, 0, 3 }, |
| 38 | { 0, 1, 3 }, |
| 39 | { 1, 0, 4 }, |
| 40 | { 1, 1, 4 }, |
| 41 | { 1, 1, 5 }, |
| 42 | { 1, 1, 5 }, |
| 43 | { 1, 1, 6 }, |
| 44 | { 1, 1, 6 }, |
| 45 | }; |
| 46 | |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 47 | static const char *mainboard_spd_names[9] = { |
| 48 | "ELPIDA 4GB", |
| 49 | "SAMSUNG 4GB", |
| 50 | "HYNIX 4GB", |
| 51 | "ELPIDA 8GB", |
| 52 | "SAMSUNG 8GB", |
| 53 | "HYNIX 8GB", |
| 54 | "ELPIDA 2GB", |
| 55 | "SAMSUNG 2GB", |
| 56 | "HYNIX 2GB", |
| 57 | }; |
| 58 | |
| 59 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 60 | { |
| 61 | void *spd_file; |
| 62 | size_t spd_file_len = 0; |
| 63 | const int spd_gpios[] = {71, 70, 16, 48, -1}; |
| 64 | |
| 65 | u32 spd_index = get_gpios(spd_gpios); |
| 66 | if (spd_index >= ARRAY_SIZE(mainboard_spd_names)) { |
| 67 | /* Fallback to pessimistic 2GB image (ELPIDA 2GB) */ |
| 68 | spd_index = 6; |
| 69 | } |
| 70 | |
| 71 | printk(BIOS_INFO, "SPD index %d (%s)\n", |
| 72 | spd_index, mainboard_spd_names[spd_index]); |
| 73 | |
Peter Lemenkov | 6b7d40a | 2020-01-22 11:40:16 +0100 | [diff] [blame] | 74 | /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 75 | spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, |
| 76 | &spd_file_len); |
| 77 | |
| 78 | if (!spd_file || spd_file_len < SPD_LEN * spd_index + SPD_LEN) |
| 79 | die("SPD data not found."); |
| 80 | |
| 81 | memcpy(spd, spd_file + SPD_LEN * spd_index, SPD_LEN); |
| 82 | } |