Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <stdint.h> |
| 17 | #include <string.h> |
| 18 | #include <cbfs.h> |
| 19 | #include <lib.h> |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 20 | #include <arch/byteorder.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <device/pci_def.h> |
| 23 | #include <device/pnp_def.h> |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 24 | #include <console/console.h> |
Elyes HAOUAS | 4ad1446 | 2018-06-16 18:29:33 +0200 | [diff] [blame] | 25 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 26 | #include <northbridge/intel/sandybridge/raminit_native.h> |
| 27 | #include <southbridge/intel/bd82x6x/pch.h> |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 28 | #include <southbridge/intel/common/gpio.h> |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 29 | #include "ec.h" |
| 30 | |
| 31 | #define SPD_LEN 256 |
| 32 | |
| 33 | void pch_enable_lpc(void) |
| 34 | { |
Peter Lemenkov | 9b7ae2f | 2018-10-09 13:09:07 +0200 | [diff] [blame^] | 35 | pci_write_config16(PCH_LPC_DEV, LPC_EN, MC_LPC_EN | KBC_LPC_EN); |
| 36 | pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc0701); |
| 37 | pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0xc0069); |
| 38 | pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0xc06a1); |
| 39 | pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 40 | |
| 41 | /* Memory map KB9012 EC registers */ |
| 42 | pci_write_config32( |
Peter Lemenkov | 9b7ae2f | 2018-10-09 13:09:07 +0200 | [diff] [blame^] | 43 | PCH_LPC_DEV, LGMR, |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 44 | CONFIG_EC_BASE_ADDRESS | 1); |
Peter Lemenkov | 9b7ae2f | 2018-10-09 13:09:07 +0200 | [diff] [blame^] | 45 | pci_write_config16(PCH_LPC_DEV, BIOS_DEC_EN1, 0xffc0); |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 46 | |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 47 | /* Enable external USB port power. */ |
Martin Roth | 5ef5c00 | 2017-03-24 11:08:32 -0600 | [diff] [blame] | 48 | if (IS_ENABLED(CONFIG_USBDEBUG)) |
| 49 | ec_mm_set_bit(0x3b, 4); |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 50 | } |
| 51 | |
Nico Huber | ff4025c | 2018-01-14 12:34:43 +0100 | [diff] [blame] | 52 | void mainboard_rcba_config(void) |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 53 | { |
| 54 | /* Disable devices. */ |
Peter Lemenkov | 9b7ae2f | 2018-10-09 13:09:07 +0200 | [diff] [blame^] | 55 | RCBA32(BUC) = 0x00000020; |
Tobias Diedrich | cee930a | 2017-02-12 14:09:06 +0100 | [diff] [blame] | 56 | } |
| 57 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 58 | { 1, 1, 0 }, |
| 59 | { 1, 0, 0 }, |
| 60 | { 1, 1, 1 }, |
| 61 | { 1, 0, 1 }, |
| 62 | { 1, 1, 2 }, |
| 63 | { 1, 0, 2 }, |
| 64 | { 0, 0, 3 }, |
| 65 | { 0, 1, 3 }, |
| 66 | { 1, 0, 4 }, |
| 67 | { 1, 1, 4 }, |
| 68 | { 1, 1, 5 }, |
| 69 | { 1, 1, 5 }, |
| 70 | { 1, 1, 6 }, |
| 71 | { 1, 1, 6 }, |
| 72 | }; |
| 73 | |
| 74 | void mainboard_early_init(int s3resume) |
| 75 | { |
| 76 | } |
| 77 | |
| 78 | void mainboard_config_superio(void) |
| 79 | { |
| 80 | } |
| 81 | |
| 82 | static const char *mainboard_spd_names[9] = { |
| 83 | "ELPIDA 4GB", |
| 84 | "SAMSUNG 4GB", |
| 85 | "HYNIX 4GB", |
| 86 | "ELPIDA 8GB", |
| 87 | "SAMSUNG 8GB", |
| 88 | "HYNIX 8GB", |
| 89 | "ELPIDA 2GB", |
| 90 | "SAMSUNG 2GB", |
| 91 | "HYNIX 2GB", |
| 92 | }; |
| 93 | |
| 94 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 95 | { |
| 96 | void *spd_file; |
| 97 | size_t spd_file_len = 0; |
| 98 | const int spd_gpios[] = {71, 70, 16, 48, -1}; |
| 99 | |
| 100 | u32 spd_index = get_gpios(spd_gpios); |
| 101 | if (spd_index >= ARRAY_SIZE(mainboard_spd_names)) { |
| 102 | /* Fallback to pessimistic 2GB image (ELPIDA 2GB) */ |
| 103 | spd_index = 6; |
| 104 | } |
| 105 | |
| 106 | printk(BIOS_INFO, "SPD index %d (%s)\n", |
| 107 | spd_index, mainboard_spd_names[spd_index]); |
| 108 | |
| 109 | /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ |
| 110 | spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, |
| 111 | &spd_file_len); |
| 112 | |
| 113 | if (!spd_file || spd_file_len < SPD_LEN * spd_index + SPD_LEN) |
| 114 | die("SPD data not found."); |
| 115 | |
| 116 | memcpy(spd, spd_file + SPD_LEN * spd_index, SPD_LEN); |
| 117 | } |