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Tobias Diedrichcee930a2017-02-12 14:09:06 +01001/*
2 * This file is part of the coreboot project.
3 *
Tobias Diedrichcee930a2017-02-12 14:09:06 +01004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <stdint.h>
16#include <string.h>
17#include <cbfs.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +020018#include <device/pci_ops.h>
Tobias Diedrichcee930a2017-02-12 14:09:06 +010019#include <console/console.h>
Elyes HAOUAS4ad14462018-06-16 18:29:33 +020020#include <northbridge/intel/sandybridge/sandybridge.h>
21#include <northbridge/intel/sandybridge/raminit_native.h>
22#include <southbridge/intel/bd82x6x/pch.h>
Tobias Diedrichcee930a2017-02-12 14:09:06 +010023#include <southbridge/intel/common/gpio.h>
Tobias Diedrichcee930a2017-02-12 14:09:06 +010024#include "ec.h"
25
26#define SPD_LEN 256
27
Arthur Heymans2b28a162019-11-12 17:21:08 +010028void mainboard_pch_lpc_setup(void)
Tobias Diedrichcee930a2017-02-12 14:09:06 +010029{
Tobias Diedrichcee930a2017-02-12 14:09:06 +010030 /* Memory map KB9012 EC registers */
31 pci_write_config32(
Peter Lemenkov9b7ae2f2018-10-09 13:09:07 +020032 PCH_LPC_DEV, LGMR,
Tobias Diedrichcee930a2017-02-12 14:09:06 +010033 CONFIG_EC_BASE_ADDRESS | 1);
Peter Lemenkov9b7ae2f2018-10-09 13:09:07 +020034 pci_write_config16(PCH_LPC_DEV, BIOS_DEC_EN1, 0xffc0);
Tobias Diedrichcee930a2017-02-12 14:09:06 +010035
Tobias Diedrichcee930a2017-02-12 14:09:06 +010036 /* Enable external USB port power. */
Julius Wernercd49cce2019-03-05 16:53:33 -080037 if (CONFIG(USBDEBUG))
Martin Roth5ef5c002017-03-24 11:08:32 -060038 ec_mm_set_bit(0x3b, 4);
Tobias Diedrichcee930a2017-02-12 14:09:06 +010039}
40
Tobias Diedrichcee930a2017-02-12 14:09:06 +010041const struct southbridge_usb_port mainboard_usb_ports[] = {
42 { 1, 1, 0 },
43 { 1, 0, 0 },
44 { 1, 1, 1 },
45 { 1, 0, 1 },
46 { 1, 1, 2 },
47 { 1, 0, 2 },
48 { 0, 0, 3 },
49 { 0, 1, 3 },
50 { 1, 0, 4 },
51 { 1, 1, 4 },
52 { 1, 1, 5 },
53 { 1, 1, 5 },
54 { 1, 1, 6 },
55 { 1, 1, 6 },
56};
57
Tobias Diedrichcee930a2017-02-12 14:09:06 +010058static const char *mainboard_spd_names[9] = {
59 "ELPIDA 4GB",
60 "SAMSUNG 4GB",
61 "HYNIX 4GB",
62 "ELPIDA 8GB",
63 "SAMSUNG 8GB",
64 "HYNIX 8GB",
65 "ELPIDA 2GB",
66 "SAMSUNG 2GB",
67 "HYNIX 2GB",
68};
69
70void mainboard_get_spd(spd_raw_data *spd, bool id_only)
71{
72 void *spd_file;
73 size_t spd_file_len = 0;
74 const int spd_gpios[] = {71, 70, 16, 48, -1};
75
76 u32 spd_index = get_gpios(spd_gpios);
77 if (spd_index >= ARRAY_SIZE(mainboard_spd_names)) {
78 /* Fallback to pessimistic 2GB image (ELPIDA 2GB) */
79 spd_index = 6;
80 }
81
82 printk(BIOS_INFO, "SPD index %d (%s)\n",
83 spd_index, mainboard_spd_names[spd_index]);
84
Peter Lemenkov6b7d40a2020-01-22 11:40:16 +010085 /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */
Tobias Diedrichcee930a2017-02-12 14:09:06 +010086 spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
87 &spd_file_len);
88
89 if (!spd_file || spd_file_len < SPD_LEN * spd_index + SPD_LEN)
90 die("SPD data not found.");
91
92 memcpy(spd, spd_file + SPD_LEN * spd_index, SPD_LEN);
93}