Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
| 3 | #include <types.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 4 | #include <arch/io.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 6 | #include <console/console.h> |
| 7 | #include <cpu/x86/cache.h> |
| 8 | #include <device/pci_def.h> |
| 9 | #include <cpu/x86/smm.h> |
Kyösti Mälkki | e31ec29 | 2019-08-10 17:27:01 +0300 | [diff] [blame] | 10 | #include <cpu/intel/em64t101_save_state.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 11 | #include <elog.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 12 | #include <halt.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame] | 13 | #include <option.h> |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 14 | #include <southbridge/intel/common/finalize.h> |
Tristan Corrick | 09fc634 | 2018-11-30 22:53:01 +1300 | [diff] [blame] | 15 | #include <northbridge/intel/haswell/haswell.h> |
| 16 | #include <cpu/intel/haswell/haswell.h> |
Kyösti Mälkki | 661ad46 | 2020-12-29 06:26:21 +0200 | [diff] [blame] | 17 | #include <soc/nvs.h> |
Matt DeVillier | 8187f11 | 2018-12-24 21:46:46 -0600 | [diff] [blame] | 18 | #include <smmstore.h> |
Tristan Corrick | 63626b1 | 2018-11-30 22:53:50 +1300 | [diff] [blame] | 19 | #include "me.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 20 | #include "pch.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 21 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 22 | int southbridge_io_trap_handler(int smif) |
| 23 | { |
| 24 | switch (smif) { |
| 25 | case 0x32: |
| 26 | printk(BIOS_DEBUG, "OS Init\n"); |
| 27 | /* gnvs->smif: |
| 28 | * On success, the IO Trap Handler returns 0 |
| 29 | * On failure, the IO Trap Handler returns a value != 0 |
| 30 | */ |
| 31 | gnvs->smif = 0; |
| 32 | return 1; /* IO trap handled */ |
| 33 | } |
| 34 | |
| 35 | /* Not handled */ |
| 36 | return 0; |
| 37 | } |
| 38 | |
| 39 | /** |
| 40 | * @brief Set the EOS bit |
| 41 | */ |
| 42 | void southbridge_smi_set_eos(void) |
| 43 | { |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 44 | enable_smi(EOS); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 45 | } |
| 46 | |
| 47 | static void busmaster_disable_on_bus(int bus) |
| 48 | { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 49 | int slot, func; |
| 50 | unsigned int val; |
| 51 | unsigned char hdr; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 52 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 53 | for (slot = 0; slot < 0x20; slot++) { |
| 54 | for (func = 0; func < 8; func++) { |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 55 | pci_devfn_t dev = PCI_DEV(bus, slot, func); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 56 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 57 | val = pci_read_config32(dev, PCI_VENDOR_ID); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 58 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 59 | if (val == 0xffffffff || val == 0x00000000 || |
| 60 | val == 0x0000ffff || val == 0xffff0000) |
| 61 | continue; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 62 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 63 | /* Disable Bus Mastering for this one device */ |
Angel Pons | bf9bc50 | 2020-06-08 00:12:43 +0200 | [diff] [blame] | 64 | pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MASTER); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 65 | |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 66 | /* If this is a bridge, then follow it. */ |
| 67 | hdr = pci_read_config8(dev, PCI_HEADER_TYPE); |
| 68 | hdr &= 0x7f; |
| 69 | if (hdr == PCI_HEADER_TYPE_BRIDGE || |
| 70 | hdr == PCI_HEADER_TYPE_CARDBUS) { |
| 71 | unsigned int buses; |
| 72 | buses = pci_read_config32(dev, PCI_PRIMARY_BUS); |
| 73 | busmaster_disable_on_bus((buses >> 8) & 0xff); |
| 74 | } |
| 75 | } |
| 76 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 77 | } |
| 78 | |
Kyösti Mälkki | 3c18186 | 2021-01-08 19:01:30 +0200 | [diff] [blame] | 79 | static int power_on_after_fail(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 80 | { |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 81 | /* save and recover RTC port values */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 82 | u8 tmp70, tmp72; |
| 83 | tmp70 = inb(0x70); |
| 84 | tmp72 = inb(0x72); |
Angel Pons | 88dcb31 | 2021-04-26 17:10:28 +0200 | [diff] [blame^] | 85 | const unsigned int s5pwr = get_uint_option("power_on_after_fail", |
Angel Pons | 62719a3 | 2021-04-19 13:15:28 +0200 | [diff] [blame] | 86 | CONFIG_MAINBOARD_POWER_FAILURE_STATE); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 87 | outb(tmp70, 0x70); |
| 88 | outb(tmp72, 0x72); |
| 89 | |
Kyösti Mälkki | 3c18186 | 2021-01-08 19:01:30 +0200 | [diff] [blame] | 90 | /* For "KEEP", switch to "OFF" - KEEP is software emulated. */ |
| 91 | return (s5pwr == MAINBOARD_POWER_ON); |
| 92 | } |
| 93 | |
| 94 | static void southbridge_smi_sleep(void) |
| 95 | { |
| 96 | u32 reg32; |
| 97 | u8 slp_typ; |
| 98 | u16 pmbase = get_pmbase(); |
| 99 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 100 | /* First, disable further SMIs */ |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 101 | disable_smi(SLP_SMI_EN); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 102 | |
| 103 | /* Figure out SLP_TYP */ |
| 104 | reg32 = inl(pmbase + PM1_CNT); |
| 105 | printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32); |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 106 | slp_typ = acpi_sleep_from_pm1(reg32); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 107 | |
| 108 | /* Do any mainboard sleep handling */ |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 109 | mainboard_smi_sleep(slp_typ); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 110 | |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 111 | /* USB sleep preparations */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 112 | #if !CONFIG(FINALIZE_USB_ROUTE_XHCI) |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 113 | usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ); |
| 114 | usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ); |
Duncan Laurie | 911cedf | 2013-07-30 16:05:55 -0700 | [diff] [blame] | 115 | #endif |
Duncan Laurie | 1f52908 | 2013-07-30 15:53:45 -0700 | [diff] [blame] | 116 | usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ); |
Duncan Laurie | 2d9d39a | 2013-05-29 15:27:55 -0700 | [diff] [blame] | 117 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 118 | /* Log S3, S4, and S5 entry */ |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 119 | if (slp_typ >= ACPI_S3) |
Kyösti Mälkki | 9dd1a12 | 2019-11-06 11:04:27 +0200 | [diff] [blame] | 120 | elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 121 | |
| 122 | /* Next, do the deed. |
| 123 | */ |
| 124 | |
| 125 | switch (slp_typ) { |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 126 | case ACPI_S0: |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 127 | printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); |
| 128 | break; |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 129 | case ACPI_S1: |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 130 | printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); |
| 131 | break; |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 132 | case ACPI_S3: |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 133 | printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n"); |
| 134 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 135 | /* Invalidate the cache before going to S3 */ |
| 136 | wbinvd(); |
| 137 | break; |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 138 | case ACPI_S4: |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 139 | printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); |
| 140 | break; |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 141 | case ACPI_S5: |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 142 | printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n"); |
| 143 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 144 | /* Disable all GPE */ |
| 145 | disable_all_gpe(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 146 | |
Kyösti Mälkki | 3c18186 | 2021-01-08 19:01:30 +0200 | [diff] [blame] | 147 | /* Always set the flag in case CMOS was changed on runtime. */ |
| 148 | if (power_on_after_fail()) |
| 149 | pci_and_config8(PCH_LPC_DEV, GEN_PMCON_3, ~1); |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 150 | else |
Kyösti Mälkki | 3c18186 | 2021-01-08 19:01:30 +0200 | [diff] [blame] | 151 | pci_or_config8(PCH_LPC_DEV, GEN_PMCON_3, 1); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 152 | |
| 153 | /* also iterates over all bridges on bus 0 */ |
| 154 | busmaster_disable_on_bus(0); |
| 155 | break; |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 156 | default: |
| 157 | printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); |
| 158 | break; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 159 | } |
| 160 | |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 161 | /* |
| 162 | * Write back to the SLP register to cause the originally intended |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 163 | * event again. We need to set BIT13 (SLP_EN) though to make the |
| 164 | * sleep happen. |
| 165 | */ |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 166 | enable_pm1_control(SLP_EN); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 167 | |
| 168 | /* Make sure to stop executing code here for S3/S4/S5 */ |
Aaron Durbin | da5f509 | 2016-07-13 23:23:16 -0500 | [diff] [blame] | 169 | if (slp_typ >= ACPI_S3) |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 170 | halt(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 171 | |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 172 | /* |
| 173 | * In most sleep states, the code flow of this function ends at |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 174 | * the line above. However, if we entered sleep state S1 and wake |
| 175 | * up again, we will continue to execute code in this function. |
| 176 | */ |
| 177 | reg32 = inl(pmbase + PM1_CNT); |
| 178 | if (reg32 & SCI_EN) { |
| 179 | /* The OS is not an ACPI OS, so we set the state to S0 */ |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 180 | disable_pm1_control(SLP_EN | SLP_TYP); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 181 | } |
| 182 | } |
| 183 | |
| 184 | /* |
| 185 | * Look for Synchronous IO SMI and use save state from that |
| 186 | * core in case we are not running on the same core that |
| 187 | * initiated the IO transaction. |
| 188 | */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 189 | static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) |
| 190 | { |
| 191 | em64t101_smm_state_save_area_t *state; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 192 | int node; |
| 193 | |
| 194 | /* Check all nodes looking for the one that issued the IO */ |
| 195 | for (node = 0; node < CONFIG_MAX_CPUS; node++) { |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 196 | state = smm_get_save_state(node); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 197 | |
Elyes HAOUAS | 581fe58 | 2018-04-26 09:57:07 +0200 | [diff] [blame] | 198 | /* Check for Synchronous IO (bit0 == 1) */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 199 | if (!(state->io_misc_info & (1 << 0))) |
| 200 | continue; |
| 201 | |
Elyes HAOUAS | 581fe58 | 2018-04-26 09:57:07 +0200 | [diff] [blame] | 202 | /* Make sure it was a write (bit4 == 0) */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 203 | if (state->io_misc_info & (1 << 4)) |
| 204 | continue; |
| 205 | |
| 206 | /* Check for APMC IO port */ |
| 207 | if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) |
| 208 | continue; |
| 209 | |
| 210 | /* Check AX against the requested command */ |
| 211 | if ((state->rax & 0xff) != cmd) |
| 212 | continue; |
| 213 | |
| 214 | return state; |
| 215 | } |
| 216 | |
| 217 | return NULL; |
| 218 | } |
| 219 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 220 | static void southbridge_smi_gsmi(void) |
| 221 | { |
| 222 | u32 *ret, *param; |
| 223 | u8 sub_command; |
| 224 | em64t101_smm_state_save_area_t *io_smi = |
Patrick Georgi | d61839c | 2018-12-03 16:10:33 +0100 | [diff] [blame] | 225 | smi_apmc_find_state_save(APM_CNT_ELOG_GSMI); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 226 | |
| 227 | if (!io_smi) |
| 228 | return; |
| 229 | |
| 230 | /* Command and return value in EAX */ |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 231 | ret = (u32 *)&io_smi->rax; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 232 | sub_command = (u8)(*ret >> 8); |
| 233 | |
| 234 | /* Parameter buffer in EBX */ |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 235 | param = (u32 *)&io_smi->rbx; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 236 | |
| 237 | /* drivers/elog/gsmi.c */ |
| 238 | *ret = gsmi_exec(sub_command, param); |
| 239 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 240 | |
Matt DeVillier | 8187f11 | 2018-12-24 21:46:46 -0600 | [diff] [blame] | 241 | static void southbridge_smi_store(void) |
| 242 | { |
| 243 | u8 sub_command, ret; |
| 244 | em64t101_smm_state_save_area_t *io_smi = |
| 245 | smi_apmc_find_state_save(APM_CNT_SMMSTORE); |
| 246 | uint32_t reg_ebx; |
| 247 | |
| 248 | if (!io_smi) |
| 249 | return; |
| 250 | /* Command and return value in EAX */ |
| 251 | sub_command = (io_smi->rax >> 8) & 0xff; |
| 252 | |
| 253 | /* Parameter buffer in EBX */ |
| 254 | reg_ebx = io_smi->rbx; |
| 255 | |
| 256 | /* drivers/smmstore/smi.c */ |
| 257 | ret = smmstore_exec(sub_command, (void *)reg_ebx); |
| 258 | io_smi->rax = ret; |
| 259 | } |
| 260 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 261 | static void southbridge_smi_apmc(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 262 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 263 | u8 reg8; |
Tristan Corrick | 09fc634 | 2018-11-30 22:53:01 +1300 | [diff] [blame] | 264 | static int chipset_finalized = 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 265 | |
Kyösti Mälkki | 9a1620f | 2021-01-08 13:27:33 +0200 | [diff] [blame] | 266 | reg8 = apm_get_apmc(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 267 | switch (reg8) { |
Tristan Corrick | 09fc634 | 2018-11-30 22:53:01 +1300 | [diff] [blame] | 268 | case APM_CNT_FINALIZE: |
| 269 | if (chipset_finalized) { |
| 270 | printk(BIOS_DEBUG, "SMI#: Already finalized\n"); |
| 271 | return; |
| 272 | } |
| 273 | |
| 274 | intel_pch_finalize_smm(); |
Tristan Corrick | 09fc634 | 2018-11-30 22:53:01 +1300 | [diff] [blame] | 275 | intel_cpu_haswell_finalize_smm(); |
| 276 | |
| 277 | chipset_finalized = 1; |
| 278 | break; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 279 | case APM_CNT_ACPI_DISABLE: |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 280 | disable_pm1_control(SCI_EN); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 281 | break; |
| 282 | case APM_CNT_ACPI_ENABLE: |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 283 | enable_pm1_control(SCI_EN); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 284 | break; |
Kyösti Mälkki | b486f29 | 2020-06-18 14:05:35 +0300 | [diff] [blame] | 285 | case APM_CNT_ROUTE_ALL_XHCI: |
Duncan Laurie | 911cedf | 2013-07-30 16:05:55 -0700 | [diff] [blame] | 286 | usb_xhci_route_all(); |
Duncan Laurie | 911cedf | 2013-07-30 16:05:55 -0700 | [diff] [blame] | 287 | break; |
Patrick Georgi | d61839c | 2018-12-03 16:10:33 +0100 | [diff] [blame] | 288 | case APM_CNT_ELOG_GSMI: |
Kyösti Mälkki | 9dd1a12 | 2019-11-06 11:04:27 +0200 | [diff] [blame] | 289 | if (CONFIG(ELOG_GSMI)) |
| 290 | southbridge_smi_gsmi(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 291 | break; |
Matt DeVillier | 8187f11 | 2018-12-24 21:46:46 -0600 | [diff] [blame] | 292 | case APM_CNT_SMMSTORE: |
| 293 | if (CONFIG(SMMSTORE)) |
| 294 | southbridge_smi_store(); |
| 295 | break; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 296 | } |
| 297 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 298 | mainboard_smi_apmc(reg8); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 299 | } |
| 300 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 301 | static void southbridge_smi_pm1(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 302 | { |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 303 | u16 pm1_sts = clear_pm1_status(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 304 | |
| 305 | /* While OSPM is not active, poweroff immediately |
| 306 | * on a power button event. |
| 307 | */ |
| 308 | if (pm1_sts & PWRBTN_STS) { |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 309 | /* power button pressed */ |
Kyösti Mälkki | 9dd1a12 | 2019-11-06 11:04:27 +0200 | [diff] [blame] | 310 | elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON); |
Angel Pons | 8963f7d | 2020-10-24 12:20:28 +0200 | [diff] [blame] | 311 | disable_pm1_control(-1); |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 312 | enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10)); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 313 | } |
| 314 | } |
| 315 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 316 | static void southbridge_smi_gpe0(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 317 | { |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 318 | clear_gpe_status(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 319 | } |
| 320 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 321 | static void southbridge_smi_gpi(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 322 | { |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 323 | mainboard_smi_gpi(clear_alt_smi_status()); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 324 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 325 | /* Clear again after mainboard handler */ |
| 326 | clear_alt_smi_status(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 327 | } |
| 328 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 329 | static void southbridge_smi_mc(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 330 | { |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 331 | u32 reg32 = inl(get_pmbase() + SMI_EN); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 332 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 333 | /* Are microcontroller SMIs enabled? */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 334 | if ((reg32 & MCSMI_EN) == 0) |
| 335 | return; |
| 336 | |
| 337 | printk(BIOS_DEBUG, "Microcontroller SMI.\n"); |
| 338 | } |
| 339 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 340 | static void southbridge_smi_tco(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 341 | { |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 342 | u32 tco_sts = clear_tco_status(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 343 | |
| 344 | /* Any TCO event? */ |
| 345 | if (!tco_sts) |
| 346 | return; |
| 347 | |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 348 | // BIOSWR |
| 349 | if (tco_sts & (1 << 8)) { |
Angel Pons | cc36c4c | 2021-03-30 10:49:24 +0200 | [diff] [blame] | 350 | u8 bios_cntl = pci_read_config8(PCH_LPC_DEV, BIOS_CNTL); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 351 | |
| 352 | if (bios_cntl & 1) { |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 353 | /* |
| 354 | * BWE is RW, so the SMI was caused by a |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 355 | * write to BWE, not by a write to the BIOS |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 356 | * |
| 357 | * This is the place where we notice someone |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 358 | * is trying to tinker with the BIOS. We are |
| 359 | * trying to be nice and just ignore it. A more |
| 360 | * resolute answer would be to power down the |
| 361 | * box. |
| 362 | */ |
| 363 | printk(BIOS_DEBUG, "Switching back to RO\n"); |
Angel Pons | cc36c4c | 2021-03-30 10:49:24 +0200 | [diff] [blame] | 364 | pci_write_config8(PCH_LPC_DEV, BIOS_CNTL, (bios_cntl & ~1)); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 365 | } /* No else for now? */ |
| 366 | } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ |
| 367 | /* Handle TCO timeout */ |
| 368 | printk(BIOS_DEBUG, "TCO Timeout.\n"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 369 | } |
| 370 | } |
| 371 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 372 | static void southbridge_smi_periodic(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 373 | { |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 374 | u32 reg32 = inl(get_pmbase() + SMI_EN); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 375 | |
| 376 | /* Are periodic SMIs enabled? */ |
| 377 | if ((reg32 & PERIODIC_EN) == 0) |
| 378 | return; |
| 379 | |
| 380 | printk(BIOS_DEBUG, "Periodic SMI.\n"); |
| 381 | } |
| 382 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 383 | static void southbridge_smi_monitor(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 384 | { |
| 385 | #define IOTRAP(x) (trap_sts & (1 << x)) |
| 386 | u32 trap_sts, trap_cycle; |
Elyes HAOUAS | 2a66dd2 | 2020-08-07 15:22:12 +0200 | [diff] [blame] | 387 | u32 mask = 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 388 | int i; |
| 389 | |
| 390 | trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register |
| 391 | RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR |
| 392 | |
| 393 | trap_cycle = RCBA32(0x1e10); |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 394 | for (i = 16; i < 20; i++) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 395 | if (trap_cycle & (1 << i)) |
| 396 | mask |= (0xff << ((i - 16) << 2)); |
| 397 | } |
| 398 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 399 | /* IOTRAP(3) SMI function call */ |
| 400 | if (IOTRAP(3)) { |
| 401 | if (gnvs && gnvs->smif) |
| 402 | io_trap_handler(gnvs->smif); // call function smif |
| 403 | return; |
| 404 | } |
| 405 | |
| 406 | /* IOTRAP(2) currently unused |
| 407 | * IOTRAP(1) currently unused */ |
| 408 | |
| 409 | /* IOTRAP(0) SMIC */ |
| 410 | if (IOTRAP(0)) { |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 411 | // It's a write |
| 412 | if (!(trap_cycle & (1 << 24))) { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 413 | printk(BIOS_DEBUG, "SMI1 command\n"); |
Elyes HAOUAS | 2a66dd2 | 2020-08-07 15:22:12 +0200 | [diff] [blame] | 414 | (void)RCBA32(0x1e18); |
| 415 | // data = RCBA32(0x1e18); |
| 416 | // data &= mask; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 417 | // if (smi1) |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 418 | // southbridge_smi_command(data); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 419 | // return; |
| 420 | } |
| 421 | // Fall through to debug |
| 422 | } |
| 423 | |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 424 | printk(BIOS_DEBUG, " trapped io address = 0x%x\n", |
| 425 | trap_cycle & 0xfffc); |
Angel Pons | 2aaf7c0 | 2020-09-24 18:03:18 +0200 | [diff] [blame] | 426 | for (i = 0; i < 4; i++) |
| 427 | if (IOTRAP(i)) |
| 428 | printk(BIOS_DEBUG, " TRAP = %d\n", i); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 429 | printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); |
| 430 | printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 431 | printk(BIOS_DEBUG, " read/write: %s\n", |
| 432 | (trap_cycle & (1 << 24)) ? "read" : "write"); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 433 | |
| 434 | if (!(trap_cycle & (1 << 24))) { |
| 435 | /* Write Cycle */ |
Elyes HAOUAS | 2a66dd2 | 2020-08-07 15:22:12 +0200 | [diff] [blame] | 436 | printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", RCBA32(0x1e18)); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 437 | } |
| 438 | #undef IOTRAP |
| 439 | } |
| 440 | |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 441 | typedef void (*smi_handler_t)(void); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 442 | |
| 443 | static smi_handler_t southbridge_smi[32] = { |
| 444 | NULL, // [0] reserved |
| 445 | NULL, // [1] reserved |
| 446 | NULL, // [2] BIOS_STS |
| 447 | NULL, // [3] LEGACY_USB_STS |
| 448 | southbridge_smi_sleep, // [4] SLP_SMI_STS |
| 449 | southbridge_smi_apmc, // [5] APM_STS |
| 450 | NULL, // [6] SWSMI_TMR_STS |
| 451 | NULL, // [7] reserved |
| 452 | southbridge_smi_pm1, // [8] PM1_STS |
| 453 | southbridge_smi_gpe0, // [9] GPE0_STS |
| 454 | southbridge_smi_gpi, // [10] GPI_STS |
| 455 | southbridge_smi_mc, // [11] MCSMI_STS |
| 456 | NULL, // [12] DEVMON_STS |
| 457 | southbridge_smi_tco, // [13] TCO_STS |
| 458 | southbridge_smi_periodic, // [14] PERIODIC_STS |
| 459 | NULL, // [15] SERIRQ_SMI_STS |
| 460 | NULL, // [16] SMBUS_SMI_STS |
| 461 | NULL, // [17] LEGACY_USB2_STS |
| 462 | NULL, // [18] INTEL_USB2_STS |
| 463 | NULL, // [19] reserved |
| 464 | NULL, // [20] PCI_EXP_SMI_STS |
| 465 | southbridge_smi_monitor, // [21] MONITOR_STS |
| 466 | NULL, // [22] reserved |
| 467 | NULL, // [23] reserved |
| 468 | NULL, // [24] reserved |
| 469 | NULL, // [25] EL_SMI_STS |
| 470 | NULL, // [26] SPI_STS |
| 471 | NULL, // [27] reserved |
| 472 | NULL, // [28] reserved |
| 473 | NULL, // [29] reserved |
| 474 | NULL, // [30] reserved |
| 475 | NULL // [31] reserved |
| 476 | }; |
| 477 | |
| 478 | /** |
| 479 | * @brief Interrupt handler for SMI# |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 480 | */ |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 481 | void southbridge_smi_handler(void) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 482 | { |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 483 | int i; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 484 | u32 smi_sts; |
| 485 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 486 | /* We need to clear the SMI status registers, or we won't see what's |
| 487 | * happening in the following calls. |
| 488 | */ |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 489 | smi_sts = clear_smi_status(); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 490 | |
| 491 | /* Call SMI sub handler for each of the status bits */ |
| 492 | for (i = 0; i < 31; i++) { |
| 493 | if (smi_sts & (1 << i)) { |
| 494 | if (southbridge_smi[i]) { |
Aaron Durbin | 29ffa54 | 2012-12-21 21:21:48 -0600 | [diff] [blame] | 495 | southbridge_smi[i](); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 496 | } else { |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 497 | printk(BIOS_DEBUG, |
Martin Roth | 2ed0aa2 | 2016-01-05 20:58:58 -0700 | [diff] [blame] | 498 | "SMI_STS[%d] occurred, but no " |
Duncan Laurie | 467f31d | 2013-03-08 17:00:37 -0800 | [diff] [blame] | 499 | "handler available.\n", i); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 500 | } |
| 501 | } |
| 502 | } |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 503 | } |